DC-DC Converter Design Phase Acceleration with Virtuoso UltraSim Simulator
|
|
|
- Avice Lane
- 6 years ago
- Views:
Transcription
1 DC-DC Converter Design Phase Acceleration with Virtuoso UltraSim Simulator Mohamed Bouhamame, Didier Depreeuw NXP Semiconductors Caen France
2 Outline Motivations DC-DC converter topology Implementation Ultrasim DC-DC converter setting Simulation & measurement results Conclusions 2
3 Motivations A Controllable high voltage DC-DC Converter High level of integration Low power consumption Tunable RF filter with High linearity and High selectivity 3
4 DC-DC converter topology V in Ck Ckn C s D 1 C C s D 2 D 3 C s C s C D n-1 D n C C C out C V = V V + N * * V -V - out in d C + C ck d (C I out + C R L V out Where: s s - N is the number of commutating stages (N=20) - f is the operating frequency of the charge pump (f=16mhz) - C s is the stray capacitance at each node (1fF) - I out is the DC current required to drive the load for a given output voltage How to decrease the output voltage rapidly? ) * f 4
5 Why Tunable RF Filter? Tracking filter used in traditional TV tuner f max f min = C vmax C vmin ( C p >> C v Antenna ) L 1 L 2 C v C p R V tune =0.8V..28V Provider by the DC-DC Tunable Filters are needed because of : High dynamic range of the received signals Wide input bandwidth (F=[50MHz 870MHz]) 5
6 Implementation DC-DC UP V out D 1 D 2 D 3 DC-DC DOWN Ckup n Ckup p C 1 C 2 C 3 M diodes N diodes D 3 D 2 D 1 C Fringe capacitor Ckdw n Ckdw p C 3 C 2 C 1 Dickson Charge pump is implemented in 2.8V Bi-CMOS 0.25µm Technology (Break down voltage for collector substrate is B vcs0 =80V ) Stray capacitance C s has been reduced by the shielding done by the poly layer V out < (N+M)*V d (V d is the forward bias voltage of the diode) 6
7 Implementation R C V out =V tune 15M 1M V ck V ck Ckn Ck Resistors used have a breakdown voltage more than 200V and have a sheet resistance of 2000 /square + - V ref DAC Prog V ref enables to tune the center frequency of the tracking filter(vref =Vout/16) Spectre simulation time is really long! (40000 switching periods are required to capture the power-up (the output voltage starts from 0 volt to reach the steady state of 24 volts) How to decrease the time simulation? 7
8 What Is Ultrasim? UltraSim is a fast-spice hierarchical circuit simulator (Transistor level) which combines a variety of simulation technologies to allow high-capacity simulation of memories, digital, analog, RF and mixed-signal ICs with spicelike accuracy 8
9 Ultrasim : Fast SPICE Technology Cadence s Slide 9
10 Transistor Level Circuit Simulation Overview SPICE: Fast-SPICE: Hier-SPICE: Technologies: Compact models Sparse Matrix Solver Time step, Newton-raphson Technologies: Simplified Models: PWL, Table Matrix Partitioning Event-driven Multi-rate RC reduction Technologies: Fast-SPICE technologies Hierarchy Isomorphism Applications: Block design Analog/MS Pre Layout Tran, AC, Noise, RF 50K device capacity Applications: Large Block Design MS/Digital/Memory Pre-/Post Layout Tran 1M device capacity Applications: Full-chip simulation Analog/MS/D/Memory Pre-/Post Layout Tran 1B+ device capacity 10
11 UltraSim 3rd Generation Transistor Level Simulator Cadence s Slide 11
12 UltraSim Simulation Modes 12
13 UltraSim Multirate simulation Different time steps for partitions High frequency partition : small time step Small frequency partition : bigger time step 13
14 UltraSim Speed Options Cadence s slide 14
15 UltraSim Simulation Models Overview The same study of the Id_Vd & Id_Vg differences Is under investigation Simkit MN11 and MOS9 are supported in Ultrasim for the following models: DF DA A Spice 15
16 DC-DC converter setting the server define below is used : OS: Linux ELhugemem i686 Memory: available GB physical GB Swap: available GB physical GB CPU: CPU0 AMD Opteron(tm) Processor MHz CPU1 AMD Opteron(tm) Processor MHz cadence_ic cadence_ius 5.5.s001 cadence_mmsim We need to set vdd=1.8 to get accurate table model creation!.usim_opt progress_p=1 vdd=1.8 Circuit inventory: Nodes 307 Equations 796 bjt capacitor 57 diode 101 isource 2 juncap 696 mos1100e 278 phy_res 78 resistor 15 vcvs 2 vsource 6 16
17 Simulation & measurement results Vout (V) Vout (V) Ultrasim versus Spectre Less than 0.003% diff spectre ultrasim spectre ultrasim 5 5 measurement 0 0 0,5 1 1,5 2 t (ms) 0 0 0,4 0,8 1,2 1,6 2 t (ms) Using Ultrasim, the circuit simulation time is six times faster with the same accuracy compare to Spectre Simulation time result using local setting 17
18 Measurement results Vout(V) T=Tnom T=85C T=-20C 1,4 1,75 2,1 2,45 2,8 Voltage output range Output current max Supply current max 0V 30 V 8 µa 1mA Vref (V) When I out =8µA, f=16mhz, N=20, V d =0.6V, C=700fF and C s =1fF, V out =32V The temperature dependency of the output voltage is negligible 18
19 Die photograph Voltage regulation, Clock generation DC/DC UP DC/DC DOWN Technology : 0.25µm Bi-CMOS ft=40ghz Area : 620µm*262µm 19
20 Ultrasim Pros & Cons Pros Time saving with the same accuracy Factor 6 with DC DC Converter Would have been a great help on time saving during the design phase Cons Spectre is the reference tool, take care of ultrasim simulation results of a global system for which spectre simulation is not possible Sometimes prohibitive simulation time due to not optimized local settings : use the activity report Transient analog signal, no RF capabilities Bipolar transistors not taken into account in the table model simplification Ultrasim-Verilog : not possible to save / load an intermediate step 20
21 Conclusions A Controllable High Voltage DC-DC converter has been presented A novel solution has been used to decrease the output voltage rapidly The new discharge system solves the problem of the high tuning voltage requirement for MEMS and SMD variable capacitors The forward bias voltage V d is the main limitation of the output voltage Ultrasim have been a great help on time saving during the design phase Ultrasim allows the exploration of more design configurations, the accuracy is excellent for such Bi-CMOS circuit Ultrasim simulator is a very efficient to make possible bottom-up verification for all IC builder 21
22 Acknowledgements Jean Robert Tourret, NXP Semiconductors Luca Lococo, NXP Semiconductors Serge Toutain, IREENA André Baguenier, Cadence 22
23 Thanks for your attention! Any Question?
THE SPICE BOOK. Andrei Vladimirescu. John Wiley & Sons, Inc. New York Chichester Brisbane Toronto Singapore
THE SPICE BOOK Andrei Vladimirescu John Wiley & Sons, Inc. New York Chichester Brisbane Toronto Singapore CONTENTS Introduction SPICE THE THIRD DECADE 1 1.1 THE EARLY DAYS OF SPICE 1 1.2 SPICE IN THE 1970s
DESIGN AND ANALYSIS OF LOW POWER CHARGE PUMP CIRCUIT FOR PHASE-LOCKED LOOP
DESIGN AND ANALYSIS OF LOW POWER CHARGE PUMP CIRCUIT FOR PHASE-LOCKED LOOP 1 B. Praveen Kumar, 2 G.Rajarajeshwari, 3 J.Anu Infancia 1, 2, 3 PG students / ECE, SNS College of Technology, Coimbatore, (India)
PMOS-based Integrated Charge Pumps with Extended Voltage Range in Standard CMOS Technology
PMOS-based Integrated Charge Pumps with Extended Voltage Range in Standard CMOS Technology by Jingqi Liu A Thesis presented to The University of Guelph In partial fulfillment of requirements for the degree
Accuracy and Speed Performance of HiSIM Versions 231 and 240
Accuracy and Speed Performance of HiSIM Versions 231 and 240 H.J. Mattausch, M. Miura-Mattausch, N. Sadachika, M. Miyake Graduate School of Advanced Sciences of Matter, Hiroshima University T. Iizuka NEC
Chapter 3 Novel Digital-to-Analog Converter with Gamma Correction for On-Panel Data Driver
Chapter 3 Novel Digital-to-Analog Converter with Gamma Correction for On-Panel Data Driver 3.1 INTRODUCTION As last chapter description, we know that there is a nonlinearity relationship between luminance
Figure 1. Main window (Common Interface Window), CIW opens and from the pull down menus you can start your design. Figure 2.
Running Cadence Once the Cadence environment has been setup you can start working with Cadence. You can run cadence from your directory by typing Figure 1. Main window (Common Interface Window), CIW opens
! Review: MOS IV Curves and Switch Model. ! MOS Device Layout. ! Inverter Layout. ! Gate Layout and Stick Diagrams. ! Design Rules. !
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 3: January 21, 2016 MOS Fabrication pt. 2: Design Rules and Layout Lecture Outline! Review: MOS IV Curves and Switch Model! MOS Device Layout!
ESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 3: January 21, 2016 MOS Fabrication pt. 2: Design Rules and Layout Penn ESE 570 Spring 2016 Khanna Adapted from GATech ESE3060 Slides Lecture
NOVEMBER 29, 2017 COURSE PROJECT: CMOS TRANSIMPEDANCE AMPLIFIER ECG 720 ADVANCED ANALOG IC DESIGN ERIC MONAHAN
NOVEMBER 29, 2017 COURSE PROJECT: CMOS TRANSIMPEDANCE AMPLIFIER ECG 720 ADVANCED ANALOG IC DESIGN ERIC MONAHAN 1.Introduction: CMOS Transimpedance Amplifier Avalanche photodiodes (APDs) are highly sensitive,
Lecture 300 Low Voltage Op Amps (3/28/10) Page 300-1
Lecture 300 Low Voltage Op Amps (3/28/10) Page 300-1 LECTURE 300 LOW VOLTAGE OP AMPS LECTURE ORGANIZATION Outline Introduction Low voltage input stages Low voltage gain stages Low voltage bias circuits
MICROWIND2 DSCH2 8. Converters /11/00
8-9 05/11/00 Fig. 8-7. Effect of sampling The effect of sample and hold is illustrated in figure 8-7. When sampling, the transmission gate is turned on so that the sampled data DataOut reaches the value
Linear Voltage Regulators Power supplies and chargers SMM Alavi, SBU, Fall2017
Linear Voltage Regulator LVRs can be classified based on the type of the transistor that is used as the pass element. The bipolar junction transistor (BJT), field effect transistor (FET), or metal oxide
UNIT-III POWER ESTIMATION AND ANALYSIS
UNIT-III POWER ESTIMATION AND ANALYSIS In VLSI design implementation simulation software operating at various levels of design abstraction. In general simulation at a lower-level design abstraction offers
DESIGN AND SIMULATION OF A HIGH PERFORMANCE CMOS VOLTAGE DOUBLERS USING CHARGE REUSE TECHNIQUE
Journal of Engineering Science and Technology Vol. 12, No. 12 (2017) 3344-3357 School of Engineering, Taylor s University DESIGN AND SIMULATION OF A HIGH PERFORMANCE CMOS VOLTAGE DOUBLERS USING CHARGE
! Review: MOS IV Curves and Switch Model. ! MOS Device Layout. ! Inverter Layout. ! Gate Layout and Stick Diagrams. ! Design Rules. !
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 3: January 21, 2017 MOS Fabrication pt. 2: Design Rules and Layout Lecture Outline! Review: MOS IV Curves and Switch Model! MOS Device Layout!
Reduction of Peak Input Currents during Charge Pump Boosting in Monolithically Integrated High-Voltage Generators
Reduction of Peak Input Currents during Charge Pump Boosting in Monolithically Integrated High-Voltage Generators Jan Doutreloigne Abstract This paper describes two methods for the reduction of the peak
Design of Rail-to-Rail Op-Amp in 90nm Technology
IJSTE - International Journal of Science Technology & Engineering Volume 1 Issue 2 August 2014 ISSN(online) : 2349-784X Design of Rail-to-Rail Op-Amp in 90nm Technology P R Pournima M.Tech Electronics
Appendix. RF Transient Simulator. Page 1
Appendix RF Transient Simulator Page 1 RF Transient/Convolution Simulation This simulator can be used to solve problems associated with circuit simulation, when the signal and waveforms involved are modulated
ESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 3: January 24, 2019 MOS Fabrication pt. 2: Design Rules and Layout Penn ESE 570 Spring 2019 Khanna Jack Keil Wolf Lecture http://www.ese.upenn.edu/about-ese/events/wolf.php
Lecture 190 CMOS Technology, Compatible Devices (10/28/01) Page 190-1
Lecture 190 CMOS Technology, Compatible Devices (10/28/01) Page 190-1 LECTURE 190 CMOS TECHNOLOGY-COMPATIBLE DEVICES (READING: Text-Sec. 2.9) INTRODUCTION Objective The objective of this presentation is
YOUR VIDEO TITLE POWER DISTRIBUTION FOR
YOUR VIDEO TITLE POWER DISTRIBUTION FOR GOES SOC AND FPGA HERE APPLICATIONS THE WHAT SUBTITLE SPECS GOES TO LOOK HERE FOR Detailed Agenda Power Distribution for SoC and FPGA applications: Microprocessors
DESIGN OF A NOVEL CURRENT BALANCED VOLTAGE CONTROLLED DELAY ELEMENT
DESIGN OF A NOVEL CURRENT BALANCED VOLTAGE CONTROLLED DELAY ELEMENT Pooja Saxena 1, Sudheer K. M 2, V. B. Chandratre 2 1 Homi Bhabha National Institute, Mumbai 400094 2 Electronics Division, Bhabha Atomic
Hot Topics and Cool Ideas in Scaled CMOS Analog Design
Engineering Insights 2006 Hot Topics and Cool Ideas in Scaled CMOS Analog Design C. Patrick Yue ECE, UCSB October 27, 2006 Slide 1 Our Research Focus High-speed analog and RF circuits Device modeling,
Synthesis of Optimal On-Chip Baluns
Synthesis of Optimal On-Chip Baluns Sharad Kapur, David E. Long and Robert C. Frye Integrand Software, Inc. Berkeley Heights, New Jersey Yu-Chia Chen, Ming-Hsiang Cho, Huai-Wen Chang, Jun-Hong Ou and Bigchoug
DESIGN OF A FULLY DIFFERENTIAL HIGH-SPEED HIGH-PRECISION AMPLIFIER
DESIGN OF A FULLY DIFFERENTIAL HIGH-SPEED HIGH-PRECISION AMPLIFIER Mayank Gupta mayank@ee.ucla.edu N. V. Girish envy@ee.ucla.edu Design I. Design II. University of California, Los Angeles EE215A Term Project
Overview of Linear & Switching Regulators
Overview of Linear & Switching Regulators Vahe Caliskan, Sc.D. Senior Technical Expert Motorola Automotive Government & Enterprise Mobility Solutions September 15, 2005 Vahe Caliskan, Sc.D. (g17823) Overview
ANALYSIS, DESIGN, AND IMPLEMENTATION OF INTEGRATED CHARGE PUMPS WITH HIGH PERFORMANCE
ANALYSIS, DESIGN, AND IMPLEMENTATION OF INTEGRATED CHARGE PUMPS WITH HIGH PERFORMANCE A Thesis Presented to The Faculty of Graduate Studies of The University of Guelph by YOUNIS ALLASASMEH In partial fulfilment
On Chip Active Decoupling Capacitors for Supply Noise Reduction for Power Gating and Dynamic Dual Vdd Circuits in Digital VLSI
ELEN 689 606 Techniques for Layout Synthesis and Simulation in EDA Project Report On Chip Active Decoupling Capacitors for Supply Noise Reduction for Power Gating and Dynamic Dual Vdd Circuits in Digital
Jack Keil Wolf Lecture. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Lecture Outline. MOSFET N-Type, P-Type.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Jack Keil Wolf Lecture Lec 3: January 24, 2019 MOS Fabrication pt. 2: Design Rules and Layout http://www.ese.upenn.edu/about-ese/events/wolf.php
Fixing Antenna Problem by Dynamic Diode Dropping and Jumper Insertion
Fixing Antenna Problem by Dynamic Dropping and Jumper Insertion Peter H. Chen and Sunil Malkani Chun-Mou Peng James Lin TeraLogic, Inc. International Tech. Univ. National Semi. Corp. 1240 Villa Street
Lecture 7: Components of Phase Locked Loop (PLL)
Lecture 7: Components of Phase Locked Loop (PLL) CSCE 6933/5933 Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides are borrowed from various books, websites, authors pages,
Dr.-Ing. Ulrich L. Rohde
Dr.-Ing. Ulrich L. Rohde Noise in Oscillators with Active Inductors Presented to the Faculty 3 : Mechanical engineering, Electrical engineering and industrial engineering, Brandenburg University of Technology
A New CMOS-DC/DC-Step-Up Converter for up to 2 mw Enduring Loads
A New CMOS-DC/DC-Step-Up Converter for up to mw Enduring Loads DANIEL BATAS, KLAUS SCHUMACHER Dept of Microelectronics University of Dortmund Dortmund GERMANY http://www-ims.e-technik.uni-dortmund.de Abstract:
HA-2600, HA Features. 12MHz, High Input Impedance Operational Amplifiers. Applications. Pinouts. Ordering Information
HA26, HA26 September 998 File Number 292.3 2MHz, High Input Impedance Operational Amplifiers HA26/26 are internally compensated bipolar operational amplifiers that feature very high input impedance (MΩ,
Short Channel Bandgap Voltage Reference
Short Channel Bandgap Voltage Reference EE-584 Final Report Authors: Thymour Legba Yugu Yang Chris Magruder Steve Dominick Table of Contents Table of Figures... 3 Abstract... 4 Introduction... 5 Theory
Low Cost 10-Bit Monolithic D/A Converter AD561
a FEATURES Complete Current Output Converter High Stability Buried Zener Reference Laser Trimmed to High Accuracy (1/4 LSB Max Error, AD561K, T) Trimmed Output Application Resistors for 0 V to +10 V, 5
A CMOS Analog Front-End Circuit for MEMS Based Temperature Sensor
Technology Volume 1, Issue 2, October-December, 2013, pp. 01-06, IASTER 2013 www.iaster.com, Online: 2347-6109, Print: 2348-0017 A CMOS Analog Front-End Circuit for MEMS Based Temperature Sensor Bollam
CHAPTER 6 DIGITAL CIRCUIT DESIGN USING SINGLE ELECTRON TRANSISTOR LOGIC
94 CHAPTER 6 DIGITAL CIRCUIT DESIGN USING SINGLE ELECTRON TRANSISTOR LOGIC 6.1 INTRODUCTION The semiconductor digital circuits began with the Resistor Diode Logic (RDL) which was smaller in size, faster
DATASHEET CADENCE QRC EXTRACTION
DATASHEET Cadence QRC Etraction, the industry s premier 3D fullchip parasitic etractor that is independent of design style or flow, is a fast and accurate RLCK etraction solution used during design implementation
Reading. Lecture 17: MOS transistors digital. Context. Digital techniques:
Reading Lecture 17: MOS transistors digital Today we are going to look at the analog characteristics of simple digital devices, 5. 5.4 And following the midterm, we will cover PN diodes again in forward
Electronic Noise. Analog Dynamic Range
Electronic Noise Dynamic range in the analog domain Resistor noise Amplifier noise Maximum signal levels Tow-Thomas Biquad noise example Implications on power dissipation EECS 247 Lecture 4: Dynamic Range
A Simple On-Chip Automatic Tuning Circuit for Continuous-Time Filter
Int. J. Communications, Network and System Sciences, 010, 3, 66-71 doi:10.436/ijcns.010.31009 Published Online January 010 (http://www.scirp.org/journal/ijcns/). A Simple On-Chip Automatic Tuning Circuit
Coherent Detection Gradient Descent Adaptive Control Chip
MEP Research Program Test Report Coherent Detection Gradient Descent Adaptive Control Chip Requested Fabrication Technology: IBM SiGe 5AM Design No: 73546 Fabrication ID: T57WAD Design Name: GDPLC Technology
Preliminary Exam, Fall 2013 Department of Electrical and Computer Engineering University of California, Irvine EECS 170B
Preliminary Exam, Fall 2013 Department of Electrical and Computer Engineering University of California, Irvine EECS 170B Problem 1. Consider the following circuit, where a saw-tooth voltage is applied
EE241 - Spring 2013 Advanced Digital Integrated Circuits. Projects. Groups of 3 Proposals in two weeks (2/20) Topics: Lecture 5: Transistor Models
EE241 - Spring 2013 Advanced Digital Integrated Circuits Lecture 5: Transistor Models Projects Groups of 3 Proposals in two weeks (2/20) Topics: Soft errors in datapaths Soft errors in memory Integration
CMOS Operational Amplifier
The George Washington University Department of Electrical and Computer Engineering Course: ECE218 Instructor: Mona E. Zaghloul Students: Shunping Wang Yiping (Neil) Tsai Data: 05/14/07 Introduction In
Tsung-Chu Huang. Department of Electronic Engineering National Changhua University of Education /10/4-5 TCH NCUE
Digital IC Design Tsung-Chu Huang Department of Electronic Engineering National Changhua University of Education Email: tch@cc.ncue.edu.tw 2004/10/4-5 Page 1 Circuit Simulation Tools 1. Switch Level: Verilog,
A radiation tolerant, low-power cryogenic capable CCD readout system:
A radiation tolerant, low-power cryogenic capable CCD readout system: Enabling focal-plane mounted CCD read-out for ground or space applications with a pair of ASICs. Overview What do we want to read out
! MOS Device Layout. ! Inverter Layout. ! Gate Layout and Stick Diagrams. ! Design Rules. ! Standard Cells. ! CMOS Process Enhancements
EE 570: igital Integrated Circuits and VLI Fundamentals Lec 3: January 18, 2018 MO Fabrication pt. 2: esign Rules and Layout Lecture Outline! MO evice Layout! Inverter Layout! Gate Layout and tick iagrams!
Lecture 4. The CMOS Inverter. DC Transfer Curve: Load line. DC Operation: Voltage Transfer Characteristic. Noise in Digital Integrated Circuits
Noise in Digital Integrated Circuits Lecture 4 The CMOS Inverter i(t) v(t) V DD Peter Cheung Department of Electrical & Electronic Engineering Imperial College London URL: www.ee.ic.ac.uk/pcheung/ E-mail:
TFT-LCD DC/DC Converter with Integrated Backlight LED Driver
TFT-LCD DC/DC Converter with Integrated Backlight LED Driver Description The is a step-up current mode PWM DC/DC converter (Ch-1) built in an internal 1.6A, 0.25Ω power N-channel MOSFET and integrated
Measurement Results for a High Throughput MCM
Measurement Results for a High Throughput MCM Funding: Paul Franzon Toby Schaffer, Alan Glaser, Steve Lipa North Carolina State University paulf@ncsu.edu www.ece.ncsu.edu/erl Outline > Heterogeneous System
ECE 415/515 ANALOG INTEGRATED CIRCUIT DESIGN
ECE 415/515 ANALOG INTEGRATED CIRCUIT DESIGN OPAMP DESIGN AND SIMULATION Vishal Saxena OPAMP DESIGN PROJECT R 2 v out v in /2 R 1 C L v in v out V CM R L V CM C L V CM -v in /2 R 1 C L (a) (b) R 2 ECE415/EO
Pulsed Power Engineering Circuit Simulation
Pulsed Power Engineering Circuit Simulation January 12-16, 2009 Craig Burkhart, PhD Power Conversion Department SLAC National Accelerator Laboratory Circuit Simulation for Pulsed Power Applications Uses
Increasing Performance Requirements and Tightening Cost Constraints
Maxim > Design Support > Technical Documents > Application Notes > Power-Supply Circuits > APP 3767 Keywords: Intel, AMD, CPU, current balancing, voltage positioning APPLICATION NOTE 3767 Meeting the Challenges
AN increasing number of video and communication applications
1470 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 9, SEPTEMBER 1997 A Low-Power, High-Speed, Current-Feedback Op-Amp with a Novel Class AB High Current Output Stage Jim Bales Abstract A complementary
LECTURE 19 DIFFERENTIAL AMPLIFIER
Lecture 19 Differential Amplifier (6/4/14) Page 191 LECTURE 19 DIFFERENTIAL AMPLIFIER LECTURE ORGANIZATION Outline Characterization of a differential amplifier Differential amplifier with a current mirror
22. VLSI in Communications
22. VLSI in Communications State-of-the-art RF Design, Communications and DSP Algorithms Design VLSI Design Isolated goals results in: - higher implementation costs - long transition time between system
Full-Custom Design Fractional Step-Down Charge Pump DC-DC Converter with Digital Control Implemented in 90nm CMOS Technology
Full-Custom Design Fractional Step-Down Charge Pump DC-DC Converter with Digital Control Implemented in 90nm CMOS Technology Jhon Ray M. Esic, Van Louven A. Buot, and Jefferson A. Hora Microelectronics
A HIGH EFFICIENCY CHARGE PUMP FOR LOW VOLTAGE DEVICES
A HIGH EFFICIENCY CHARGE PUMP FOR LOW VOLTAGE DEVICES Aamna Anil 1 and Ravi Kumar Sharma 2 1 Department of Electronics and Communication Engineering Lovely Professional University, Jalandhar, Punjab, India
A Micro-Power Mixed Signal IC for Battery-Operated Burglar Alarm Systems
A Micro-Power Mixed Signal IC for Battery-Operated Burglar Alarm Systems Silvio Bolliri Microelectronic Laboratory, Department of Electrical and Electronic Engineering University of Cagliari bolliri@diee.unica.it
Microcontroller Systems. ELET 3232 Topic 13: Load Analysis
Microcontroller Systems ELET 3232 Topic 13: Load Analysis 1 Objective To understand hardware constraints on embedded systems Define: Noise Margins Load Currents and Fanout Capacitive Loads Transmission
Lecture 10: Accelerometers (Part I)
Lecture 0: Accelerometers (Part I) ADXL 50 (Formerly the original ADXL 50) ENE 5400, Spring 2004 Outline Performance analysis Capacitive sensing Circuit architectures Circuit techniques for non-ideality
VCO Design Using SpectreRF. SpectreRF Workshop. VCO Design Using SpectreRF MMSIM6.0USR2. November
SpectreRF Workshop VCO Design Using SpectreRF MMSIM6.0USR2 November 2005 November 2005 1 Contents Voltage Controlled Oscillator Design Measurements... 3 Purpose... 3 Audience... 3 Overview... 3 Introduction
CHAPTER 6 PHASE LOCKED LOOP ARCHITECTURE FOR ADC
138 CHAPTER 6 PHASE LOCKED LOOP ARCHITECTURE FOR ADC 6.1 INTRODUCTION The Clock generator is a circuit that produces the timing or the clock signal for the operation in sequential circuits. The circuit
ADC0808/ADC Bit µp Compatible A/D Converters with 8-Channel Multiplexer
ADC0808/ADC0809 8-Bit µp Compatible A/D Converters with 8-Channel Multiplexer General Description The ADC0808, ADC0809 data acquisition component is a monolithic CMOS device with an 8-bit analog-to-digital
Electronics Development for psec Time-of. of-flight Detectors. Enrico Fermi Institute University of Chicago. Fukun Tang
Electronics Development for psec Time-of of-flight Detectors Fukun Tang Enrico Fermi Institute University of Chicago With Karen Byrum and Gary Drake (ANL) Henry Frisch, Mary Heintz and Harold Sanders (UC)
A RESISTORLESS SWITCHED BANDGAP REFERENCE TOPOLOGY
A RESISTORLESS SWITCHED BANDGAP REFERENCE TOPOLOGY Hamilton Klimach, Moacir F. C. Monteiro Arthur L. T. Costa, Sergio Bampi Graduate Program on Microelectronics Electrical Engineering Department & Informatics
A high PSRR Class-D audio amplifier IC based on a self-adjusting voltage reference
A high PSRR Class-D audio amplifier IC based on a self-adjusting voltage reference Alexandre Huffenus, Gaël Pillonnet, Nacer Abouchi, Frédéric Goutti, Vincent Rabary, Robert Cittadini To cite this version:
A 24 V Chopper Offset-Stabilized Operational Amplifier with Symmetrical RC Notch Filters having sub-10 µv offset and over-120db CMRR
ROMANIAN JOURNAL OF INFORMATION SCIENCE AND TECHNOLOGY Volume 20, Number 4, 2017, 301 312 A 24 V Chopper Offset-Stabilized Operational Amplifier with Symmetrical RC Notch Filters having sub-10 µv offset
An Integrated, Dynamically Adaptive Energy-Management Framework for Linear RF Power Amplifiers
An Integrated, Dynamically Adaptive Energy-Management Framework for Linear RF Power Amplifiers Georgia Tech Analog Consortium Biranchinath Sahu Advisor: Prof. Gabriel A. Rincón-Mora Georgia Tech Analog
Substrate Coupling in RF Analog/Mixed Signal IC Design: A Review
Substrate Coupling in RF Analog/Mixed Signal IC Design: A Review Ashish C Vora, Graduate Student, Rochester Institute of Technology, Rochester, NY, USA. Abstract : Digital switching noise coupled into
Interconnect-Power Dissipation in a Microprocessor
4/2/2004 Interconnect-Power Dissipation in a Microprocessor N. Magen, A. Kolodny, U. Weiser, N. Shamir Intel corporation Technion - Israel Institute of Technology 4/2/2004 2 Interconnect-Power Definition
Design of 1.8V, 72MS/s 12 Bit Pipeline ADC in 0.18µm Technology
Design of 1.8V, 72MS/s 12 Bit Pipeline ADC in 0.18µm Technology Ravi Kumar 1, Seema Kanathe 2 ¹PG Scholar, Department of Electronics and Communication, Suresh GyanVihar University, Jaipur, India ²Assistant
Low Power Design for Systems on a Chip. Tutorial Outline
Low Power Design for Systems on a Chip Mary Jane Irwin Dept of CSE Penn State University (www.cse.psu.edu/~mji) Low Power Design for SoCs ASIC Tutorial Intro.1 Tutorial Outline Introduction and motivation
Lecture 020 ECE4430 Review II (1/5/04) Page 020-1
Lecture 020 ECE4430 Review II (1/5/04) Page 020-1 LECTURE 020 ECE 4430 REVIEW II (READING: GHLM - Chap. 2) Objective The objective of this presentation is: 1.) Identify the prerequisite material as taught
A CMOS Frequency Synthesizer with an Injection-Locked Frequency Divider for a 5 GHz Wireless LAN Receiver. Hamid Rategh
A CMOS Frequency Synthesizer with an Injection-Locked Frequency Divider for a 5 GHz Wireless LAN Receiver Hamid Rategh Center for Integrated Systems Stanford University OUTLINE Motivation Introduction
Design of a low voltage,low drop-out (LDO) voltage cmos regulator
Design of a low,low drop-out (LDO) cmos regulator Chaithra T S Ashwini Abstract- In this paper a low, low drop-out (LDO) regulator design procedure is proposed and implemented using 0.25 micron CMOS process.
Lecture 020 ECE4430 Review II (1/5/04) Page 020-1
Lecture 020 ECE4430 Review II (1/5/04) Page 020-1 LECTURE 020 ECE 4430 REVIEW II (READING: GHLM - Chap. 2) Objective The objective of this presentation is: 1.) Identify the prerequisite material as taught
Tuesday, February 1st, 9:15 12:00. Snorre Aunet Nanoelectronics group Department of Informatics University of Oslo
Bandgap references, sampling switches Tuesday, February 1st, 9:15 12:00 Snorre Aunet (sa@ifi.uio.no) Nanoelectronics group Department of Informatics University of Oslo Outline Tuesday, February 1st 11.11
A 5GHz, 32mW CMOS Frequency Synthesizer with an Injection Locked Frequency Divider. Hamid Rategh, Hirad Samavati, Thomas Lee
A 5GHz, 32mW CMOS Frequency Synthesizer with an Injection Locked Frequency Divider Hamid Rategh, Hirad Samavati, Thomas Lee OUTLINE motivation introduction synthesizer architecture synthesizer building
A 1.2-to-1.4 GHz low-jitter frequency synthesizer for GPS application
Journal of Chongqing University (English Edition) [ISSN 1671-8224] Vol. 12 No. 2 June 2013 doi:10.11835/j.issn.1671-8224.2013.02.008 To cite this article: HU Zheng-fei, HUANG Min-di, ZHANG Li. A 1.2-to-1.4
THE BASIC BUILDING BLOCKS OF 1.8 GHZ PLL
THE BASIC BUILDING BLOCKS OF 1.8 GHZ PLL IN CMOS TECHNOLOGY L. Majer, M. Tomáška,V. Stopjaková, V. Nagy, and P. Malošek Department of Microelectronics, Slovak Technical University, Ilkovičova 3, Bratislava,
Layout-Oriented Synthesis of High Performance Analog Circuits
-Oriented Synthesis of High Performance Analog Circuits Mohamed Dessouky, Marie-Minerve Louërat Université Paris VI (55/65) Laboratoire LIP6-ASIM 4 Place Jussieu. 75252 Paris Cedex 05. France Mohamed.Dessouky@lip6.fr
SiNANO-NEREID Workshop:
SiNANO-NEREID Workshop: Towards a new NanoElectronics Roadmap for Europe Leuven, September 11 th, 2017 WP3/Task 3.2 Connectivity RF and mmw Design Outline Connectivity, what connectivity? High data rates
MICROCONTROLLER BASED BOOST PID MUNAJAH BINTI MOHD RUBAEE
MICROCONTROLLER BASED BOOST PID MUNAJAH BINTI MOHD RUBAEE This thesis is submitted as partial fulfillment of the requirement for the award of Bachelor of Electrical Engineering (Power System) Faculty of
1 FUNDAMENTAL CONCEPTS What is Noise Coupling 1
Contents 1 FUNDAMENTAL CONCEPTS 1 1.1 What is Noise Coupling 1 1.2 Resistance 3 1.2.1 Resistivity and Resistance 3 1.2.2 Wire Resistance 4 1.2.3 Sheet Resistance 5 1.2.4 Skin Effect 6 1.2.5 Resistance
A Switched-Capacitor Band-Pass Biquad Filter Using a Simple Quasi-unity Gain Amplifier
A Switched-Capacitor Band-Pass Biquad Filter Using a Simple Quasi-unity Gain Amplifier Hugo Serra, Nuno Paulino, and João Goes Centre for Technologies and Systems (CTS) UNINOVA Dept. of Electrical Engineering
Due to the absence of internal nodes, inverter-based Gm-C filters [1,2] allow achieving bandwidths beyond what is possible
![Due to the absence of internal nodes, inverter-based Gm-C filters [1,2] allow achieving bandwidths beyond what is possible](/thumbs/73/68507481.jpg "Due to the absence of internal nodes, inverter-based Gm-C filters [1,2] allow achieving bandwidths beyond what is possible")
A Forward-Body-Bias Tuned 450MHz Gm-C 3 rd -Order Low-Pass Filter in 28nm UTBB FD-SOI with >1dBVp IIP3 over a 0.7-to-1V Supply Joeri Lechevallier 1,2, Remko Struiksma 1, Hani Sherry 2, Andreia Cathelin
Advanced Operational Amplifiers
IsLab Analog Integrated Circuit Design OPA2-47 Advanced Operational Amplifiers כ Kyungpook National University IsLab Analog Integrated Circuit Design OPA2-1 Advanced Current Mirrors and Opamps Two-stage
Lecture #29. Moore s Law
Lecture #29 ANNOUNCEMENTS HW#15 will be for extra credit Quiz #6 (Thursday 5/8) will include MOSFET C-V No late Projects will be accepted after Thursday 5/8 The last Coffee Hour will be held this Thursday
Mixed-Signal Simulation of Digitally Controlled Switching Converters
Mixed-Signal Simulation of Digitally Controlled Switching Converters Aleksandar Prodić and Dragan Maksimović Colorado Power Electronics Center Department of Electrical and Computer Engineering University
A 15.5 db, Wide Signal Swing, Dynamic Amplifier Using a Common- Mode Voltage Detection Technique
A 15.5 db, Wide Signal Swing, Dynamic Amplifier Using a Common- Mode Voltage Detection Technique James Lin, Masaya Miyahara and Akira Matsuzawa Tokyo Institute of Technology, Japan Matsuzawa & Okada Laḃ
Lecture 350 Low Voltage Op Amps (3/26/02) Page 350-1
Lecture 350 Low Voltage Op Amps (3/26/02) Page 3501 LECTURE 350 LOW VOLTAGE OP AMPS (READING: AH 415432) Objective The objective of this presentation is: 1.) How to design standard circuit blocks with
NOVEL OSCILLATORS IN SUBTHRESHOLD REGIME
NOVEL OSCILLATORS IN SUBTHRESHOLD REGIME Neeta Pandey 1, Kirti Gupta 2, Rajeshwari Pandey 3, Rishi Pandey 4, Tanvi Mittal 5 1, 2,3,4,5 Department of Electronics and Communication Engineering, Delhi Technological
Fractional- N PLL with 90 Phase Shift Lock and Active Switched- Capacitor Loop Filter
J. Park, F. Maloberti: "Fractional-N PLL with 90 Phase Shift Lock and Active Switched-Capacitor Loop Filter"; Proc. of the IEEE Custom Integrated Circuits Conference, CICC 2005, San Josè, 21 September
SINGLE-INDUCTOR MULTIPLE-OUTPUT DC-DC CONVERTERS
SINGLE-INDUCTOR MULTIPLE-OUTPUT DC-DC CONVERTERS Massimiliano Belloni, Edoardo Bonizzoni, Franco Maloberti University of Pavia Department of Electronics Via Ferrata, 1-27100 Pavia - ITALY [massimiliano.belloni,
Negative high voltage DC-DC converter using a New Cross-coupled Structure
Negative high voltage DC-DC converter using a New Cross-coupled Structure Jun Zhao 1, Kyung Ki Kim 2 and Yong-Bin Kim 3 1 Marvell Technology, USA 2 Department of Electronic Engineering, Daegu University,
Analysis and Design of a 1GHz PLL for Fast Phase and Frequency Acquisition
Analysis and Design of a 1GHz PLL for Fast Phase and Frequency Acquisition P. K. Rout, B. P. Panda, D. P. Acharya and G. Panda 1 Department of Electronics and Communication Engineering, School of Electrical
Department of Electrical Engineering IIT Madras
Department of Electrical Engineering IIT Madras Sample Questions on Semiconductor Devices EE3 applicants who are interested to pursue their research in microelectronics devices area (fabrication and/or