Double Edge Class BD Hybrid DPWM Implementation Using Linearized LBDD Algorithm

Transcription

1 Double Edge Class BD Hybrid DPWM Implemenaion Using Linearized LBDD Algorihm Jacek Jasielski, Sanisław Kua, Wiold Machowski, Ireneusz Brzozowski Deparmen of Elecronics AGH Universiy of Science and Technology Kraków, Poland Absrac In he paper we propose a novel archiecure and implemenaion of -bi Digial Pulse Widh Modulaor (DPWM) circui based on previously known building blocks Linearized Class-BD Double-sided (LBDD) algorihm has been used o calculae he DPWM signals of he -bi resoluion hybrid DPWM for a Class-D digial audio amplifier Noiseshaping process is used o suppor high fideliy wih feasible values of ime resoluion The proposed DPWM circui is composed of wo 6-bi couners and one Analog Delay Locked Loop (ADLL) using 4-bi apped delay line A dual ADLL employing coarse and fine programmable delay elemens has been presened elsewhere [] The proposed -bi DPWM circui, a swiching frequency of 358 khz, clock frequency of 45 MHz allows o aain SNR of db and THD of he oupu signal less han,% wihin he audio baseband and modulaion index of 98 Basic verificaion of circui manufacurabiliy and simulaion resuls (Mone Carlo analysis) for one CMOS process are presened Wojciech Kołodziejski Deparmen of Elecronics and Telecommunicaions Higher Vocaional School in Tarnów Tarnów, Poland Fig Time domain waveforms for he analog Class-BD amplifier using NBDD modulaion Keywords Class-D digial audio amplifier, Linearized Class- BD Double-sided Modulaion (LBDD), Digial Pulse Widh Modulaor (DPWM), apped delay line, Analog Delay Locked Loop (ADLL), Digial o Time Converer (DTC) I INTRODUCTION The popular commercial audio sysems having large numbers of channels rely primarily on digial audio sandards, where mos of he signals are sored, ransferred, and processed in he digial domain Implemenaion of he Class-D concep in such audio sysems provides an opporuniy o remain he audio daa in he digial domain hrough he amplificaion process, and conver o he analogue domain only a he oupu sage using power elecronic inverers Fig shows ime domain waveforms for he analog Class- BD amplifier for Naural Sampling, Double-Sided Modulaion (NBDD) The H-bridge of he Class-BD amplifier is swiching by he wo NBDD signals generaed by he NBDD modulaor which uses wo comparaors o compare he audio signal and is inverse o he riangle waveform As a resul of his comparison wo NBDD signals are generaed ( OUTP_NBDD and OUTM _ NBDD in Fig) o swich each side of he H-bridge independenly We can noice in Fig, ha effecive sampling frequency for Class-BD amplifier is doubled wihou increasing he ransiion frequency on he oupu In erms of differenial The work has been suppored by AGH Universiy of Science and Technology in Kraków gran under conrac no 37 Fig Direc digial Class-D amplifier based on he DPWM using LPWM (Linearized Pulse Widh Modulaio oupu, NBDD is superior, and has by far he mos aracive specral characerisics for all he oher NPWM mehods, and is also mos aracive PWM scheme for Class-D audio amplifiers implemenaion Unforunaely, he NBDD has a high level of CM signal on he oupu erminals, and he oupu filer of he Class-BD amplifier has o be more complicaed o eliminae his signal The digial Class-D amplifier (Fig) employs a digial PWM (DPWM) modulaor o conver direcly N-bi digial pulse-code modulaion (PCM) signal inpu ino a rain of -bi modulaed pulses The PCM signal could be ransformed ino a sandard DPWM signal using direcly uniform PWM (UPWM) [-5] Unforunaely, he fundamenal problem of he UPWM process is is inheren nonlineariy This nonlineariy may be reduced hrough increasing he sampling rae of he digial inpu signal (inerpolaio, and applicaion of precompensaion linearizaion algorihms In our design he PCM

2 signal is ransformed direcly ino a DPWM signal using LBDD algorihm [-5] and we simulaneously adop boh aforemenioned mehods of nonlineariy reducion To generae he PWM signal in he digial domain, we need noise shaping loop o reduce he required clock frequency since he bi precision of he original audio signal is usually oo high o be direcly implemened The calculaed from he noise shaping process rq -bi LPWM oupu daa needs o be convered o a physical pulse widh This is accomplished by digial-o-ime converer (DTC), which oupu pulses o conrol he oupu power sage The aforemenioned real-ime processes mus be calculaed also for he audio signal and is inverse, wha requires significan compuing power In he paper we propose a novel archiecure and implemenaion of a -bi DPWM circui based on previously known building blocks [8-] A linearized hybrid DPWM for a Class-BD digial audio amplifier is composed of wo 6-bi couners and an Analog Delay Locked Loop (ADLL) using 4-bi apped delay line The 7-bi couner generaes mos significan bis MSBs: d ( 9 : 4) of oupu, whereas he 4-bi delay line generaes less significan bis LSB: d ( 3: ) An ADLL using coarse and fine programmable delay elemens [] is used o adjus he delay ime of delay line and lock i o required ime Such hybrid - bi Class-B double-sided DPWM circui requires he clock frequency of 45 MHz and allows o aain SNR below db wihin he audio baseband Paper Organizaion A Linearized Class-BD Double-Sided (LBDD) algorihm is presened in Secion II The general archiecure of he proposed -bi hybrid DPWM circui is presened in Secion III Simulaion resuls are presened in Secion IV The overall conclusions are given in Secion VI II LINEARIZED LBDD ALGORITHM The field of PCM-UPWM conversion by precompensaion is well esablished and various mehods exis [3-7] Using enhanced sampling mehods as Pseudo Naural Pulse Widh Modulaion (PNPWM) or Linearized Pulse Widh Modulaion (LPWM), he precompensaion mehods aemp o emulae NPWM bes possible I is possible o realize significan improvemens in lineariy wih he simple LPWM algorihm, such ha modulaor lineariy is no longer an obsacle in DPWM sysems Class-D audio amplifiers based on sandard PWM usually use double-sided PWM, as i provides wo imes higher minimum ime resoluion of he generaed pulse widh The LBDD algorihm has o be simple enough o provide real-ime calculaion of he DPWM signals for audio signal as well as for is inverse Forunaely, he used LBDD algorihm has o emulae NBDD, which inherenly in erms of differenial oupu is superior, so he applied emulaion process may be simply The LBDD algorihm, used in he design, is compuaionally simple, does no lead o excessive increase in 4 S f ( ) = ( n ) 4n ; dla : n < n < 4 S r( ) = ( n ) 4n ; dla: n < ( n ) y ( n ) nt c S f, p ( k ( ( = n p( nt c T c p y ( n y ( ) ) n S f, y ( n ) ( = nt ( k c k ( n )T c Fig 3 Piecewise linear approximaion of he digial audio inpu oal compuaional complexiy, and is suiable o real-ime calculaions The pulse widh is calculaed digially a resoluion of 4- bis hrough LPWM algorihm [3-6] Inerpolaion of he PCM audio daa sream sampled a fs = 44 khz provides a arge swiching frequency fc = K fs = 358 khz, where he inerpolaion facor K=8 The inerpolaion facor allows a rade-off beween modulaor lineariy, dynamic range and facors relaing o he power conversion as efficiency and power sage lineariy In order o obain saisfacory dynamic range, sampling frequency should be increased o a leas 384 khz, which gives a dynamic range of around 6 db Furher inerpolaion, followed by he firs one, generaes inermediae sample (Fig 3) Using he border and new sample we receive piecewise linear approximaion of he digial audio inpu signal Solving he crossing poins beween he riangular carrier signal and he approximaed signal we obain he pulseedge locaions p ( and k ( wihin n-h period of he swiching frequency (he posiions of he leading edge and he railing edge, respecively) c[ y( ] [ y ( y ( ] T p ( = n p ( = n () 4 S f, ime ( n ) T c y( n ) ime e q ( x( = x( e ( q x( d ( = x( e ( q n Σ Σ N - N rq H( e rq ( N- rq Fig 4 A recursive model of noise shaping archiecure modeled as addiive noise source

3 [ y( y( 3] [ y ( y ( ] 4 k ( = n k ( = n () The finely calculaed N-bi pulse-widh can be requanized o a lower resoluion rq -bi oupu ( rq < N) However, he runcaion of he digial inpu daa o rq -bis resuls in higher quanizaion noise floor in he bandwidh (BW), ie lower Signal o uanizaion Noise Raio (SNR) Inroducing he noise shaping coders o reduce he LPWM bi oupu hrough a requanizing process and a feedback filer increases he SNR wihin he audio BW, whils moving he quanizaion noise power o an unused par of he bandwidh creaed by oversampling Fig4 shows a recursive model of noise shaping archiecure modeled as added noise source Basing on his model we can obain he following z-domain relaionship beween he oupu error noise and he requanized noise source, defined as noise ransfer funcion NTF ( : En( NTF( = = H ( (3) E ( rq The noise shaping filer H ( requires a leas one sample delay, ie he ransmiance H ( can be facorized in a one sample delay and a normal causal digial filer Thus he expression of an opimal ransfer funcion NTF( is causal and wihou delay: N A( a z a z an z NTF( = = B( N b z bz bn z (4) The noise shaping process using fifh order filer and -bi quanizer, applied o he 4-bi LPWM swiching frequency f c = 358 khz, allows o aain SNR of db wihin he audio baseband [3,4,7] I means ha noise shaping process of he 4-bi calculaed LPWM pulse widhs gives - bi DPWM oupu Using pure couner mehod, for -bi PWM oupus ( rq = ), he clock generaor frequency of he DCT would be very high : f = 7 MHz III CLASS-BD DOUBLE-SIDED HYBRID DPWM ARCHITECTURE AND IMPLEMENTATION A Class-BD double-sided hybrid DPWM archiecure can be composed of wo Class-AD ones, using for circui simplificaion only one Analog Delay Locked Loop (DLL) The Indexes L and R in Fig 5 announce wo subsysems of he Class-BD double-sided hybrid DPWM sysem generaing he LBDD signals for audio inpu signal and is inverse, respecively The designed modulaor has following parameers: an inpu audio signal sampling frequency f s = 44 khz, swiching L_Daa -bis [9:] L_Conrol Clock: F R_Daa -bis [9:] R_Conrol Fig5 Archiecure of -bi Class-BD double-sided hybrid DPWM for Class-D audio amplifier frequency f c = 358 khz (T c = 83 μs) and he -bi resoluion of pulse-widh Le us consider an archiecure of -bi Class-AD doublesided hybrid DPWM for a Class-D digial audio amplifier A linearized hybrid DPWM is composed of 6-bi couner and ADLL using 4-bi apped delay line o rade-off resources versus performance Inegraion of wo commonly used Digial o Time Conversion (DTC) mehods: i e couner mehod and based on he apped delay line mehod ino a hybrid DTC allows o a rade-off beween he high-frequency clock requiremen and quanizaion lineariy of he digial o ime conversion [9-] In his approach, an rq -bi resoluion is achieved using an N c -bi couner ( N c < rq ), whereas he remaining Nd = rq Nc bis of resoluion are obained from a apped delay line moved ino he ADLL loop In our design he 6-bi couner generaes mos significan d 9 : 4 of oupu, whereas he 4-bi delay line d 3 : bis MSBs: ( ) generaes less significan bis LSB: ( ) L_Couner 6-bis L_MSB [9:4] R_Couner 6-bis R_MSB [9:4] L_Conrol L_LSB [3:] A naural code 6-bi forward-backward couner couns clock pulses wih frequency of 6 f f (5) = c L_Conrol Circui L_LSB [3:] MUX L_LSB [3:] where f c = K fs fc - PWM swiching frequency, fs - sampling frequency of he digial audio inpu, K - inerpolaion facor, plays a role of ime quanizer wih rising or falling saircase characerisics corresponding o riangle waveform for analog PWM As i is shown in Fig 3, he pulse widh PW ( = k ( p ( wihin each n-h swiching period ( = fc ) is he resul of he wo comparisons of he calculaed posiion of he leading edge of he pulse p ( n ) wih he backward couner conen, and he posiion of he railing edge of he pulse k ( n ) wih he forward couner conen The maximum pulse widh τ PW max occurs for full scale conen () of he forward couner and zero sae () of he backward couner R_LSB [3:] R_Conrol ADLL MUX R_LSB [3:] R_Conrol Circui R_LSB [3:] L_OUT R_OUT

4 SET T C SET T C / R/W A-Regiser Selec Daa A-Regiser Daa T p ( Daa Ou b rq bis d(b rq -:) SET T C B-Regiser Daa T k ( Daa Ou b rq bis d(b rq -:) Daa T p (n-) b rq bis Daa T k (n-) b rq bis b rq -(m) MSB d(b rq -:m) Reverse Couner Daa Couning C-Regiser Ou Sae Decoder b rq -(m) Bis L= D _ CK Rese S R _ T C = T C = 5 5 S R _ Ou Ou B-Regiser Selec SET T C / m LSBs d(m-:) Daa m LSBs d(m-:) Mux 6: Ou F = F Clock C brq -m Phase Deecor Delay Conrol Sage Fig 6 Archiecure of -bi Class-AD double-sided hybrid DPWM for a Class-D digial audio amplifier where: N = ( ) 6 τ T NT (6) PW max = c = is a coun up and coun down capaciy The used couner mehod requires a clock frequency of F = 45 MHz The ADLL using coarse and fine programmable delay elemens is used o adjus he delay ime of delay line and lock i o required ime When he DLL is locked, hen he oupu clock is delayed wih respec o he reference signal by single clock period ie T = 5 ns The DLL comprises a cascade of N = 6 idenical delay cells, wih a delay ime: = 4 d T c =38 ns Each of hem is composed of coarse and fine uning delay elemens The complee archiecure of he hybrid LADD modulaor and he ime domain waveforms of he conrol signals are shown in Figs 6 and 7, respecively Two shif regisers (A and B) are used for soring daa immediaely afer calculaions are done The calculaed posiions of he leading edge p ( n ) and railing edge k ( n ) of he pulse from he preceding swich period are wrien o A and B regiser, respecively The sub-dpwm circuis for coarse pulse-widh esimaion explois a backward couner and sae decoder To differeniae beween he firs and second half of he swiching period T C, an RS flip-flop is used, which is seing by SETT c signal a he very beginning of he cycle, and is reseing by SETT c / signal in he middle of he period cycle Clock: F SET T C Cycle T C Sar SET T C/ Cycle T C Middle Sae Decoder Mux Mux Oupu DPWM Ou Pulse T p T p(n-)=p p TC/ T C LK p k Fig 7 Time domain waveforms of he conrol signals for -bi Class- AD double-sided hybrid DPWM A he sar of period T c, he couner is loaded wih he MSBs of he calculaed posiion of he leading edge p (n-) of he pulse The pulse of T / duraion appears a he oupu of decoder as a resul of backward couning The rise edge of aforemenioned pulse ses he oupu of he D flip-flop o high level, which acivaes he muliplexer (=) The oupu pulse of he muliplexer, seleced by 4 LSBs digial represenaion of leading edge posiion p (n-) of he pulse ses he DPWM oupu pulse, ie ses he oupu RS flip-flop assuming ha T C = Simulaneously he D flip-flop is rese PW T C T d=t / 4 k(n-)=kk T k

5 and muliplexer is no acive any more (=) As we see in Fig 3: p ( n ) = p p In a very similar way he railing edge posiion k ( n ) of he pulse is generaed This process sars in he middle of he period cycle and finishes afer he ime k ( n ) = k k, when he DPWM oupu pulse is reseing, ie he oupu RS flip-flop is reseing assuming ha T = More deailed descripion of building blocks implemenaion is presened in already menioned reference [] IV SIMULATION RESULS All ime domain characerisics and specral plos of DPWM signals have been generaed using Malab ools The specrum is esimaed by soring a number of pulses of he DPWM oupu signal which represens one period of he modulaing waveform Each pulse wihin his periods represens a recangular funcion in he ime domain which is offse by a cerain ime value from he zero ime coordinae Nex he generaed recangular pulse is convered o is frequency domain counerpar, a he same ime a frequency index is generaed o include he relevan frequency sinc values according o he signal specrum characerisic These sequence are hen muliplied wih a Hanning window The calculaed, for each pulse widh, windowed sinc sequences form a marix, which is hen added column wise and subsequenly averaged according o he used number of pulse widhs The averaged sequence represens a saisical average of he DPWM ampliude specrum The calculaion accuracy depends on he number of modulaing periods, ie he number of he pulses wihin he used ime range Fig 8 shows ime domain waveforms for double edge Class-BD modulaion using LBDD algorihm a: M = 95, =, F c = 358 khz, f m = 98 khz, where: M - modulaion index, number of inermediae samples during he second inerpolaion, F c swiching frequency, f m frequency of he modulaing audio signal Fig 9 shows he specra of he calculaed DPWM oupu The HF- specral characerisic is inbeween he naurally sampling and uniformly sampling cases The frequency specrum of he 4-bi has no significan harmonics of he modulaing audio signal wihin he audio baseband, however we can noice a hird harmonic, which in our example (f m = 98 kh lies ou of he audio baseband Wih sufficien approximaion, LBDD provides ha effecive sampling frequency is doubled, jus as NBDD (his is no he case wih UBDD) The noise shaping process using he fifh order filer H( has been applied o he 4-bi LBDD oupu o calculae noise shaped -bi DPWM oupu I is seen from Fig 9, how he noise ransfer funcion has displaced he baseband noise error power o he higher frequency band The zoomed view of he -bi DPWM specrum of LBDD oupu shows ha a SNR of db has been aained wihin he audio baseband c Am Am Am Double edge Class BD modulaion using LBDD: M= 95, =, Fc= 358kHz, fm= 98kHz [ms] [ms] LBDD differenial oupu [ms] Fig 8 Time domain waveforms of he conrol signals for -bi Class- AD double-sided hybrid DPWM *log Am *log Am *log Am *log Am Ampliude specrum for LBDD Zoomed view of ampliude specrum for LBDD Ampliude specrum of noise shaped -bi DPWM oupu LBDD Zoomed view of noise shaped -bi DPWM oupu LBDD Fig 9 Ampliude specrum for LBDD algorihm: =, M = 95, F c = 35,8 khz, f m = 9,8 khz From op o boom: 4-bi DPWM oupu; Zoomed view of 4-bi DPWM oupu; Noise shaped -bi DPWM oupu; Zoomed view of noise shaped -bi DPWM oupu Using he simulaion resuls of he LBDD oupu frequency specrum, i is very easy o calculae LBDD THD versus f r = fm Fc : for: = (UBDD), = (LBDD), M = 5, M = The simulaed resuls are shown in Fig As we see, using very simple LBDD algorihm, for =, THD is less han 87 % wihin he audio baseband and modulaion index M = 95 A complee archiecure of -bi Class-AD doublesided hybrid DPWM for a Class-D digial audio amplifier, presened in Fig 6, has been implemened in 8V 8 nm CMOS echnology from UMC, using he same building blocks which we described in [] The operaion and basic parameers of he sub-dpwm circui convering 4 LSBs have been simulaed using Specre and BSIM3V3 device models for UMC8 CMOS echnology Fig shows ransien responses on he wo firs and wo las delay-line aps As we see in Fig, he DLL is locked, he oupu clock is delayed in relaion o he reference signal by he one clock period ie T = 5 ns, whereas a delay ime of one delay cell equals: = 38 ns d

6 The key poin jusifying he usabiliy of he proposed implemenaion is is robusness and insensiiviy o process and especially mismach variaions in inegraed echnology Therefore we carefully invesigaed he issue in quesion Inensive simulaions wih echnology corners, differen emperaures and supply volages, as well as Mone Carlo models for echnology have been performed Their resuls indicae ha for 45 MHz inpu min-max deviaions from he nominal delay for rising and railing edges, does no exceed value corresponding o /4 LSB In erms of mean values and variance he aforemenioned raio is even beer I seems ha he circui is manufacurable in chosen echnology V CONCLUSIONS A novel archiecure and implemenaion of -bi DPWM circui dedicaed for audio class D power amplifier has been proposed LBDD algorihm has been used o calculae he DPWM signals of he -bi resoluion hybrid DPWM Noiseshaping process using fifh order filer and -bi quanizer, applied o he calculaed 4-bi LPWM swiching frequency f c = 358 khz, allows o aain SNR of db and THD of he oupu signal less han % wihin he audio baseband and modulaion index M = 98 The Class-BD double-sided hybrid DPWM archiecure is composed of wo Class-AD ones, using for circui simplificaion only one ADLL On he oher hand he archiecure of he Class-AD double-sided hybrid DPWM inegraes wo commonly used DTC mehods: ie couner mehod and based on he apped delay line mehod o rade-off beween he high-frequency clock requiremen and quanizaion lineariy of he digial o ime conversion -bi resoluion of he hybrid DPWM is achieved using 6-bi couner, whereas he remaining 4 bis of resoluion are obained from a apped delay line moved ino he ADLL loop Such hybrid -bi Class-B double-sided DPWM circui requires he clock frequency of f = 45 MHz and allows o aain SNR below db wihin he audio baseband Basic verificaion of circui operaion and is manufacurabiliy in available 8nm CMOS process have been done Simulaion resuls show ha he new DPWM archiecure may be very useful in pracical applicaions REFERENCES [] B H Gwee, J S Chang, H Li, A Micropower Low-Disorion Digial Pulsewidh Modulaor for a Digial Class D Amplifier, IEEE Transacions On Circuis And Sysems -II: Analog and Digial Signal Processing, Vol 49, No 4, April, pp45-56 [] F Guanziroli, R Bassoli, C Crippa, D eal, A W 4 db SNR Filer-Less Fully-Digial Open-Loop Class D Audio Amplifier Wih EMI Reducion, IEEE Journal Of Solid-Sae Circuis, Vol 47, No 3, March, pp [3] K Nielsen, Audio Power Amplifier Techniques Wih Energy Efficien Power Conversion, Ph D Thesis, Tech Univ of Denmark April 3, 998 [4] M Johansen, K Nielsen, A Review and Comparison of Digial PWM Mehods for Digial Pulse Modulaion Sysems, 7h AES Convenion, 999 Sepember 4-7 New York [5] C Pascual, Z Song, P T Krein, e al, High-Fideliy PWM Inverer for Digial Audio Amplificaion: Specral Analysis, Real-Time DSP Implemenaion, and Resuls, IEEE Transacions on Power Elecronics, Vol 8, No, January, 3, pp Fig LBDD THD versus f r=f m/f c for: = (UBDD), = (LBDD) Fig Transien responses on he wo firs and wo las delay-line aps [6] V Adrian, Bah-Hwee Gwee, J S Chang, A Review of Design Mehods for Digial Modulaors, 7 IEEE Inernaional Symposium on Inegraed Circuis (ISIC-7) [7] M Berkhou, L Dooper, Class-D Audio Amplifiers in Mobile Applicaions IEEE Transacions On Circuis And Sysems-I: Regular Papers, Vol 57, No 5, pp 99-, May [8] B J Paella, A Prodic, A Zirger, D Maksimovic, High-Frequency Digial PWM Conroller IC for DC DC Converers, IEEE Transacions on Power Elecronics, Vol 8, No, January 3, pp [9] V Yousefzadeh, T Takayama, D Maksimovic, Hybrid DPWM wih digial delay-locked loop, Proc IEEE COMPEL Works, pp [] Xuzhen Shen, Xiaobo Wu, and Jing Lu, Lin in, Hybrid DPWM wih Analog Delay Locked Loop, Proceedings of he Inernaional MuliConference of Engineers and Compuer Scieniss, Vol II, IMCS March [] S C Huera, A de Casro, O Garcia and J A Cobos, FPGA-based digial pulsewidh modulaor wih ime resoluion under ns, IEEE Trans Power Elecron, vol 3, no 6, pp [] J Jasielski, S Kua, W Machowski, W Kolodziejski, An Analog Dual Delay Locked Loop Using Coarse and Fine Programmable Delay Elemens, Proc of he h In Conf MIXDES, Gdynia, Pl June -3, 3, pp 85-9

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