FPGA based Control of a PWM Inverter by the Third Harmonic Injection Technique for Maximizing DC Bus Utilization

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1 FPGA based Control of a PWM Inverter by the Third Harmonic Injection Technique for Maximizing DC Bus Utilization Ahmed Belkheiri 1,2, Said Aoughellanet 1 1 Department of electronics Université Hadj Lakhdar Batna 05 Av Chahid Boukhlouf Algérie a.belkheiri@lagh-univ.dz Mohammed Belkheiri 2, Abdelhamid Rabhi 3 2 Laboratoire de Télécommunications, Signaux et Systèmes Universié Amar Telidji de Laghouat, Algérie 3 Laboratoire de Modélisation, Information et Systèmes (MIS), Université de Picardie Amiens, France Abstract The objective of this paper is to design and implement a third harmonic injection PWM strategy THIPWM on an FPGA, to control a two-level three phase PWM inverter, in order to generate a fundamental component, with variable amplitude and frequency of the inverter output voltage, by varying the modulation index and reference frequency. The developed strategy aims to explore the maximum of the available DC bus that supplies the inverter with a minimum level of THD, and uses the minimum number of logic elements LEs available on the FPGA. This technique is verified through simulation results. An experimental power electronics set-up that consists of a DC to AC PWM inverter, a DC supply, and an output LR low pass filter is built and controlled using the Altera DE2 development and education board based on a Cyclone II ALTERA FPGA to test the proposed THIPWM architecture. Keywords THIPWM ; FFT; FPGA; Les; Modulation Index, MOSFETs; PWM inverters, THD, VHDL I. INTRODUCTION Recent advances in digital systems such as microprocessors, microcontrollers, Digital Signal Processors (DSP), Very Large Scale Integrated VLSI circuits and Programmable logic devices FPGAs and the variety of the available hardware resources, and Computer Aided Design (CAD) tools offered by different constructors for developing digital systems based on these devices [1,2] on one hand. And advances in solid-state power electronic devices with power ratings up to the 1 MVA range, and switching frequency ratings up to about 100 khz on the other hand [3], has increased the requirement for better process control. This has resulted in many new applications for AC variable speed drives (VSDs), Active Power Filters (APF), Dynamic Voltage Restorers (DVR), Uninterruptible Power Supplies (UPS), and Distribution Static Compensators (DSTATCOM) [4 8], induction heating, and renewable energy systems [9]. The inverters (VSI), which generate an AC voltage with a desired frequency from a constant DC voltage using PWM techniques is the most important component used in such applications. PWM techniques have been studied extensively during the last few decades. A large variety of methods, differing in concept and performance, have been developed to achieve one or more of the following objectives: a maximum fundamental component, best DC utilization. [10][11], wide linear modulation range, fewer switching losses, less total harmonic distortion (THD), easy implementation and less computation time [12]. Among these techniques we can mention the SPWM strategy which is easy to implement and can generate a fundamental of output voltage from zero to 78.54% of the voltage value obtained by the six-step mode. The drawback of this limited percentage can be overcome easily by the third harmonic Injection strategy THIPWM [13]. Such technique is used to generate a variable frequency voltage by synchronism to insert the correct third harmonic [14] [15], this means that the real time implementation of such scheme requires high performance digital controllers which provide the sequentially executable software solution, and FPGA provide the parallel executable hardware solution, which offer the high speed computation in real time. Moreover, another important issue in using FPGAs is their reconfigurability and reusability of hardware architectures for rapid prototyping of the digital system [16]. During 1980s, the low performance microprocessors were used as reported in [17]. In 1990s, the DSPs were used for power electronics converter control [18]. The objective of this paper is to present a simplified THIPWM technique to control three phase inverter, in order to generate variable frequency of inverter output fundamental component, with maximum DC bus utilization. This paper is organized as follows: the next section is devoted to review of THIPWM technique. Then in section III the whole design architecture will be detailed. Section VI is devoted to experimental results. Finally some concluding remarks are reported. II. PRINCIPAL OF THIPWM Fig. 1 shows the overall system that consists of a two level three-phase inverter, which use 6-pulse for control switches gate (three-leg), an output LR low pass filter as a three phase load. The system requirements for this study are as follows: DC- Bus voltage, Fundamental frequency,

2 PWM carrier frequency, Modulation index, Output filter parameters : L 24 m H and R 150 Note that the same system parameters are used in both simulation study and experimental results sections. (a) Figure 1. PWM inverter topology. In its simplest form, a square output voltage waveform can be obtained easily by switching on each leg for one half-period and switching it off for the next half-period, at the same time ensuring that each phase is shifted one third of the period to ensure a 120 o phase shift as shown in the Fig 2. This is referred to as the six-step mode. Figure 2. Six-step mode pulses, line to line V ab and line to neutral V an The resulting phase-to-phase voltage waveform comprises a series of square pulses whose widths are two thirds of the period of the switch in each phase. The harmonic spectrums of line to neutral output voltage Van and of filter output voltage VaR are shown in the Fig. 3. The Amplitude value of the fundamental (60 Hz) sinusoidal voltage component obtained by six-step mode is [19]: V 2Ud π 260 π 1six -step 38.2V (1) The Amplitude value of the n th harmonic voltage: V n V 1six- step (2) n Figure 3. (a) Harmonic spectrum of line to neutral Van voltage, (b) Harmonic spectrum of filter output voltage VaR. The Fig. 3.a illustrates that the square wave output voltage has a lot of components (THD31.08%) of reasonably large magnitude at frequencies close to the fundamental, which means that it is difficult to filter it (THD21,18%), FIG 3.b; furthermore, the triple harmonics (harmonics whose frequency is a multiple of three times the fundamental frequency), 3rd, 9th, 15th, 21st, etc., have been eliminated, this characteristic is obtained, only, with three-phase inverter topology, which will be used in third harmonic injection strategy. Since, this harmonic components are unwanted in many applications, in order to overcome this drawback, the SPWM strategy was introduced, the SPWM pulses are generated by comparing, three low-frequency target reference waveforms (usually a sinusoid), shifted between them by 120, against a highfrequency carrier waveform (sawteeth, triangular), with amplitude Vc, and frequency fc, the reference waveforms have the form: V V V a _ ref b _ ref c _ ref (b) ( t) Vr sin(2πft) 2π ( t) Vr sin2πft + 3 2π ( t) V Vr r sin 2πft, m 3 V c (3) Where m : modulation index or modulation depth, used to adjusting output voltage magnitude, with ranges 0 < m < 1 f : fundamental frequency. Fig. 4.a shows three generated SPWM pulses, for three upper switches inverter (Ka, Kb, Kc), their complements are used to control the three lower switches with fc1980 Hz, f60 Hz, and m1.

3 Fig. 7, which makes THD to increase and we will be in the over-modulation region. (a) Figure 4. (a) :Three SPWM pulses, (b): Inverter output voltage Vab,Van, Van harmonic spectrum at fc1980 Hz. FFT analysis of the inverter output voltage as illustrated in Fig. 4.b. shows that the fundamental component amplitude is Ud/230V, which make 78.54% of those obtained by six-step mode 30/ %, as mentioned in introduction, furthermore thanks to SPWM the first harmonics group is pushed away at carrier frequency 1980 Hz. Figure 7. Over-modulation technique. To avoid pulses cancellation, the sine reference waveform must modified, in over-modulation region, this done by third harmonic injection, since, the 3th, 9th, 15th, 21st, etc harmonics, are eliminated, in three phase topology. Following Reference [20], consider a waveform consisting of a fundamental component with the addition of a triplefrequency term: y( t) K sin ωt + Asin 3ωt (4) Where K and A is a parameters to be optimized while keeping the maximum amplitude of y(t) under unity. The maximum value of y(t) is found by setting its derivative with respect to wt equal to zero. Figure 5. Filter output voltage VaR, and its harmonic spectrum at fc1980 Hz. Fig. 5. Shows that the VaR is still distorted with total harmonic distortion THD of 21.73%. It is evident that is not properly filtered and cannot be used as a clean sinusoidal voltage source for power applications. Figure 6. Filter output voltage VaR, and its harmonic spectrum at fc15 KHz Let s now take fc15khz, as shown in Fig. 6, the filter output voltage is purely sinusoidal, with THD0.57%, this means that the first harmonics group are pushed away to frequency greater than the cutoff frequency of the LR filter. By SPWM we can obtain sinusoidal output voltage, with less harmonic distortion, but the maximum obtained output fundamental amplitude, when m1, is only %, of the fundamental that can be reached by six-step mode. To expand the output fundamental amplitude beyond 78.54% region, we have to take m>1, until some pulses are cancelled as shown on Figure 8. One-Phase Third-Harmonic Injection PWM principal According to [20], the three reference waveforms, to implement third harmonic injection are given by: 1 V a_ref(t) V r( sint + sin3t) 6 (5) + 1 V + + a_ref(t) V r( sin( 2 ) sin( 3t 2 )) V (t). V ( ( 2 1 ) + ( t 2 a_ref 1156 r sin sin 3 )) Fig. 8 shows the injection of a third harmonic with a peak magnitude of one sixth to the modulation waveform where the red curve presents the resulting reference signal. The THIPWM is implemented in the same manner as the SPWM, that is, the reference waveforms are compared with a triangular waveform. As a result, the amplitude of the reference waveforms does not exceed the DC supply voltage Ud/2, but the fundamental component is approximately 15,5% higher in amplitude than the normal SPWM, which provides a maximum fundamental amplitude about 90% of fundamental amplitude than obtained by six-step mode.

4 waveform (128 samples), the two other references are obtained by offset (c(0), c(128/3),c(-128/3)), this reduces FPGA logic elements utilization, however, the reference samples are read from the look-up-table at periodic interval, using an adjustable counter as a pointer, then, every read sample is scaled, which allows us to generate three reference waveforms with desired frequency and amplitude. Figure 9. THIPWM pulses generation. Fig 10.a Shows inverter output voltage Vab, Van, and Fig. 10.b shows filter output voltage VaR along with its FFT spectrum. As shown in Fig 10.b the fundamental component of the filter output voltage is 34.4 V (90% of 38.2 V see Fig. 3.), with a THD of 0.43%. The presented study confirms the efficiency of third harmonic injection strategy, in terms of DC bus utilization, harmonic distortion and simplicity of its implementation. Figure 11. Proposed THIPWM scheme. The reference waveform frequency is controlled by the clock of the pointer counter. Hence, a configurable sub module is designed to generate adequate clock frequencies, in this paper the sub module is configured to generate a sine wave with frequencies ranging from 0.5Hz to 60 Hz, with a 0.5Hz step, depending on the entered Frequency_ ref as shown in Fig. 12. (a) Figure 10.Simulation results for THIPWM control. III. FPGA THIPWM GENERATOR The THIPWM generator, based on regular sampled PWM, is shown in Fig. 10, which is designed to generate three output pulses, adjusted in both the index modulation m and the modulating sine frequency f with 0.5 Hz step (highest possible resolution), with a phase angle of 120 between each 2 phases. The carrier frequency is set at 15 KHz. To prevent short circuit problems and the power inverter breakdown, the complementary pulses are generated by MOSFET driver IC, with an appropriate dead time. The THIPWM pulses are generated by comparison of THIPWM reference waveforms of equation (5) with carrier triangle waveform. Only one look-up table (ROM) is used rather than three, which contains one cycle of a sampled Va_ref Figure 12. Sub module scheme for adjusting reference waveform frequency. The value of frequency references is calculated by the following formula: Where: F ref F 2 FPGA N. Fw 2 fw is desired reference wave frequency N: is the word length of the counter (8 bits in our case). Using the previous formula (6), all Frequency_ref values are calculated and stored in a memory, in order to generate the range frequency (0.5~60 Hz). Another specification should be set to scale the generated sine-wave amplitude related to (6)

5 modulation index m (0 to 1 by the requested step), to perform this operation; we have used the fixed-point arithmetic. Two operations are used the multiplication and the division which is carried easily by the shift operation. In this approach, each 8 bit reference sample is read from the memory then it is multiplied by the desired m, the result is a 16 bit signed data, which is shifted by 7 (division by 128) after that, finally the result is converted to 8 bits signed data. This approach allows us to scale the sine wave between 0% and 99,2% with a 0.78% step. The carrier waveform is a triangle wave that was implemented in FPGA like an up-down counter, with the same way described in the previous paragraph; we can generate the carrier waveform with the desired frequency. The designed THIPWM top module has been developed and implemented on the Altera DE2 development and education board, which includes a Cyclone II 2C35 family FPGA devise in a 672-pin package, and EPCS16 serial configuration device [21]. IV. EXPERIMENTAL VALIDATION After achieving satisfactory implementation result, in term of FPGA Logic Elements 2% (628 LEs) utilization, an experimental work is carried to test THIPWM generator efficiency. Fig. 15 shows the experimental hardware set-up which consists of: DC bus rectifier module. Home made three phase inverter, based on six (three legs) IRFPC60 MOSFET power transistor with ultrafast soft recovery diode, opto-coupler (HP2200 IC) to isolate electrically the control circuit and the power circuits from each other, and gate drivers (IR 2111 IC) to drive the gates of the inverter switches, by creating a floating supply. These modules are designed and constructed in our laboratory, according to fig. 1. FPGA ALTERA DE2 board to generate the THIPWM pulses. Tektronix oscilloscope for measurement and analysis. Figure 13. Top -level entity of THIPWM generator scheme. The HDL code was synthesized using Quartus II software provided by Altera. Fig. 13 shows the top level entity of THIPWM which is developed by using schematic and vhdl description language. Fig. 14 displays the compiler flow summary section, which indicates that only 2% (628) logic element, 0% of memory bits, 1% (7) of pins, 0% of PLLs unit are needed to implement this circuit on the selected FPGA chip. Figure 14. Compiler flow summary of THIPWM module. Figure 15. Experimental hardware set-up. For safety precautions the DC bus is fixed only at 60 Volts. Before programming the FPGA a pin assignment should be performed, so two debounced pushbuttons are used to increase and decrease the modulating wave signal frequency and amplitude of fundamental component output voltage, the triangle waveform carrier frequency is fixed at 15 KHz, in FPGA program, the three output pulses of THIPWM are assigned to three pins of expansion headers with 3.3 V output voltages, 27 MHz oscillator clock input is chosen as the main clock for designed system. The Signal Express software is used for signals measurement, acquisition and analysis. The resulting output voltages with their spectrum are represented in Fig. 16. It is clear that the quality of the voltage waveform has not been significantly degraded and the first group is pushed properly at carrier frequency 15 KHz, the fundamental component at 60 Hz has amplitude value of 31.26V, which is less than the fundamental component obtained by simulation 34.32V, this little decrease is due to Switch losses and voltage drop.

6 Figure 17. Experimental results of filter three line to neutral output voltages, and VaR harmonic spectrum at f50 Hz, m0.78. Figure 16. Experimental results of the inverter line to line voltage Vab, inverter line to neutral voltage Van and its harmonic spectrum The Experimental results of Fig. 17 show the filter three line to neutral output voltages, which are shifted by 120, according to harmonic spectrum the filtered VaR voltage has an amplitude of V, which means that the inverter output voltage is slightly attenuated by the filter. The obtained three sinusoidal voltages have only 2.17% of THD. The experimental results of Fig. 16 and Fig. 17 are obtained at f 60Hz, fc 15 khz 0.95 m and, when m is more than 0.95, the output voltage will decrease and the THD will increase, however, m may take practically 0.95 as maximum value.. Figure 19. Experimental results of filter three line to neutral output voltages, and VaR harmonic spectrum at f25 Hz, m0.37. Figure 17. Experimental results of filter three line to neutral output voltages, and VaR harmonic spectrum. As shown in Fig. 18 the amplitude of output voltage is 25.8 V at m0.78. According to Fig. 19, When m0.37 the inverter output voltage amplitude is V, however, the inverter controlled by the digital THIPWM modulator has properly generated a three phase sinusoidal voltage with the desired frequency V. CONCLUSION This paper presented the design and implementation of THIPWM generator, based on FPGA, which can be used for PWM inverter to control output voltage in both frequency and amplitude. A novel approach was introduced in designing such module, on FPGA, in order to reduce the number of used logic elements (LEs) 628. Experimental results have confirmed that, the proposed THIPWM scheme works properly, which improve the DC bus utilization, with low harmonic distortion. REFERENCES [1] A.Belkheiri, M.Belkheiri, S.Aoughellanete and A.Rabhi. "FPGA implementation of configurable three-phase SPWM module ", IEEE Conference Publications, DOI: /CCCA nd International Conference on Communications, Computing and Control Application (CCCA), pp. 1-5, DEC [2] K.Pongiannan, P.Selvabharathi and N.Yadaiah "FPGA based three phase sinusoidal PWM VVVF controller", IEEE Conference

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