Control Integrated POwer System (CIPOS )

Transcription

1 Control Integrated POwer System (CIPOS ) Datasheet Datasheet Please read the Important Notice and Warnings at the end of this document <Revision 2.1> <21681>

2 Table of Contents CIPOS Control Integrated POwer System... 3 Features... 3 Target Applications... 3 Description... 3 System Configuration... 3 Pin Configuration... 4 Internal Electrical Schematic... 4 Pin Assignment... 5 Pin Description... 5 HIN(U, V, W) and LIN(U, V, W) (Low side and high side control pins, Pin 7 12)... 5 VFO (Faultoutput and NTC, Pin 14)... 6 ITRIP (Over current detection function, Pin 15)... 6 VDD, VSS (Low side control supply and reference, Pin 13, 16)... 6 VB(U, V, W) and VS(U, V, W) (High side supplies, Pin 1 6)... 6 N (Low side common emitter, Pin 17)... 6 W, V, U (High side emitter and low side collector, Pin 18 2)... 6 P, NR (Positive bus input voltage and negative bus voltage, Pin 21, 24)... 6 R, S (Single phase diode bridge rectifier input pins, Pin 22, 23)... 6 Absolute Maximum Ratings... 7 Module Section... 7 Inverter Section... 7 Rectifier Diode Section... 7 Control Section... 8 Recommended Operation Conditions... 8 Static Parameters... 9 Dynamic Parameters... 1 Bootstrap Parameters... 1 Thermistor Mechanical Characteristics and Ratings Circuit of a Typical Application Switching Times Definition Electrical characteristic Package Outline Revision History Datasheet 2 <Revision 2.1> <21681>

3 CIPOS Control Integrated POwer System Dual InLine Intelligent Power Module 3Φ bridge 6V / 1A, Single Phase Diode Bridge Rectifier Features Fully isolated Dual InLine molded module TRENCHSTOP IGBTs Optimized diodes for single phase diode bridge rectifier Rugged SOI gate driver technology with stability against transient and negative voltage Allowable negative VS potential up to 11V for signal transmission at VBS=15V Integrated bootstrap functionality Over current shutdown Temperature monitor Undervoltage lockout at all channels Low side common emitter Crossconduction prevention All of 6 switches turn off during protection Leadfree terminal plating; RoHS compliant Description The CIPOS module family offers the chance for integrating various power and control components to increase reliability, optimize PCB size and system costs. It is designed to control three phase AC motors and permanent magnet motors in variable speed drives for applications like a washing machine. The package concept is specially adapted to power applications, which need good thermal conduction and electrical isolation, but also EMIsave control and overload protection. TRENCHSTOP IGBTs and anti parallel diodes are combined with an optimized SOI gate driver for excellent electrical performance. System Configuration Target Applications Washing machines Fans Low power motor drives 3 half bridges with TRENCHSTOP IGBTs and anti parallel diodes Single phase diode bridge rectifier 3Φ SOI gate driver Thermistor Pintoheatsink clearance distance typ. 1.6mm Datasheet 3 <Revision 2.1> <21681>

4 Pin Configuration Bottom View (1) VS(U) (2) VB(U) (3) VS(V) (4) VB(V) (5) VS(W) (6) VB(W) (7) HIN(U) (8) HIN(V) (9) HIN(W) (1) LIN(U) (11) LIN(V) (12) LIN(W) (13) VDD (14) VFO (15) ITRIP (16) VSS (24) NR (23) R (22) S (21) P (2) U (19) V (18) W (17) N Figure 1 Pin configuration Internal Electrical Schematic NR (24) (1) VS(U) R (23) (2) VB(U) VB1 HO1 RBS1 VS1 S (22) (3) VS(V) (4) VB(V) VB2 HO2 RBS2 VS2 P (21) (5) VS(W) (6) VB(W) VB3 HO3 RBS3 VS3 U (2) (7) HIN(U) HIN1 LO1 (8) HIN(V) (9) HIN(W) (1) LIN(U) (11) LIN(V) HIN2 HIN3 LIN1 LIN2 LO2 V (19) (12) LIN(W) (13) VDD LIN3 VDD W (18) (14) VFO (15) ITRIP VFO ITRIP LO3 (16) VSS VSS N (17) Thermistor Figure 2 Internal schematic Datasheet 4 <Revision 2.1> <21681>

5 Pin Assignment Pin Number Pin Name Pin Description 1 VS(U) Uphase high side floating IC supply offset voltage 2 VB(U) Uphase high side floating IC supply voltage 3 VS(V) Vphase high side floating IC supply offset voltage 4 VB(V) Vphase high side floating IC supply voltage 5 VS(W) Wphase high side floating IC supply offset voltage 6 VB(W) Wphase high side floating IC supply voltage 7 HIN(U) Uphase high side gate driver input 8 HIN(V) Vphase high side gate driver input 9 HIN(W) Wphase high side gate driver input 1 LIN(U) Uphase low side gate driver input 11 LIN(V) Vphase low side gate driver input 12 LIN(W) Wphase low side gate driver input 13 VDD Low side control supply 14 VFO Fault output / Temperature monitor 15 ITRIP Over current shutdown input 16 VSS Low side control negative supply 17 N Low side common emitter 18 W Motor Wphase output 19 V Motor Vphase output 2 U Motor Uphase output 21 P Positive bus input voltage 22 S Single phase diode bridge rectifier S input 23 R Single phase diode bridge rectifier R input 24 NR Negative bus voltage Pin Description HIN(U, V, W) and LIN(U, V, W) (Low side and high side control pins, Pin 7 12) These pins are positive logic and they are responsible for the control of the integrated IGBT. The Schmitttrigger input thresholds of them are such to guarantee LSTTL and CMOS compatibility down to 3.3V controller outputs. Pulldown resistor of about 5k is internally provided to prebias inputs during supply startup and a zener clamp is provided for pin protection purposes. Input Schmitttrigger and noise filter provide beneficial noise rejection to short input pulses. The noise filter suppresses control pulses which are below the filter time t FILIN. The filter acts according to Figure 4. CIPOS TM INPUT NOISE FILTER UZ=1.5V SWITCH LEVEL VIH; VIL Datasheet 5 <Revision 2.1> <21681> HINx LINx VSS Figure 3 5k SchmittTrigger Input pin structure a) b) HIN LIN HO LO Figure 4 t FILIN low HIN LIN HO LO high Input filter timing diagram t FILIN

6 It is not recommended for proper work to provide input pulsewidth lower than.5µs. The integrated gate drive provides additionally a shoot through prevention capability which avoids the simultaneous onstate of two gate drivers of the same leg (i.e. HO1 and LO1, HO2 and LO2, HO3 and LO3). When two inputs of a same leg are activated, only former activated one is activated so that the leg is kept steadily in a safe state. A minimum deadtime insertion of typically 38ns is also provided by driver IC, in order to reduce crossconduction of the external power switches. VFO (Faultoutput and NTC, Pin 14) The VFO pin indicates a module failure in case of under voltage at pin VDD or in case of triggered over current detection at ITRIP. A pullup resistor is externally required. VDD VFO VSS Figure 5 Thermistor R ON,FLT 1 CIPOS TM From ITRIP Latch From UV detection Internal circuit at pin VFO The same pin provides direct access to the NTC, which is referenced to VSS. An external pullup resistor connected to +5V ensures that the resulting voltage can be directly connected to the microcontroller. ITRIP (Over current detection function, Pin 15) CIPOS provides an over current detection function by connecting the ITRIP input with the IGBT collector current feedback. The ITRIP comparator threshold (typ..47v) is referenced to VSS ground. An input noise filter (typ.: t ITRIPMIN = 53ns) prevents the driver to detect false overcurrent events. Over current detection generates a shutdown of all outputs of the gate driver after the shutdown propagation delay of typically 1ns. The faultclear time is set to minimum 4µs. VDD, VSS (Low side control supply and reference, Pin 13, 16) VDD is the control supply and it provides power both to input logic and to output power stage. Input logic is referenced to VSS ground. The undervoltage circuit enables the device to operate at power on when a supply voltage of at least a typical voltage of V DDUV+ = 12.1V is present. The IC shuts down all the gate drivers power outputs, when the VDD supply voltage is below V DDUV = 1.4V. This prevents the external power switches from critically low gate voltage levels during onstate and therefore from excessive power dissipation. VB(U, V, W) and VS(U, V, W) (High side supplies, Pin 1 6) VB to VS is the high side supply voltage. The high side circuit can float with respect to VSS following the external high side power device emitter voltage. Due to the low power consumption, the floating driver stage is supplied by integrated bootstrap circuit. The undervoltage detection operates with a rising supply threshold of typical V BSUV+ = 12.1V and a falling threshold of V BSUV = 1.4V. VS(U, V, W) provide a high robustness against negative voltage in respect of VSS of 5V transiently. This ensures very stable designs even under rough conditions. N (Low side common emitter, Pin 17) The low side common emitter is available for current measurements. It is recommended to keep the connection to pin VSS as short as possible in order to avoid unnecessary inductive voltage drops. W, V, U (High side emitter and low side collector, Pin 18 2) These pins are motor U, V, W input pins. P, NR (Positive bus input voltage and negative bus voltage, Pin 21, 24) The high side IGBTs are connected to the bus voltage. It is noted that the bus voltage does not exceed 45V. The bus voltage is referenced to NR ground. R, S (Single phase diode bridge rectifier input pins, Pin 22, 23) Rectifier input pins for connecting to the grid line. Datasheet 6 <Revision 2.1> <21681>

7 Absolute Maximum Ratings (V DD = 15V and T J = 25 C, if not stated otherwise) Module Section Description Condition Symbol min max Storage temperature range T stg C Isolation test voltage RMS, f = 6Hz, t = 1min V ISOL 2 V Operating case temperature range Refer to Figure 6 T C 4 1 C Inverter Section Description Condition Symbol min max Max. blocking voltage I C = 25µA V CES 6 V DC link supply voltage of PN Applied between PN V PN 45 V DC link supply voltage (surge) of PN Applied between PN V PN(surge) 5 V Output current T C = 25 C, T J < 15 C T C = 8 C, T J < 15 C I C A Maximum peak output current less than 1ms I C(peak) A Short circuit withstand time 1 V DC 4V, T J = 15 C t SC 5 µs Power dissipation per IGBT P tot 22.1 W Operating junction temperature range T J 4 15 C Single IGBT thermal resistance, junctioncase Single diode thermal resistance, junctioncase R thjc 6.78 K/W R thjcd 7.7 K/W Rectifier Diode Section Description Condition Symbol Maximum repetitive reverse voltage V RRM 9 V RMS forward current T C = 1 C, T J < 15 C I FRM 1 A Peak surge forward current I 2 t value 5Hz, Non repetitive T C = 25 C T C = 125 C tp = 1ms T C = 25 C T C = 125 C min I FSM I 2 t Operating junction temperature range T J(RD) 4 15 C Single Diode thermal resistance Junctioncase R thjc(rd) 6.2 K/W max A A 2 s 1 Allowed number of short circuits: <1; time between short circuits: >1s. Datasheet 7 <Revision 2.1> <21681>

8 Control Section Description Condition Symbol Module supply voltage V DD 1 2 V High side floating supply voltage (VB vs. VS) Input voltage LIN, HIN, ITRIP min max V BS 1 2 V Switching frequency f PWM 2 khz V IN V ITRIP V Recommended Operation Conditions All voltages are absolute voltages referenced to V SS potential unless otherwise specified. Description Symbol min typ max DC link supply voltage of PN V PN 45 V High side floating supply voltage (V B vs. V S) V BS V Low side supply voltage V DD V Control supply variation Logic input voltages LIN, HIN, ITRIP ΔV BS, ΔV DD V IN V ITRIP Between VSS N (including surge) V SS 5 5 V V/µs V Figure 6 T C measurement point 1 1 Any measurement except for the specified point in figure 6 is not relevant for the temperature verification and brings wrong or different information. Datasheet 8 <Revision 2.1> <21681>

9 Static Parameters (V DD = 15V and T J = 25 C, if not stated otherwise) Description Condition Symbol min typ max I C = 6A CollectorEmitter saturation voltage T J = 25 C 15 C V CE(sat) V I F = 6A Diode forward voltage T J = 25 C 15 C V F V I F = 1A Rectifier diode forward voltage T J = 25 C 15 C V FR V CollectorEmitter leakage current V CE = 6V I CES 1 ma Logic "1" input voltage (LIN, HIN) V IH V Logic "" input voltage (LIN, HIN) V IL.7.9 V ITRIP positive going threshold V IT,TH mv ITRIP input hysteresis V IT,HYS 4 7 mv VDD and VBS supply under voltage positive going threshold VDD and VBS supply under voltage negative going threshold VDD and VBS supply under voltage lockout hysteresis V DDUV+ V BSUV+ V DDUV V BSUV V DDUVH V BSUVH V V V Input clamp voltage (HIN, LIN, ITRIP) Iin=4mA V INCLAMP V Quiescent VB x supply current (VB x only) Quiescent VDD supply current (VDD only) H IN = V I QBS 3 5 µa L IN = V, H INX = 5V I QDD 37 9 µa Input bias current V IN = 5V I IN ma Input bias current V IN = V I IN 2 µa ITRIP input bias current V ITRIP = 5V I ITRIP µa VFO input bias current VFO = 5V, V ITRIP = V I FO 6 µa VFO output voltage I FO = 1mA, V ITRIP = 1V V FO.5 V Datasheet 9 <Revision 2.1> <21681>

10 Dynamic Parameters (V DD = 15V and T J = 25 C, if not stated otherwise) Description Condition Symbol min typ max Turnon propagation delay time t on 6 ns V LIN, HIN = 5V, Turnon rise time t r 15 ns I C = 6A, Turnon switching time t V DC = 3V c(on) 8 ns Reverse recovery time t rr 9 ns Turnoff propagation delay time V LIN, HIN = V, t off 77 ns Turnoff fall time I C = 6A, t f 9 ns Turnoff switching time V DC = 3V t c(off) 125 ns Short circuit propagation delay time From V IT,TH+ to 1% I SC t SCP 12 ns Input filter time ITRIP V ITRIP = 1V t ITRIPmin 53 ns Input filter time at LIN, HIN for turn on and off V LIN, HIN = V & 5V t FILIN 29 ns Fault clear time after ITRIPfault V ITRIP = 1V t FLTCLR µs Deadtime between low side and high side DT PWM.5 µs Deadtime of gate drive circuit DT IC 38 ns IGBT turnon energy (includes reverse recovery of diode) IGBT turnoff energy Diode recovery energy V DC = 3V, I C = 6A T J = 25 C 15 C V DC = 3V, I C = 6A T J = 25 C 15 C V DC = 3V, I C = 6A T J = 25 C 15 C E on E off E rec µj µj µj Bootstrap Parameters (T J = 25 C, if not stated otherwise) Description Condition Symbol min typ max Repetitive peak reverse voltage V RRM 6 V Bootstrap diode resistance of Uphase 1 VS2 or VS3 = 3V, T J = 25 C VS2 and VS3 = V, T J = 25 C VS2 or VS3 = 3V, T J = 125 C VS2 and VS3 = V, T J = 125 C R BS Ω Reverse recovery time I F =.6A, di/dt = 8A/µs t rr_bs 5 ns Forward voltage drop I F = 2mA, VS2 and VS3 = V V F_BS 2.6 V 1 R BS2 and R BS3 have same values to R BS1. Datasheet 1 <Revision 2.1> <21681>

11 Thermistor resistance [kω ] Control Integrated POwer System (CIPOS ) Thermistor Description Condition Symbol min typ max Resistor T NTC = 25 C R NTC 85 k Bconstant of NTC (Negative Temperature Coefficient) B(25/1) 492 K 35 Thermistor resistance [kω ] Min. Typ. Max Thermistor temperature [ ] Figure Thermistor temperature [ ] Thermistor resistance temperature curve and table (For more information, please refer to the application note AN2161 CIPOS Mini Technical description ) Mechanical Characteristics and Ratings Description Condition min typ max Mounting torque M3 screw and washer Nm Flatness Refer to Figure µm Weight 6.15 g + + Figure 8 Flatness measurement position Datasheet 11 <Revision 2.1> <21681>

12 Control GND line Control Integrated POwer System (CIPOS ) Circuit of a Typical Application NR (24) (1) VS(U) R (23) AC (2) VB(U) VB1 HO1 #4 (3) VS(V) (4) VB(V) VB2 RBS1 VS1 HO2 S (22) RBS2 VS2 P (21) (5) VS(W) (6) VB(W) VB3 HO3 #1 RBS3 VS3 U (2) #5 (7) HIN(U) HIN1 Micro Controller (8) HIN(V) (9) HIN(W) (1) LIN(U) (11) LIN(V) (12) LIN(W) HIN2 HIN3 LIN1 LIN2 LIN3 LO1 LO2 V (19) W (18) 3ph AC Motor VDD line (13) VDD VDD (14) VFO (15) ITRIP VFO ITRIP LO3 #7 (16) VSS 5 or 3.3V line N (17) VSS Thermistor #3 Temperature monitor #2 U, V, W phase current sensing <Signal for protection> <Signal for protection> #6 Power GND line Figure 9 Typical application circuit 1. Input circuit To reduce input signal noise by high speed switching, the R IN and C IN filter circuit should be mounted. (1Ω, 1nF) C IN should be placed as close to V SS pin as possible. 2. Itrip circuit To prevent protection function errors, C ITRIP should be placed as close to Itrip and V SS pins as possible. 3. VFO circuit VFO output is an open drain output. This signal line should be pulled up to the positive side of the 5V/3.3V logic power supply with a proper resistor R PU. It is recommended that RC filter be placed as close to the controller as possible. 4. VBVS circuit Capacitor for high side floating supply voltage should be placed as close to VB and VS pins as possible. 5. Snubber capacitor The wiring between CIPOS Mini and snubber capacitor including shunt resistor should be as short as possible. 6. Shunt resistor The shunt resistor of SMD type should be used for reducing its stray inductance. 7. Ground pattern Ground pattern should be separated at only one point of shunt resistor as short as possible. Datasheet 12 <Revision 2.1> <21681>

13 Switching Times Definition HINx LINx.9V 2.1V t rr t off t on i Cx 9% 9% 1% t f t r 1% 1% 1% 1% v CEx t c(off) t c(on) Figure 1 Switching times definition Datasheet 13 <Revision 2.1> <21681>

14 Z thjc, transient thermal resistance [K/W] Eon, Turn on switching energy loss [mj] Eoff, Turn off switching energy loss [mj] Erec, Reverse recovery energy loss [uj] Ic, Collector Emitter current [A] Ic, Collector Emitter current [A] I F, Anode Cathode current [A] Control Integrated POwer System (CIPOS ) Electrical characteristic T J VDD=2V T J T J J J J J VCE(sat), Collector Emitter voltage [V] Typ. Collector Emitter saturation voltage VCE(sat), Collector Emitter voltage [V] Typ. Collector Emitter saturation voltage V F, Forward voltage [V] Typ. Anode Cathode forward voltage VDC=3V VDC=3V Ic, Collector current [A] Typ. Turn on switching energy loss.5 VDC=3V Ic, Collector current [A] Typ. Turn off switching energy loss Ic, Collector current [A] Typ. Reverse recovery energy loss ton, Turn on propagation delay time [ns] 74 VDC=3V Ic, Collector current [A] Typ. Turn on propagation delay time tc(on), Turn on switching time [ns] VDC=3V Ic, Collector current [A] Typ. Turn on switching time toff, Turn off propagation delay time [ns] VDC=3V Ic, Collector current [A] Typ. Turn off propagation delay time tc(off), Turn off switching time [ns] VDC=3V trr, Reverse recovery time [ns] VDC=3V E3 D : duty ratio D=5% D=2% D=1% D=5% D=2% Single pulse Ic, Collector current [A] Typ. Turn off switching time Ic, Collector current [A] Typ. Reverse recovery time 1E4 1E7 1E6 1E5 1E4 1E t P, Pulse width [sec.] IGBT transient thermal resistance at all six IGBTs operation Datasheet 14 <Revision 2.1> <21681>

15 Package Outline Datasheet 15 <Revision 2.1> <21681>

16 Revision History Major changes since the last revision Page or Reference Description of change Additional information and typo corrections 4 Pin configuration 15 Package outline Datasheet 16 <Revision 2.1> <21681>

17 Trademarks of Infineon Technologies AG µhvic, µipm, µpfc, AUConvertIR, AURIX, C166, CanPAK, CIPOS, CIPURSE, CoolDP, CoolGaN, COOLiR, CoolMOS, CoolSET, CoolSiC, DAVE, DIPOL, DirectFET, DrBlade, EasyPIM, EconoBRIDGE, EconoDUAL, EconoPACK, EconoPIM, EiceDRIVER, eupec, FCOS, GaNpowIR, HEXFET, HITFET, HybridPACK, imotion, IRAM, ISOFACE, IsoPACK, LEDrivIR, LITIX, MIPAQ, ModSTACK, myd, NovalithIC, OPTIGA, OptiMOS, ORIGA, PowIRaudio, PowIRStage, PrimePACK, PrimeSTACK, PROFET, PROSIL, RASIC, REAL3, SmartLEWIS, SOLID FLASH, SPOC, StrongIRFET, SupIRBuck, TEMPFET, TRENCHSTOP, TriCore, UHVIC, XHP, XMC Trademarks updated November 215 Other Trademarks All referenced product or service names and trademarks are the property of their respective owners. Edition <21681> Published by Infineon Technologies AG München, Germany 216 Infineon Technologies AG. All Rights Reserved. Do you have a question about this document? erratum@infineon.com Document reference ifx1 IMPORTANT NOTICE The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics ( Beschaffenheitsgarantie ). With respect to any examples, hints or any typical values stated herein and/or any information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of noninfringement of intellectual property rights of any third party. In addition, any information given in this document is subject to customer s compliance with its obligations stated in this document and any applicable legal requirements, norms and standards concerning customer s products and any use of the product of Infineon Technologies in customer s applications. The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of customer s technical departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in this document with respect to such application. For further information on the product, technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies office ( Please note that this product is not qualified according to the AEC Q1 or AEC Q11 documents of the Automotive Electronics Council. WARNINGS Due to technical requirements products may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies office. Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized representatives of Infineon Technologies, Infineon Technologies products may not be used in any applications where a failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury.