Proposed Baseline text for: Chip-to-module 400 Gb/s eightlane Attachment Unit Interface (CDAUI-8) Tom Palkert MoSys Jan

Transcription

1 Proposed Baseline text for: Chip-to-module 400 Gb/s eightlane Attachment Unit Interface (CDAUI-8) Tom Palkert MoSys Jan

2 Contributors: Haoli Qian (Credo) Jeff Twombly (Credo) Scott Irwin (Mosys) Piers Dawe (Mellanox) Mike Dudek (qlogic) Ali Ghiasi (Quantum) Supporters: Yangjing (Huawei) Mizuki Shiro (Mitsubishi) Dr. Kojima (Mitsubishi) Bill Brennan (Credo) Yonatan Malkiman (Mellanox) Oded Wertheim (Mellanox)

3 OSI REFERENCE MODEL LAYERS APPLICATION PRESENTATION SESSION TRANSPORT NETWORK DATA LINK PHYSICAL MAC AND HIGHER LAYERS RECONCILIATION CDGMII 400GBASE-R PCS RS-FEC PMA (X:8) CDAUI-8 Chip to Module PMA (8:8) PMD MDI MEDIUM Figure B 1 Example CDAUI-8 chip-to-module relationship to the ISO/IEC Open System Interconnection reference model and the IEEE CSMA/CD LAN model

4 Chip to Module insertion loss budget at 25 GHz

5 Sdd21 (db) 0-5 Insertion loss (SDD21) Meets equation constraints Frequency (GHz) Solid: 1.076*( f f) 10 MHz to GHz f GHz to 35 GHz Dashed: f f 10 MHz to GHz f GHz to 38 GHz

6 Host CDAUI-8 Compliance points

7 Module CDAUI-8 compliance points

8 CDAUI-8 host output characteristics (at TP1a) Parameter Reference Value Units Signaling rate per lane (range) ppm GBd DC common-mode output voltage (max) V DC common-mode output voltage (min) V Single-ended output voltage (max) V Single-ended output voltage (min) V AC common-mode output voltage (max, RMS) mv Differential peak-to-peak output voltage (max) mv Transmitter disabled Transmitter enabled Eye width (min) UI Eye height A, differential (min) mv Eye height B, differential (min) mv Differential output return loss (min) Equation 2 db Common to differential mode conversion return loss Equation 3 db (min) Differential termination mismatch (max) % Transition time (min, 20% to 80%) ps

9 Sddxx (db) Differential input return loss -3-4 Final return loss curve will be in between these curves Meets equation constraints Frequency (GHz)

10 Example host output test configuration

11 Selectable continuous time linear equalizer (CTLE) Characteristics

12 CDAUI-8 module output characteristics (at TP4) Parameter Reference Value Units Signaling rate per lane (range) ppm GBd AC common-mode output voltage (max, RMS) mv Differential output voltage (max) mv Eye width (min) UI Eye height, differential (min) mv Vertical eye closure (max) db Differential output return loss (min) Equation 2 db Common to differential mode conversion return loss (min) Equation 3 db Differential termination mismatch (max) % Transition time (min, 20% to 80%) ps DC common mode voltage (min) a mv DC common mode voltage (max) a mv a DC common mode voltage is generated by the host. Specification includes effects of ground offset

13 Example module output test configuration

14 CDAUI-8 host input characteristics Parameter Reference Test point Value Units Signaling rate, per lane (range) TP4a GBd Differential pk-pk input voltage tolerance (min) TP4 900 mv Differential input return loss (min) TP4a Equation 5 db Differential to common mode input return loss (min) TP4a Equation 6 db Host stressed input testa TP4 See 99E Differential termination mismatch (max) TP4a 10 % Common-mode voltage b Min Max TP4a V a Meets BER specified in E.1.1 b Generated by host, referred to host ground

15 Sddxx (db) Differential input return loss -3-4 Final return loss curve will be in between these curves Meets equation constraints Frequency (GHz)

16 Example host stressed input test Parameter Eye width 0.57 UI Applied pk-pk sinusoidal jitter Table Eye Height 228 mv Value

17 CDAUI-8 Module input Characteristics Parameter Reference Test point Value Units Signaling rate per lane (range) TP GBd Differential pk-pk input voltage tolerance (min) TP1a 900 mv Differential input return loss (min) TP1 Equation 5 db Differential to common mode input return loss TP1 Equation 6 db (min) Differential termination mismatch (max) TP1 10 % Module stressed input test a TP1a See Single-ended voltage tolerance range (min) TP1a -0.4 to 3.3 V DC common mode voltage (min) b TP1-350 mv DC common mode voltage (max) b TP mv a Meets BER specified in 1.1 b DC common mode voltage generated by host. Specification includes effects of ground offset voltage.

18 Example module stressed input test Parameter Eye width 0.46 UI Applied pk-pk sinusoidal jitter Table Eye Height 60 mv Value