Digitally controlled switch mode power supply

Transcription

1 Copenhagen University College of Engineering Center for Information Technology & Electronics (CITE) Lautrupvang Ballerup Denmark Tel.: Fax: Bachelor Project for: Spring , Mads Frimann Pedersen Digitally controlled switch mode power supply Abstract: This project deals with a three channel buck converter running digitally implemented peak current mode based on the TMS320F28035 microprocessor I accept that the report is available at the library of CITE. Student: Mads Frimann Pedersen Sign.:. Supervisor: Claus Schakow Sign.:. Company: Thrane & Thrane Coordinator: Lars Maack Sign.:. Ext. examiner Jan Møller Hansen Sign.:.

2 Table of Contents 1. INTRODUCTION PROJECT START PROBLEM FORMULATION Requirements PROBLEM ANALYSIS PROJECT DELIMITATION AND METHODS PROPOSED SOLUTION STRATEGY THEORY AND METHODS The buck converter TMS320F The digital compensator RESOURCES PROBLEM SOLUTION DESIGN Hardware Software TEST ECONOMICAL OVERVIEW CONCLUSION PRODUCT ASSESSMENT PROCESS ASSESSMENT BIBLIOGRAPHY FIGURE REFERENCES INCLUDED ON CD APPENDIX 1. MILESTONE PLAN APPENDIX 3. TMS320F28035 FUNCTIONAL DIAGRAM APPENDIX 4. CONTROLCARD SCHEMATIC APPENDIX 5. FERROXCUBE RM-5I DATASHEET APPENDIX 6. CALCULATIONS FOR THE 3.3/1.2 V SUPPLY APPENDIX 7. PROJECT SCHEMATIC APPENDIX 8. PCB APPENDIX 9. SOURCE CODE APPENDIX 10. START-UP CIRCUITRY COST APPENDIX 11. TEST SETUPS

3 Preface I would like to thank Thrane & Thrane for letting me write my bachelor project on their premises providing office, tools and instruments. Thanks to my company supervisor Claus Schakow for taking the time to form an overall project description and for answering whatever questions that might arise with little or no wait, to Anders Lange from Texas Instruments for providing a very useful introduction to the C2000 family microprocessors, to Lars Maack for taking the time to be my coordinator and for giving pointers and feedback to the report, to my parents for reading through the report and thanks to everyone whom I have talked to or have discussed this project with. This project was running from February through May 2012 with no major delays except from the always tedious soft- and hardware bugs which any project is bound to have. The work load has been close to full time pretty much all the way though the project. It has been really nice to be in a large company where the right piece of equipment is at hand no matter how obscure it might be, to have round-the-clock access and to be treated like an employee with all the perks that might follow. 2

4 1. Introduction 1.1 Project start This project contains an investigation into the use of digital power in switch mode power supplies for use in maritime antennas and radios, land mobile communication systems etc. Currently Thrane & Thrane makes use of analog switch mode power supply modules which is implemented in a wide range of their products. The objective of this project is to design and produce a digitally controlled switch mode power supply, with the same specifications as the analog supply in use. Furthermore investigate the pros and cons of a digital solution. Due to the fact that these power supplies are used in many of Thrane & Thrane s products and the quantities of these products fabricated has grown, an economical perspective are of great interest. 3

5 1.2 Problem formulation A multichannel switch mode power supply controlled by a microprocessor should be designed and produced. The design must be optimized to production costs and the total cost should be compared to an analog converter which is currently implemented in many of Thrane & Thrane s products. The power supply should match the specifications of the analog power supply. As a minimum one of the supplies should be running peak current mode Requirements Supply 1: Input DC voltage range: V Output DC voltage: 5.75 V ±250 mv Max output ripple voltage: 50 mv peak to peak Output load range 100 ma - 4 A Supply 2: Nominal input DC voltage: 5.75 V Input DC voltage range: 5.50 V 6.00 V Output DC voltage: 3.3 V ±150 mv Max output ripple voltage: 20 mv peak to peak Output load range 100 ma A Supply 3: Nominal input DC voltage: 5.75 V Input DC voltage range: 5.50 V 6.00 V Output DC voltage: 1.2V ±60 mv Max output ripple voltage: 15 mv peak to peak Output load range 100 ma A All supplies must have a power-up rise time: 0.2 ms t r 50 ms The 1.2 V supply and the 3.3 V supply should ramp together and never be more than a diode voltage drop above the output of the 5.75 V supply. 4

6 2. Problem analysis To proper analyse this project and to form the problem formulation a series of questions has to be made. Like what is the input and output voltages? How large currents must the supply source? Is it necessary to have isolation in the converter? Which converter topology should be used? What are the requirements to ripple and step load transients? And are there any requirements to their output voltages at start up? A digital power supply must have some kind of processor. What are the features needed in such a device? Are some manufacturers better than others? And is it possible to get advanced processors at a reasonable prize? The processor obviously needs some sort of supply at start up how can this be managed, and can it be done without ruining the overall efficiency of the converter. Can the processor drive the FET s directly or must it have some kind of driver circuitry? If a driver is needed, can this be supplied from the same supply as the processor or should it have its separate supply? 3. Project delimitation and methods 3.1 Proposed solution strategy A variety of manufactures like TI, Microchip and Atmel makes processers for real time applications but not all has the same focus on digital power. It is clear that Texas Instruments has very good support in that area, resulting in good documentation, application notes, software libraries making programming easier and they are available in a price range that is competitive to the rest. Furthermore a company called Biricha Digital offers library packs intended for power supply applications. So having decided on a TI product in the C2000 family which one should it be? In digital switch mode applications it is crucial to have a fast clock rate making the calculation time shorter, fast ADC s with high resolution and high resolution PWM modules. A good compromise between features and cost would be the piccolo series. One of the devices from the piccolo series called TMS320F28035 is available on what TI calls a CONTROLcard which is a little PCB with on board flash programming and debugging. This device might be overqualified but for the sake of this project it will be a good way to get the programming abilities and to see what features are needed. The processor can then easily be downgraded. Since there is no requirement for isolation between input and output in this converter and all input voltages should be converted down the obvious choice is the buck topology. In order to make the buck converter more efficient the freewheeling diode is replaced with a second FET making this a synchronous buck converter. 5

7 In order only to have to make the large voltage step down once the 1.2 V supply and the 3.3 V supply will be running from the 5.75 V supply It is requested that at least one of the supplies preferably all, should run in peak current mode. The problematic part of this is to generate the slope compensation ramps necessary to avoid sub harmonic oscillation. One way to create such a ramp is to calculate it in the piccolo s arithmetic co-processor however this way could only produce a ramp for a single supply. Fortuity the DAC modules in the piccolo have built in ramp generators which are perfect for generating slope compensation ramps. The piccolo processor cannot drive the FET s on its own therefore gate drivers have to be used. This introduces a problem on how these should be supplied. The gate drivers on the 3.3 V and 1.2 V supplies do not introduce a problem since they run from the 5.75 V supply so they can be supplied directly from this voltage. The gate driver for the 5.75 V supply on the other hand is a little bit more tricky. It is not possible to get gate drivers with a 5 V supply, that can drive FET s which run up to 48 V these all have to be supplied by 9-15 V. In order to get this voltage with minimum efficiency loss a second winding will be introduced on the inductor of the 5.75 V supply. This winding will then be a part of an unregulated flyback converter producing the 10 V needed. A disadvantage of running peak current mode is that an image of the current in the inductor is needed in order to regulate. There are numerous ways to get a voltage feedback of the current in the inductors some lossless others not. The lossless methods are preferable but they can in some situations be more expensive. All of this is shown in form of a block diagram in Figure V supply 10 V PWM module Gate driver FETs Iout Output filter Vout 5.75 V out Comparator module Vin VIout Current mirror Microcontroller A/D converter PWM module Comparator module A/D converter 5.75 V supply Gate driver 3.3 V supply FETs Iout VIout Output filter Current mirror Voltage divider Vout Voltage divider 3.3 V out PWM module Gate driver FETs Iout Output filter Vout 1.2 V out Vin Power-up circuit Comparator module A/D converter 1.2 V supply VIout Current mirror Figure 1 Converter block diagram 6

8 3.2 Theory and methods The concept of digital power has a very wide span. Some IC manufactures makes analog switch mode controllers with logic level inputs for control thus calling them digital but the way of making a digitally controlled switch mode power supply which is in focus in this project, is theoretically to take an ordinary switch mode power supply; remove the analog controller and put in a microcontroller instead which then will generate the PWM signal to drive the FETs on the basis of the feedback provided through the ADCs. Some of the benefits of using a microcontroller is that it is possible to run multiple supplies with different specifications and topologies on the same controller, input voltage and output load can be monitored and logged, coefficients in the controller can be changed dynamically or a non-linear control algorithm can be implemented etc. However there are drawbacks to a digital system as well. The digital system comes with a control loop delay which will cause the phase margin to deteriorate. The switch frequency will be limited by the time it takes to sample and do the calculations for the controller. Furthermore there is a question of how the microprocessor itself should be supplied The buck converter The buck is a fairly simple way to convert voltages down. It consists of two switches an inductor and a capacitor. The buck converter operates in two states as illustrated in Figure 2. In the first state the inductor is connected to the source charging energy into the inductor. And in the second state the inductor discharges into the load. The capacitor on the output then stores the energy in order to avoid a large voltage drop while the inductor is re charged. State 1 State 2 Load Load Figure 2 Buck states Under normal operation current will always be running in the inductor this is known as continuous current mode (CCM), but at low load situations where the load current is less than half the ripple current in the inductor, the inductor gets discharged when sourcing current to the load. This is discontinuous mode (DCM). 7

9 Figure 3 - CCM and DCM When going from CCM to DCM, the output characteristics changes making it difficult to control if regulating solely on the output voltage. This type of control is called voltage mode and has the further disadvantage of the inductor and the capacitor creating a double pole which has to be compensated for thereby increasing the calculation time. Alternately the supply can be controlled on the current running in the inductor. One way of doing this is by running the supply in peak current mode. - - Vref I L Vout Error Amp. PWM Output filter Ri (current feedback gain) Voltage divider Figure 4 Peak current mode control loop As seen in Figure 4 the peak current mode controller consists of two control loops an inner loop which regulates the peak current in the inductor according to the input reference. The input reference is generated by the outer loop where the output voltage is subtracted from a reference value and then fed through an error amplifier equipped with phase compensation. When controlling the current in the inductor the inductor itself is acting as a current source thereby eliminating the double pole. A disadvantage of a current mode supply is that it can suffer from sub harmonic oscillation. This is due to the fact that the average current is increasing as function of the duty cycle. This is illustrated in Figure 5 on the left. 8

10 Figure 5 Slope compensation of current feedback This can be compensated for by subtracting the current feedback with a compensation ramp, illustrated in Figure 5 on the right. The size of this ramp can be calculated from the downslope of the ripple current. The slope of the compensation ramp should be somewhere in between 50% and 90% of the downslope of the ripple current. According to Biricha Digital is there usually need for rather large compensation ramps in digital implementations. Figure 6 Analog peak current mode In Figure 6 a principle schematic of analog peak current mode is shown. It can be seen how the output voltage is scaled down, fed through the error amplifier and used as the reference for the comparator controlling the current through PWM. The current feedback is subtracted by the compensation ramp and used as input to the comparator TMS320F28035 The TMS320F28035 Piccolo B is a device designed specifically for real time applications. It is based on the 32 bit C28x core running on a 60 MHz clock, optimized for fast interrupts and has enhanced control peripherals for real time control whereas for the purpose of this project the most interesting might be the enhanced PWM module (epwm) and the comparator block. A functional diagram is 9

11 shown in Appendix 1 on page 45. The integrated analog comparators are making it possible to implement an effective semi analog peak current mode. Figure 7 F28035 comparator module A block diagram of the comparator modules are shown in Figure 7 from this it can be seen how the negative input of the comparator can be supplied internally from the 10-bit DAC which can be supplied with a fixed value via DACVAL [9:0] or with a decreasing value via the ramp generator. On the output there are the possibilities to invert the signal and to run the comparator synchronous or asynchronous. Figure 8 F28035 PWM module 10

12 In Figure 8 a block overview of the comparator module is shown. Some of the useful features of this module are the dead band feature which makes it possible to control FETs in a half bridge with dead band eliminating the risk of shot through where both FETs are on at the same time, and the trip zone module where the duty cycle of either PWM channel A and B can be overruled by the use of interrupts or internal signals. Unfortunately if running an application by the use of trip zones the dead band module cannot be used as it is placed before the trip zone module in the signal path for this reason the dead band must be taken care of externally. Figure 9 Digital peak current mode Figure 9 shows how this can be implemented in the Piccolo microprocessor. In the piccolo the output voltage is sampled by the ADC, subtracted by the reference and fed to the digital controller. The output from the controller is then set as a max value in the ramp generator of the DAC where the slope compensation is performed. The analogue value from the DAC is then passed internally to the negative input of the comparator where the current feedback is connected to the positive input. The output of the comparator then controls the duty cycle of the PWM module. This is done in a way where the duty cycle is set to 100% in the start of every period. The comparator then trips the PWM module forcing its output low, once the current limit is reached. A blanking window is introduced to avoid false tripping caused by the top FET being turned on. In order to design any kind of SMPS the first thing to be decided upon is the switch frequency. In digital power this is restrained by the calculation time of the controller given that all calculations have to be done within one switch period. To investigate the calculation time of the controller the Multichannel buck DC/DC developer s kit were used in combination with the TMS320F28035 CONTROLcard. This kit only runs in voltage mode resulting in more calculation time. Measurements do show based on a single running SMPS that it should be possible to run three supplies with a 250 khz switch frequency. When running multiple supplies the supplies are run out of phase in order to avoid the interrupts starting the calculations all being in the same time and causing delay. This has the further effect that the 3.3 V and 1.2 V supplies which is supplied from the 5.75 V, does not start to consume power at the same time. The TMS320F28035 CONTROLcard is a PCB mounted with a F28035 microprocessor and a USB interface for programming and real time silicon debugging. The CONTROLcard is furthermore equipped with anti-aliasing filters on some of the analog inputs which should be taken into account when designing voltage dividers 11

13 to supply the output voltage feedback thus resistance added in series with this will lower the crossover frequency and if the crossover frequency gets to low it will cause an unwanted delay. The schematic of the CONTROLcard can be seen in Appendix 4 on page The digital compensator The compensator is where the compensation for the converters output characteristics is calculated in Figure 9 a bode plot of a buck output stage is shown. PLoad ZESR Figure 10 Buck output characteristics The objective for the compensator is to manipulate the gain and phase in order to achieve a phase margin of min. 60, a gain margin of min. 10 db and a bandwidth of 10 khz or more. In order to simulate the phase margin and bandwidth of the system in MATLAB transfer functions are set up for both the current mode buck and the compensator. According to Biricha Digitals design paper [1] the transfer function for a current mode buck can be described by three terms. A DC model H DC, a power stage small signal transfer function H B (S) and a high frequency transfer function H HF (S). The complete transfer function for the peak current mode buck will then be. ( ) ( ) ( ) ( ) ( ) ( ) Where is the load, is the gain in the current feedback, is the inductance, is the time of the switch period, is the ESR of the capacitor and is the output capacitance. For controlling a current mode buck Type II compensation is needed. The transfer function for such a compensator is. ( ) ( ) ( ) ( ) 12

14 Where if following the Biricha notes, which will result in a stable system but not necessarily the best phase margin. Then should cancel out the zero caused by the output capacitance and its ESR is then set to 20% of the crossover frequency to achieve a reasonable phase margin. And finally is calculated to get the desired crossover frequency. ( ) ( ) However if a higher gain margin is desired the zero should be moved down below the pole caused by the output capacitance and the resistance of the load. And the pole can then be adjusted to gain the desired crossover frequency. Bode plots and phase margin plots can now be made in MATLAB by creating an open loop transfer function of the entire system by multiplying the two transfer functions with the gain of the voltage divider on the voltage feedback and the total delay of the system which is a huge factor for digital power because it deteriorates the phase margin. ( ) ( ) Pole and zero placements can now be simulated but in order to be able to use these, a digital compensator is needed. A digital type II compensator is supplied with the Chip Support Library (CSL) from Biricha Digital. This is essentially a linear difference equation which is derived from the S-domain transfer function using bilinear transformation substituting with The linear difference equation is Where [ ] [ ] [ ] [ ] [ ] [ ] 13

15 ( ) ( ) ( ) ( ) 3.3 Resources The software tools used for this project were TIs CodeComposer 5 for writing C- code programming and debugging the microprocessor along with TIs CONTROLsuite which provides documentation of the TI devices. And MATLAB was used for calculations and simulations. Some of the hardware used for test and measurements are the Maynuo M9812 DC electronic loads, the HP4194A Impedance/Gain-Phase Analyser, Kenwood DLE1051 bench multimeters, FLIR E1 thermal camera and the Agilent DSO7034B and Tektronix TDS 3012B oscilloscopes. 4. Problem solution 4.1 Design In this section the design and implementation of a digitally controlled buck converter running in peak current mode is described Hardware For a complete schematic of the power supply s hardware refer to Appendix 6 on page 52. In Figure 11 a block diagram of the buck converters is shown this fits all of the supplies with minor changes for instance is a voltage divider not necessary on the 1.2 V supply and the 5.75V supply has a secondary winding on its output inductor to supply the gate driver and the op-amps. Microcontroller Gate driver FETs Iout VIout Output filter Current mirror Vref Vout Voltage divider Out Figure 11 Digitally implemented buck The gate driver is supplied with a PWM signal from the microprocessor on the base of this it drives two N-channel mosfets in a half bridge which will switch the input voltage resulting in a square wave from 0 to Vin. This is then filtered in the output 14

16 filter which consists of an inductor and some capacitance. The current in the inductor is then measured and returned as a feedback to the microcontroller and the output voltage is divided down and returned to the microcontroller as well. A circuit like this is realized and shown in Figure 12. Figure V supply schematic Shown in Figure 12 is the schematic of the 3.3 V supply. Furthest to the left is the gate driver U3 which is connected to the two FETs Q3 and Q4. C14 is the bootstrap capacitor which holds the charge to keep the top side FET open. L2 and C16 is the output filter where the current running in L2 is measured by amplifying the voltage over the series resistance this is done U4 which also compensates for the effects of the inductor. The output voltage is divided by the resistors R19 and R21 to provide the output voltage feedback to the microprocessor FETs and drivers Early in the design phase the FETs of the three supplies were chosen to be the same as the ones in the existing product which means IPD135N08N3 MOSFETs will be used for the 5.75 V supply and IRLMS2002TRPBF MOSFETs will be used for the 3.3 V and 1.2 V supplies. This decision was made in order to get some working hardware early in the project which then later could be revised if needed. The FETs for the 3.3 V and 1.2 V supplies is rather ideal for the task with a drainsource voltage of 20 V and a continuous drain current of 5.2 A. Whereas the FETs for the 5.75 V supply might be over dimensioned with a continuous drain current of 39 A. To make sure the FETs are suited an approximation of the power dissipation in the FETs is calculated as a sum of on state losses and switch losses and compared to the max ratings in the datasheet. ( ) 15

17 If the assumption is made that the gate is driven by a current of 1 A which is well within the capabilities of the gate drivers on the market, the power dissipation can be calculated to be. V IN = 15 V V IN = 48 V 5V75 Top 5V75 Bottom 5V75 Top 5V75 Bottom 3V3 Top 3V3 Bottom 1V2 Top 1V2 Bottom P ON P switch P total [mw] As the FETs on the 5.75 V supply can dissipate 79 W and the FETs on the 3.3 V and 1.2 V supplies can dissipate 1.3 W they will have no problem working in this application. The FETs cannot be driven directly from the outputs of the microprocessor due to this a gate driver circuit is needed. Since a voltage higher than the input voltage is needed to turn on the top FET the way of making such a circuit is by the use of a gate driver IC which can drive the FETs with very limited external components. There are some requirements to these gate drivers in order for them to work in this application. The gate driver must be able to drive two N-channel MOSFETs in a half bridge configuration with dead band. The gate driver has to be controlled by a single 3.3 V PWM signal and for the gate driver on the 5.75 V supply, it should be able to work with input voltages up to 48 V. For the 5.75 V supply the LM5106 from National Semiconductor was chosen as it fulfils the requirements as one of the very few on the market and is the most inexpensive. The drawback of the high voltage gate drivers is that none of them can be supplied by the 5.75 V which is highest voltage available in this power supply. This is due to the fact that higher voltage FETs has higher Gate-source threshold voltages and since the gate driver uses its supply voltage on top of the input voltage via a bootstrap circuit the supply voltage has to be of a certain size. The LM5106 has programmable dead time. This is fixed dead time adjusted by the value of a resistor. Measurements show that a dead time of approx. 100 ns is needed to avoid shot through the resistor can then be determined by the graph in Figure 13 where 15 kω will give dead time of approx. 125 ns. 16

18 Figure 13 Dead-time vs. resistor value The gate drivers needed for the 3.3 V and 1.2 V supplies only needed to work with the input voltage of 5.75 V this means a greater selection of devices is available with more features. For these two supplies the gate driver chosen is the TPS28225 from Texas Instruments. The TPS28225 is able to run from the 5.75 V and has adaptive dead time. This means that it monitors the voltage in the switching note and when it reaches an unspecified threshold a dead time of 14 ns begins. This efficiently minimizes the dead time to the shortest possibly. Both the gate drivers need external bootstrap circuits. The LM5106 should have an external diode and capacitor whereas the TPS28225 has the diode integrated. The diode for the LM5106 should be a schottky diode with a reverse bias voltage greater than 48 V. The bootstrap capacitors should hold the charge needed to turn on the FETs and keep them on. As a rule of thumb the capacitance can be calculated as the total gate charge divided by the maximum voltage drop wanted then multiplied by a factor ten to compensate for gate-source, diode, capacitor and level shifter leakage. The gate charge of both FETs is about 25 nc and a voltage drop of no more than 1 V from the supply is wanted Inductors The Inductor for the 5.75 V supply is unique because of its secondary winding for the flyback converter. Therefore it will have to be custom made which is not a low cost solution. The first thing that should be calculated is the actual inductance of the primary winding. The inductance is accountable for the ripple current running in the inductor. The ratio between the ripple current and the output current will be referenced to as the LIR factor as in [2]. The greater the LIR factor, the faster the transient response however the disadvantage of a large LIR factor is that the ripple voltage on the output will be harder to supress. In this design a LIR factor of 0.25 has been used. This is more in favour of the low output ripple than the transient response, as this power supply is not exposed to large load changes in normal operation. The inductance is calculated as follows. 17

19 ( ) ( ) The next thing that should be calculated is the maximum current that will run in the inductor as the inductor should be able to supply this current without saturating. 20% is then added to this current in order to compensate for any tolerances. ( ) ( ) ( ) Since almost all of the energy in an inductor is stored in the core a suitable core is found by choosing the style, material and air gap. The RM core was chosen as it has fine properties for inductors and transformers and almost encloses the inductor thus having a shielding effect preventing radiation and reducing electromagnetic interference. Furthermore these was available at the company in the 3F3 material which is quite good at frequencies around khz. The size of the core and the air gap is then determined by the energy it should be able to deliver. In the core the energy is stored in the core itself and in the air gap. The core does not store as much energy as the air gap and it is subject to hysteresis whereas all the stored energy in the air gap is available. The fastest way to determine if a core can contain energy enough would be to calculate the air gap using the approximated formula. (( ) ) ( ) ( ) Where V g is the volume, d g is the diameter and l g is the length of the gap. This calculation is for the RM-5i core which is the smallest core that will supply the sufficient energy. From the Ferroxcube RM-5i Datasheet at page 50 in the appendix it can be seen that the air gap must be 380 µm and the inductance will be 100 nh pr. turn squared. The number of turns will therefore be. The inductance will be. The turns on the secondary winding can then be calculated from the basic transformer equation 18

20 Ideally the secondary winding should fill up an entire layer of the bobbin thus should the diameter of the wire be. Taking account of the insulation thickness a 0.14 mm wire is chosen. The wire diameter of the primary winding is then determined to be. ( ) ( ) Where A window is the winding area of the bobbin and F is the fill factor which is set a bit low. Tests have afterwards shown that there is room for a 0.6 mm wire or two 0.4 mm wires wound bifilar. The last was chosen due to the large wire being hard to handle on the bobbin and because it should be less affected by the skin effect. Where the skin depth at 250 khz is The inductors for the 3.3 V and 1.2 V supplies are ordinary inductors and the only two parameters that are necessary to calculate are the inductance and the maximum current these calculations can be found in Appendix 6 on page Capacitors The output capacitance and ESR of the capacitors is calculated according to the maximal allowable voltage overshoot at load step and the ripple voltage. ( ) ( ) Where is the voltage overshoot at load step and 20% is added to take the tolerances of the capacitors into account. The ESR of the output capacitor can be calculated by the equation. ( ( ) ) Where is the output ripple voltage. Calculations for the 5.75 V supply. ( ) ( ) ( ) 19

21 ( ( ) ) From the capacitors available two electrolytic capacitors on 330 µf and 90 mω ESR, was chosen. Calculations for the 3.3 V and the 1.2 V supplies can be found in Appendix 6 on page 52. All supplies have a 100 nf ceramic capacitor in parallel with the output capacitance in order to filter out any high frequency spikes Current feedback There are numerous ways to get a voltage feedback of the current in the inductor of the power supplies. Some introduces a loss like if a sense resistor is put in series with the inductor and then amplifying the voltage over the resistor, and others are lossless like measuring the voltage over the topside FET using its on resistance as a sense resistor or using the ESR of the inductor itself as a sense resistor. The disadvantage of measuring over the FET is low accuracy, the on resistance varies with different FETs and it drifts with temperature. For the 3.3 V and 1.2 V supplies the current feedback will be made by amplifying the voltage over the inductor. Since an inductor has a zero at f o a filter will be calculated which can compensate for the characteristic of the inductor. ESR Resistance Gain Frequency f 0L Frequency f 0C Figure 14 X-over of inductor and compensation filter In Figure 14 on the left it is illustrated that f o of the inductor is where so by knowing the inductance and measuring the resistance the crossover frequency can be determined. The resistance of an inductor increases with frequency therefor the voltage will increase as well if the current is fixed. The filter needed to counteract the inductor is therefore a low-pass filter as seen in Figure 14 on the right this can then be designed to have the same crossover frequency. The voltage over the inductor will be amplified by an op-amp in a differential amplifier setup as shown in Figure 15 where the voltage on the negative input is 20

22 subtracted from the voltage on the positive input and the difference is amplified by the ratio Figure 15 differential amplifier A low-pass filter is implemented on this amplifier by inserting a capacitor in the feedback path and from the positive input to ground as seen in Figure 16. This will efficiently damp high frequencies with a crossover frequency at Figure 16 differential amplifier with compensation The op-amps that will be used for this application will be OPA830 due to their low cost and rather high gain bandwidth product at 110 MHz. The common mode rejection ratio of these amplifiers is 80 db which is in the lower end of the scale but tests show that it is sufficient. To guaranty proper amplification of the signal the bandwidth of the amplifier should be at least a decade higher than the amplified signal which is the switch frequency. Restricting the gain of the amplifier to In order the Match the components R1, R2 and C1 to available std. component values the gain of the amplifier is set to 30 and R1 set to 1.2 kω then R2 and C1 can be calculated to This gives a current to voltage gain of 21

23 Unfortunately this method cannot be used on the 5.75 V supply because of the voltage over the inductor being too high to measure with an op-amp. One way to get around this is to place a passive filter over the inductor as in [3] and then measure the voltage over the capacitor as in Figure 17. This current sense method was implemented in the first revision of the hardware and works well. Figure 17 Filter sense circuit The only drawback is that the amplifier which amplifies the signal must have high input impedance in order to not to load the filter too heavily. Therefore an instrumentation amplifier must be used consisting of tree op-amps. This solution is however too expensive for this project where the optimal solution was found to be a 20 mω sense resistor in series with the inductor and a single op-amp to amplify the voltage difference over the resistor. The op-amp used for this application is the OPA830 chosen on the basis that it is cheaper to mount three op-amps of the same type than of two different types. Due to this op-amp cannot go all the way down to the lower supply rail a bias voltage is inserted into the positive input by a resistor to the positive supply. In order to calculate the gain of this amplifier it is decided upon which voltage the 4 A should correspond to. This voltage is set to 2.5 V leaving good headroom up to the 3.3 V which is the maximum input voltage of the comparator. According to Ohms law the output voltage of the amplifier will be This can then be rearranged for the amplifier gain The input resistors R1 is set to 2.7 kω and the feedback resistor R2 can then be calculated to The current to voltage gain of the circuit will then be Flyback converter The objective of the flyback converter is to supply the 5.75 V supply gate driver and the op-amp for the current sense circuit. It needs to produce 10V, around 10 ma and is basically just a diode and a capacitor rectifying the AC from the second winding of the 5.75 V inductor. The diode is dimensioned to withstand the voltages of the secondary winding which can get up to 22

24 In top of this voltage spikes and oscillations can occur at the time of the switch and therefore the diode is chosen to be with a 200 V reverse voltage Snubbers Snubbers are introduced to the circuit where switches such as FETs or the diode, produce high frequency oscillations that need to be damped in order to meet the ripple voltage requirements for the outputs. These oscillations appear when the capacitor in the switch forms a resonance circuit with the spread inductance of a coil and/or the spread inductance of wires and tracks. The purpose of the snubber is to introduce resistance to the resonant circuit which will lower the Q thus damping the oscillations. A capacitor is then put in series with the resistor to avoid the power dissipation from a DC current running in the resistor. This capacitor is then charged and discharged every time the switch turns on/of, this adds to the switching losses. For this reason the capacitor must be chosen just large enough for the resistor to be in contact with the switch. A rule of thumb says that the capacitor in the snubber should be 3 times the internal capacitance of the switch. The resistor should then be dimensioned so that Q for the resonant circuit is approximately 1. By measuring on the output of the 5.75 V supply as seen upper most in Figure 18 it can be seen that it is clear a snupper is needed with a ripple voltage at 85 mv. The oscillations are traced to the diode on the flyback winding of the inductor which is shown in the bottom of Figure 18. Figure 18 Output without snubber For designing the snubber needed the capacity within the diode is part of the resonant circuit needs to be determined. To find this unknown capacity a trial-anderror method is used. By adding extra capacitance across the diode it is analyse the capacitance of the diode. Given that if a capacitor C y is added until the frequency has dropped to ¾ we can set up the equation shown below and isolate 23

25 ( ) ( ) This means that by adding some capacity until the frequency has dropped to the correct value and then multiplying the added capacity by 9/7 the capacity of the diode can be found. Figure 19 Oscillations on the fly-back diode In Figure 19 a zoom of the oscillations measured on the diode is shown. From this the frequency of the oscillation can be measured to be 32.1 MHz. Capacitance is now set in parallel with the diode until the frequency is reduced to ¾ of the original oscillations. 24

26 The frequency of 25.5 MHz is reached when putting 27 pf in parallel. From this the capacity of the diode is calculated: The snubber capacitor should be 3 times this value: ( ) To be able to calculate the size of the snubber resistor the inductance of the resonant circuit is needed: ( ) ( ) ( ) The resistor is then calculated from the formula for Q in a parallel circuit with Q = 1 The result is then verified by the measurements in Figure 20 where it can be seen that the oscillations on the flyback diode has been damped and ripple voltage is reduced to 44.5 mv. Figure 20 Output with snupper A snupper is designed in a similar fashion for the bottom FET of the 3.3 V supply Start-up circuitry Upon start up there is a need for supply to the processor and circuits of the 5.75 V supply in order for it to get started and itself produce the voltages needed for operation. In Figure 21 a block diagram can be seen of the start-up circuit which essentially is just two linear regulators with a switch to turn them off once power supply is up and running. 25

27 Switch 10 V Regulator 3.3 V Regulator Vin Vin 10 V 3.3 V out OFF/ON 10 V out Figure 21 Start up circuitry The linear regulators are quite inefficient but as in comes this circuit should only be in effect for maximal 100 ns before the processor is running and has shut it off. Therefore has the design criteria been the cost in this case. Figure 22 Start up circuitry In Figure 22 a schematic of the start-up circuit is shown. U8 is a high side switch this is conducting when it can source a current from its input pin to ground. This happens at start up where the signal PSU_on is low and therefore is the transistor Q7 conducting. The voltage regulators are chosen to be of the type LM317 because they are inexpensive and they can operate with a voltage difference of 40 V from input to output. When the switch is closed the voltage regulator U9 is supplied with the input voltage which it regulates down to ( ) ( ) The next stage then regulates the voltage down to ( ) ( ) In series with both supplies are schottky diodes to make sure that current does not run into the voltage regulators when they are turned off and Q8 makes sure that the 3.3 V start-up voltage does not go to the 3.3 V output of the actual supply. 26

28 Printed circuit board A PCB is made for the power supply. In the design of this PCB the routing has been with focus on making the areas where HF currents are running as small as possible as well as grouping the gate drivers and FETs as close to the output filter as possible. A number of other design precautions noted in the component datasheets has been followed in order to gain the best results. The final layout can be found in Appendix 8 on page Software The software for the power supply makes use of header files provided by Biricha Digital. These contain functions to initialize the microprocessor, configure peripheral modules; set different bits etc. for the source code refer to Appendix 9 on page 60 As the most of the program is very time dependant when controlling real time applications. Most of the actions in the microprocessor are caused by interrupts where the different hardware blocks is linked together causing them to chain react when the process is started. Take for instance a single one of the supplies used in this project where the entire event chain is started by the PWM module. Channel B of the PWM module is set up to start the sample conversion in the ADC module once the sample is ready the ADC module triggers a interrupt service routine (ISR) where the value is read from the ADC and passed on to the controller which calculates the new threshold for the comparator. All of this takes 2.6 µs so Channel B is configured so all of this can be done just when the new PWM cycle starts as shown in Figure 23. PWM channal A D PWM channal B 2.6 us Ts Start of ADC convertion Figure 23 PWM channel B timing The comparator then trips the PWM module once the current threshold is reached thereby adjusting the duty cycle. When constructing the software for the supplies the software for each supply was made individually to make sure all of the supplies are running optimal before the three programs was merged. Unfortunately when the code was merged it became clear that the initial assessment of calculation time for each supply was off. As a result of this it is not possible to run all three supplies at 250 khz. In order to get all the supplies running the switch frequency was lowered until the program was running this was at 180 khz. This will have effect on the hardware performance but tests shown in 4.2 Test at page 33 that the specifications for the supply can still be met. 27

29 One of the things that were not considered when setting the initial switch frequency were the time it takes to save the value of the program counter when an interrupt is serviced thereafter to return. This can be one of the reasons why the switch frequency would have to be lowered. In Figure 24 the load on the ADC and CPU is illustrated in a timing diagram based on measurements of ADC conversion time (0.95 µs) and the execution time of the ISR (1.2 µs) us 1.2 us Figure 24 System timing From this the CPU should be loaded of the cycle resulting in a load of The LED can be used to make an approximated analyse of the CPU load. By making the assumption that the CPU load is proportional to the ratio between the time period of the LED at no load and the actual time period. The actual load of the CPU is approximated to ( ) ( ) 28

30 Code analysis In Figure 25 a flow chart of the code execution is shown. Start Initialization Configure the 5.75/ 3.3/1.2 V supply IsrADC5/3/1V Initialization Initialize system Configure PWM PWM channel B triggers start of ADC conversion Acknoledge ADC interrupt No Time to toggle LED? Configure the 5.75 V supply Configure ADC End of convertion triggers ADC interrupt (IsrADC5/3/1V) Read ADC Yes Configure the 3.3 V supply Execute 2p2z controller Toggle LED Configure 2p2z controller Interrupts to service? No Configure the 1.2 V supply Setup phase the of the supplies Configure the comparator and slope compensation Set max ramp height of DAC return Yes Return Service Interrupt Enable PWM outputs Return Figure 25 Software flow chart The code of the main() function is now analysed. In order to use any of the peripherals the system and the peripherals must be initialized by the functions SYS_init(); //Initialize the microprocessor ADC_init(); //Initialize the A-D converter This initializes the system and AD converter and sets up the system for internal 60 MHz clock. Next the output pins are configured. // Configure output pins GPIO_config( GPIO_39, GPIO_DIR_OUT, false ); GPIO_config( GPIO_31, GPIO_DIR_OUT, false ); // Configure PWM module 4 to 0% duty and connect it to the output pin PWM_config( PWM_MOD_4, PWM_nsToTicks(period_ns), PWM_COUNT_UP ); PWM_setDutyA( PWM_MOD_4, 0); PWM_pin(PWM_MOD_4, PWM_CH_A, GPIO_NON_INVERT); In this case PWM module 4 is used as an output controlling the power up supply by running it at either 0% or 100% the PWM module is used for this because these stay low when the microprocessor is powered up where the GPIOs are only low 29

31 from start up when running the program from FLASH when running from RAM the GPIOs are sourcing until it is configured. Now the three supplies are initialized. All three initialization routines are identical so only the 1.2 V supply will be analysed here. PWM_config( PWM_MOD_3, PWM_nsToTicks(period_ns), PWM_COUNT_UP ); PWM_setDutyA( PWM_MOD_3, PWM_nsToTicks(period_ns)*0.8); PWM_setDutyB( PWM_MOD_3, PWM_nsToTicks(period_ns-2600) ); PWM_setAdcSoc(PWM_MOD_3,PWM_CH_B, PWM_INT_CMPB_UP ); PWM_configBlanking( PWM_MOD_3, PWM_CMP_COMP1, GPIO_NON_INVERT, true ); PWM_setBlankingWindow(PWM_MOD_3, PWM_nsToTicks(420)); PWM_setTripZone( PWM_MOD_3, PWM_DCEVT, PWM_TPZ_CYCLE_BY_CYCLE ); PWM_setTripState( PWM_MOD_3, PWM_CH_A, GPIO_CLR ); PWM_setTripState( PWM_MOD_3, PWM_CH_B, GPIO_NO_ACTION ); The PWM module is configured to count up with a period time of period_ns which is defined to 5556 ns for a 180 khz switch frequency Channel A is connected to the gate driver. In theory the duty cycle is set to 100% and the channel is then tripped when the current increases. But in practice the duty cycle is limited to 80% for this supply, in case something happens to the circuit providing the current feedback. Channel B is timing the start of the ADC conversion by triggering the ADC on its compare match which is set to 2600 ns before the new cycle starts. The blanking window of 420 ns is then setup for the comparator which then once it is trigged sets the digital compare event PWM_DCEVT PWM_DCEVT is then used to trigger the trip zone module which is set up to a cycle by cycle trip which will clear channel A and have no effect on channel B. The ADC is then configured by the code #ifdef SILICON_REV0 ADC_config( ADC_MOD_5, ADC_SH_WIDTH_7, ADC_CH_B4, ADC_TRIG_EPWM3_SOCB ); #endif ADC_config( ADC_MOD_6, ADC_SH_WIDTH_9, ADC_CH_B4, ADC_TRIG_EPWM3_SOCB ); ADC_setCallback( ADC_MOD_6, IsrAdc1V, ADC_INT_3 ); According to the F28035 errata sheet if running on rev.0 silicon the first sample of the ADC can be invalid. Therefore if SILICON_REV0 is defined two ADC modules is setup to sample on the same trigger. Given that the ADC prioritizes in a round robin fashion then will ADC module 5 contain the invalid sample which then later can be dumped. An ADC call back is then setup to trigger an ISR once the ADC is done converting. The controller is then initialized by the function CNTRL_2p2zInit(&ctrl1V,REF_1V,_IQ26(A1_1V),_IQ26(A2_1V),_IQ26(B0_1V),_IQ26(B1_1V),_IQ26(B2_1V),_IQ23(K_1V),MIN_DUTY,MAX_DUTY_1V ); 30

32 The comparator is configured with its integrated DAC to perform the slope compensation needed. CMP_config(CMP_MOD_1, CMP_ASYNC, GPIO_NON_INVERT, CMP_DAC ); Comp1Regs.DACVAL.all = 0; EALLOW; Comp1Regs.DACCTL.bit.FREE_SOFT = 0; Comp1Regs.DACCTL.bit.DACSOURCE = 1; //use ramp gen as input for DAC Comp1Regs.DACCTL.bit.RAMPSOURCE = 2; //use EPWM3 as sync source EDIS; Comp1Regs.RAMPDECVAL_SHDW = DecVal_1V; It is setup for non-inverted operation with the DAC connected to its inverted input and the ramp generator is set as input for the DAC. The size of the ramp is then set to the defined value of DecVal_1V. Then the soft start feature is set up with start time and the time between updates, by the function CNTRL_2p2zSoftStartConfig( &ctrl1v, 20, ); This is then repeated for the two remaining supplies. And then the supplies are setup to run 120 degrees out of phase /* Setup the PWM modules to be 120deg out of phase */ PWM_setPhase( PWM_MOD_1, 0 ); PWM_setPhase( PWM_MOD_2, 111 ); PWM_setPhase( PWM_MOD_3, 222 ); PWM_setSyncOutSelect( PWM_MOD_1, PWM_SYNCOSEL_ZERO ); PWM_setSyncOutSelect( PWM_MOD_2, PWM_SYNCOSEL_IN ); The supplies are then synced when PWM module 1 reaches zero The PWM outputs are then enabled /* enable outputs on the PWM modules */ PWM_pin(PWM_MOD_1, PWM_CH_A, GPIO_NON_INVERT); PWM_pin(PWM_MOD_2, PWM_CH_A, GPIO_NON_INVERT); PWM_pin(PWM_MOD_3, PWM_CH_A, GPIO_NON_INVERT); And the global interrupts are enabled INT_enableGlobal( true ); Now the supplies are soft started /* the 5.75 V supply is soft started */ while(x < 1500) { GPIO_clr(GPIO_31); CNTRL_2p2zSoftStartUpdate( &ctrl5v ); x++; } x=0; /* the 3.3 V and 1.2 V supplies are soft started */ while(x < 750) { CNTRL_2p2zSoftStartUpdate( &ctrl3v ); CNTRL_2p2zSoftStartUpdate( &ctrl1v ); x++; } 31

33 These update functions are originally intended to be in the ISRs but for this application there simply isn t time for the extra calculations. Therefore the update functions are looped until the supply is up and running. As the time between these updates the input of the SoftStartConfig function is adjusted until it matches the desired start up time. And x is sized so the loop is left when the supply is running. PWM_setDutyA( PWM_MOD_4, PWM_nsToTicks(period_ns)); //Disable the start-up power supply while(1) { } /* toggle the LED forever */ GPIO_set(GPIO_31); SYS_msDelay( 250 ); GPIO_clr(GPIO_31); SYS_msDelay( 250 ); Then the start-up power supply is disabled and an endless loop is entered where a led will be toggled Pole / Zero placement The initial placement of the poles and zero was based on the calculations from the Biricha Digital note [1] where the zero was placed on 20% of the crossover frequency, the pole was placed on top of the ESR zero and the last pole was calculated to set the gain of the system. A Gain/phase measurement was taken and the K-value of the controller was sized so the gain of the measurement fit the simulation. The phase margin of the measurement was lower than the simulation due to the delay in the digital circuit. To match the simulation a delay is multiplied onto the transfer function. This setup gave a stable system but it did only have a phase margin of about 45 and a bandwidth of 8 khz. This is enough for a stable system but not enough to match Thrane & Thrane s design criteria. Since the voltage divider in the voltage feedback is not included in Birichas calculations when adjusting the K-value in this way, the higher K-value will compensate for the attenuation in the voltage divider. This is however not optimal the K-value is therefore lowered and a constant is multiplied onto the transfer function to compensate In order to boost the phase the zero is placed down below the pole caused by the output load. This will however also increase the gain so the pole is moved down until the simulated gain is correct. In cases as in the 3.3V supply where the ESR zero is placed far above the crossover frequency the pole which normally would be on top of the ESR zero, can be moved upwards to further increase the phase margin. This will also change the gain curve so if the ESR zero is not placed high enough it will cost on the gain margin. 32

34 4.2 Test In this section test will be made to verify that the power supply can live up to the requirements stated in the requirements section at page 4 Pictures has been taken of some of the teat setups and can be found in Appendix 11 on page Phase margin / system bandwidth The phase margin of the system is simulated in MATLAB and then measured by the HP4194A Gain-Phase Analyser. The simulation is then adjusted by adding the delay of the digital system and compensation for the altered loop gain due to the K factor of the controller. The design goal is a phase margin greater than 60, gain margin greater than 10 db and the bandwidth should be greater than 10 khz The phase margin of the 5.75 V supply is simulated and measured at a load of 4 A in Figure 26. Figure V - supply phase margin at max. load And at 0.1A load in Figure 27. Figure V - supply phase margin at min. load 33

35 As can be seen from the plots the phase margin is well over 60 which was the design criteria and a bandwidth of 10.6 khz and gain margin of about 12 db are achieved. The phase margin of the 3.3 V supply is then simulated and measured at a load of 1.5 A in Figure 28 and at a load of 100 ma in Figure V supply - phase margin at max. load Figure V supply - phase margin at min. load From the plots can be seen that the phase margin for the 3.3 V supply is at least 63.7, the gain margin is 10.1 db and the bandwidth of the system is 10 khz. The same simulations and measurements have been made for the 1.2 V supply and shown in Figure 30 where the supply is loaded with 1.5A and in where the load is reduced to 100 ma. 34

36 Figure V supply - phase margin at max. load Figure V supply - phase margin at min. load The plots show that although the phase margin is below 60 at low loads it is still very reasonable with a minimum phase response of 59 a gain margin of 10 db and a bandwidth of 11.2 khz. As can be seen does all the supplies match the simulations rather well. And all the supplies match the design goals close enough. 35

37 Start-up voltages To make sure the requirement of the start-up voltage rise times being between 0.2 ms and 50 ms, the supplies are soft started. A measurement of the start-up and power down rise and fall times is shown in Figure 32. Figure 32 Power up/down voltages From the plot can be seen that the rise time for the supplies lies between 12.5 ms and 17.5 ms furthermore it can be seen that the voltage of the 3.3 V and 1.2 V supplies never supersedes the voltage of the 5.75 V supply Ripple voltage The output ripple voltages of the supplies are measured with a limited bandwidth of approximately 25 khz through a 50Ω coax cable in series with a 50Ω resistor and at maximum load. The ripple voltage of the 5.75 V supply should be below 50 mv. From Figure 33 on the left it can be seen that the actual ripple voltage is just 36 mv however it can be seen from Figure 33 on the right that some noise is superimposed onto the output voltage making the total ripple voltage 42.6 mv still well within specifications. This extra noise can due to the resolution of the PWM module. Figure V supply - output ripple voltage A measurement of the ripple voltage of the 1.2V supply can be seen in Figure 34 this supply is specified to have a ripple voltage below 15 mv and measurements show that the ripple voltage itself is 7.7 mv and the total ripple is 11.6 mv. 36

38 Figure V supply - output ripple voltage Last up is the 3.3V supply where its measurement can be seen in Figure 35 the voltage ripple of this supply is specified to 20 mv. Figure V supply - output ripple voltage Unfortunately when loading this supply with more than 1.1 A large transients appear which means that the requirement cannot be kept. These transients are traced all the way back to the microprocessor where it can be seen that when the PWM output goes low a short impulse follows this is seen in Figure V supply - output ripple voltage and PWM signal 37

39 Figure V supply - output ripple voltage and PWM signal Figure 37 is a zoom of Figure 36 with an additional measurement of the switching node between the FETs (yellow). The green trace is the output of the PWM module and the red is the output where the cursers indicate the maximal allowed ripple. It can be seen how the impulse is switched through the FETs with an added delay of the gate drivers dead time. These impulses reappear on all of the supplies but only the 3.3 V supply is affected by it. This can be due to the fact that this supply is designed with a higher LIR factor causing the output filter to be less ripple suppressant. The origin of these impulses is still unknown but since the controlling part of the PWM output in this implementation is the trip zone module which should not be able to toggle more than once every cycle it seems like the problem could be in the silicon of the microprocessor although no such symptom is described in the errata sheet. 38

40 Load step response The load step response is measured in the same way as the output voltage ripple and the load is then pulsed from minimum to maximum. The load step response of the 5.75 V supply is shown in Figure 38 where the output response is the red trace and the current feedback from the electronic load is the purple. Figure V supply load step response The cursers are set to 5.50 V and 6.00 V which is the requirement so there is plenty of headroom. In Figure 39 the load step response of the 3.3 V supply is shown here the cursers are set to 3.15 V and 3.45 V. It can be seen that the response is well within the requirements. Figure V supply load step response 39

41 The step response for the 1.2 V supply is shown in Figure 40 where the cursers are set to 1.14 V and 1.26 V and once again the requirements are kept Efficiency Figure V supply load step response The total efficiency of all three of the supplies is plotted in Figure 41 with a input voltage of 15 V (red) and an input voltage of 48 V (blue) in this efficiency measurement is included the 5V which supplies the microprocessor through a buck converter. In a final layout the microprocessor would be supplied directly from the 3.3 V supply eliminating the need for a 5 V supply. Figure 41 Overall efficiency 40

42 An efficiency of 87% is reached with a 15 V input voltage and of 85% with an input voltage of 48 V In order to see where changes could be made to increase the efficiency infrared pictures are taken to see which components dissipate the most power in form of infrared radiation. Figure 42 IR shot of board and 5.75 V supply In Figure 42 on the left can be seen a picture of the entire PCB where the hottest part is the 5.75 V supply. On the right is a zoom of the 5.75 V supply from which it is clear that the top side FET is the hottest component on the board followed up by the inductor. Considering the surface area of the inductor and the FET these might be equal contributors to the overall power dissipation. To increase the efficiency an alternate top side FET could be found and the inductor could be designed in an RM- 6 core with more room for cupper thereby reducing the series resistance. In Figure 43 pictures of the 3.3 V supply (Left) and 1.2 V supply (right) is shown. In these cases it does not seem to be necessary for any improvements. Figure 43 IR shot of 3.3 V supply and 1.2 V supply 41

43 5. Economical overview One of the points of interest in this project was if it would be of economical advance to implement this power supply in digital instead of the already implemented analog supply. The easiest way to hold these two supplies up to each other is to compare the prizes of the parts that are different from one another. The FETs and output filters of the supplies are more or less the same so what differs are the controllers. The analog controllers use external resistors and capacitors for the compensation circuit but in a digital controller the same amount of external components are used with the op-amps to sense the current. Furthermore the digital controller needs gate drivers, current sense circuits and a start-up circuit which is integrated in the analog ICs. The price difference is summed up in the table below. Analog solution Digital digital pcs. device description unit price total pcs. device description unit price total 1 LM5116 High voltage SMPS controller TMS320F28035 Microcontroller TPS51220 dual low voltage SMPS controller LM5106 high voltage gate driver TPS28225 low voltege gate driver OPA830 operational amplifier start-up circuitry total 2.57 total 8.17 As can be seen from the table the digital solution is the more expensive in this case. This digital solution could be made with a less expensive microprocessor like the TMS320F28032 which is the cheapest available with the features needed. But even with this the digital controller cost will add up to For a detailed calculation of the costs of the start-up circuitry see 42

44 6. Conclusion 6.1 Product assessment A digitally controlled switch mode power supply which should be able to substitute an already implemented analog supply was designed and produced. It can deliver 5.75 V - 4 A, 3.3 V A and 1.2 V 1.5 A and run from an input voltage of 15 V to 48 V. The 5.75 V supply is able to stay within ±250 mv at load step and has an output voltage ripple below 50 mv. The 1.2 V supply is able to stay within ±60 mv at load step and has an output voltage ripple below 15 mv. The 1.2 V supply is able to stay within ±150 mv at load step. This supply can however not keep the requirement of an output ripple voltage of 20 mv this is due to a bug which is believed to originate either in the software or in the silicon of the microprocessor. All of the supplies is running peak current mode and has a phase margin around 60, gain margin around 10 db and loop bandwidth greater than 10 khz. A soft start routine was implemented providing a controlled ramp-up of the voltages. The 5.75 V supply is ramped to operational voltage in less than 50 ms and only then is the 3.3 V and 1.2 V supplies ramped up together in less than 50 ms in this way the 3.3 V and 1.2 V supplies never supersedes the 5.75 V supply with more than 0.6 V. All in all the digital implementation of this would be a good switch for the analog supply if it was not for the cost. In this case an implementation of a digital supply will mean an extra expense of 6 euro however further cost optimization on the digital implementation might be possible. Suggestions for further implementations in this project could be Implement current limiting Rewrite program to run from flash, in this way the processor does not have to be programmed at each power-up Investigate if the delay in the control loop can be reduced to gain more phase margin 6.2 Process assessment During this project I have gained a deeper understanding of some of the theory behind switch mode power supplies that I already knew and I have learned a lot about digital handling of real time control and the programming of the C2000 series microprocessor which was a subject that was totally new to me. Due to the fact that there were so many things I did not know how to solve when I started this project the initial time plan were rather rough. Due to this the time plan might have been quite easy to uphold and has been held with minor exceptions. 43

45 In the end I am pretty satisfied with the outcome of this project however I could easily have used more time for perfecting the product even more. 7. Bibliography [1] A. Shirsaver, Step-by-Step Design Guide for Digital Peak Current Mode Control, Biricha Digital, [2] D. Schelle and J. Castorena, Buck-converter design demystified, Maxim. [3] H. Forghani-zadeh and G. Rincón-mora, Current-sensing Techniques for DC-DC converters, Georgia Institute of Technology. [4] Current Mode Control, Venable industries. [5] S. Choudhury, Designing a TMS320F280x Based Digitally Controlled DC-DC Switching powersupply, Texas Instruments, [6] Hands-On Digital Power Design Workshop Abridged Lecture Notes, Biricha Digital. [7] R. Poley and A. Shirsavar, Digital Peak Current Mode Control with Slope Compensation using the TMS320F2803x, Texas Instruments, [8] J. N. Ross, The Essence of Power Electronics, Prentice Hall Europe, Figure references Figure 5 From Unitrodes application note U-111, practical considerations in current mode power supplies ( Figure 6, Figure 9 From Biricha Digitals application note BAN105, Step-by-step design guide for digital peak current mode control ( Figure 7, Figure 8 From the TMS320F28035 datasheet. Figure 13 From the LM5106 datasheet. 7.2 Included on CD Literature: Papers [1] thru [7] MATLAB files Software files: complete CodeComposer 5 project Relevant datasheets Schematic and PCB documentation PDF copy of this report 44

46 Appendices Appendix 1. Milestone plan Underneath is shown a rather rough time plan for the milestones that needs to be achieved in this project. Preliminary research / problem analysis Deciding on main components Getting familiar with the processor Hardware design Hardware fabrication and test Software programming and implementation Final tests and report writing February Marts April May The milestone plan held up more or less. One of the major deviations from the original plan was that a new revision of the hardware had to be made when it was found that the microprocessor was not able to handle the dead-time itself. An updated plan is shown underneath. 45

47 Appendix 3. TMS320F28035 Functional diagram Form 46

48 Appendix 4. CONTROLcard schematic 47

49 48

50 49

51 Appendix 5. Ferroxcube RM-5i Datasheet 50

52 51

53 Appendix 6. Calculations for the 3.3/1.2 V supply Inductor calculations for the 3.3 V supply. ( ) And for the 1.2 V supply. ( ) ( ) ( ) In order to keep down the production costs the two inductors has been chosen to be 10 µh with a saturation current at 4.4 A. This gives the 3.3 V supply a slightly higher LIR factor at which is still reasonable. Capacitor calculations for the 3.3 V supply. ( ) ( ) ( ) ( ( ) ) For this supply a 150 µf and 30 mω ESR polymer capacitor is chosen. And for the 1.2 V supply. ( ) ( ) ( ) ( ( ) ) For this supply tree electrolytic capacitors on 330 µf and 90 mω ESR, was chosen. 52

54 Appendix 7. Project schematic Schematic overview 53

55 54

56 55

57 56

58 57

59 58

60 Appendix 8. PCB Top side Bottom side 59

61 Appendix 9. Source code #include "csl.h" // Include the Biricha header files //#define SILICON_REV0 /* Uncomment if F28035 rev.0 silicon is used */ Uint16 dummy; Uint16 x = 0; Uint16 phase = 120; /*Define section for the 5.75V supply */ #define DecVal_5V 26 #define K_5V 46 #define REF_5V 3567 #define MIN_DUTY 0 //common for all supplies #define MAX_DUTY_5V #define A1_5V #define A2_5V #define B0_5V #define B1_5V #define B2_5V /*Define section for the 5.75V supply */ /*Define section for the 3.3V supply */ #define DecVal_3V 45 #define K_3V 9 #define REF_3V 3400 #define MAX_DUTY_3V #define A1_3V #define A2_3V #define B0_3V #define B1_3V #define B2_3V /*Define section for the 3.3V supply */ /*Define section for the 1.2V supply */ #define DecVal_1V 4 #define K_1V 9 #define REF_1V 1520 #define MAX_DUTY_1V #define A1_1V #define A2_1V #define B0_1V #define B1_1V #define B2_1V /*Define section for the 1.2V supply */ #define period_ns (5556) //Time period in ns for fs = 180 khz /* Allocate memory for the controllers */ #pragma DATA_ALIGN ( ctrl5v, 64 ); CNTRL_2p2zData ctrl5v; #pragma DATA_ALIGN ( ctrl3v, 64 ); CNTRL_2p2zData ctrl3v; #pragma DATA_ALIGN ( ctrl1v, 64 ); CNTRL_2p2zData ctrl1v; /* Prototypes for the interrupt service routines */ interrupt void IsrAdc5V( void ); interrupt void IsrAdc3V( void ); interrupt void IsrAdc1V( void ); void main ( void ) { SYS_init(); //Initialize the microprocessor ADC_init(); //Initialize the A-D converter // Configure output pins GPIO_config( GPIO_39, GPIO_DIR_OUT, false ); GPIO_config( GPIO_31, GPIO_DIR_OUT, false ); // Configure PWM module 4 to 0% duty and connect it to the output pin PWM_config( PWM_MOD_4, PWM_nsToTicks(period_ns), PWM_COUNT_UP ); PWM_setDutyA( PWM_MOD_4, 0); PWM_pin(PWM_MOD_4, PWM_CH_A, GPIO_NON_INVERT); 60

62 /*initialize the 5.75V supply*/ PWM_config( PWM_MOD_1, PWM_nsToTicks(period_ns), PWM_COUNT_UP ); PWM_setDutyA( PWM_MOD_1, PWM_nsToTicks(period_ns)*0.55 ); PWM_setDutyB( PWM_MOD_1, PWM_nsToTicks(period_ns-2600) ); PWM_setAdcSoc(PWM_MOD_1,PWM_CH_B, PWM_INT_CMPB_UP ); PWM_configBlanking( PWM_MOD_1, PWM_CMP_COMP3, GPIO_NON_INVERT, true ); PWM_setBlankingWindow(PWM_MOD_1, PWM_nsToTicks(420)); PWM_setTripZone( PWM_MOD_1, PWM_DCEVT, PWM_TPZ_CYCLE_BY_CYCLE ); PWM_setTripState( PWM_MOD_1, PWM_CH_A, GPIO_CLR ); PWM_setTripState( PWM_MOD_1, PWM_CH_B, GPIO_NO_ACTION ); // Configure PWM module 1 to count up and set the time period // Set the maximal duty-cycle of PWM channel A // Set the duty-cycle of PWM channel B /* Configure PWM module 1 channel B to trigger the ADC start of conversion at the compare match of channel B */ /* Configure the blinking window of PWM module 1 to be asynchronous with comparator block 3 as input and non-inverted input */ // Set the blanking time to 420 ns /* Sets up the trip zone to trigger on the event caused by the blanking module and make a cycle by cycle trip */ // The trip will clear channel A // And have no effect on channel B /* If rev. 0 silicon is used the ADC will take a sample prior to every conversion and discard it in the ISR */ #ifdef SILICON_REV0 ADC_config( ADC_MOD_1, ADC_SH_WIDTH_7, ADC_CH_B0, ADC_TRIG_EPWM1_SOCB ); #endif ADC_config( ADC_MOD_2, ADC_SH_WIDTH_9, ADC_CH_B0, ADC_TRIG_EPWM1_SOCB ); // Setup ADC module 2 to sample channel B0 on command from PWM module 1 channel B ADC_setCallback( ADC_MOD_2, IsrAdc5V, ADC_INT_1 ); // At the end of conversion the ADC will raise interrupt flag 1 and go to the ISR CNTRL_2p2zInit(&ctrl5V,REF_5V,_IQ26(A1_5V),_IQ26(A2_5V),_IQ26(B0_5V),_IQ26(B1_5V),_IQ26(B2_5V),_IQ23(K_5V),MIN_DUTY,MAX_DUTY_5V ); // This initializes the controller with previous defined constants CMP_config(CMP_MOD_3, CMP_ASYNC, GPIO_NON_INVERT, CMP_DAC ); /* Configure comparator module 3 to be asynchronous with a non inverted output and connect the DAC to the negative input */ Comp3Regs.DACVAL.all = 0; // Set the value of the DAC to 0 EALLOW; Comp3Regs.DACCTL.bit.FREE_SOFT = 0; // Stop the ramp generator immediately when emulation is suspended Comp3Regs.DACCTL.bit.DACSOURCE = 1; // Setup the DAC to be controlled by the ramp generator Comp3Regs.DACCTL.bit.RAMPSOURCE = 0; // 0 = Sync with PWM module 1 EDIS; Comp3Regs.RAMPDECVAL_SHDW = DecVal_5V; // Setup the decrement of the compensation ramp CNTRL_2p2zSoftStartConfig( &ctrl5v, 20, ); // Configure soft start of the supply /*End of the 5.75V supply initialization*/ /*initialize the 3.3V supply*/ PWM_config( PWM_MOD_2, PWM_nsToTicks(period_ns), PWM_COUNT_UP ); PWM_setDutyA( PWM_MOD_2, PWM_nsToTicks(period_ns)*0.80); PWM_setDutyB( PWM_MOD_2, PWM_nsToTicks(period_ns-2600) ); PWM_setAdcSoc(PWM_MOD_2,PWM_CH_B, PWM_INT_CMPB_UP ); PWM_configBlanking( PWM_MOD_2, PWM_CMP_COMP2, GPIO_NON_INVERT, true ); PWM_setBlankingWindow(PWM_MOD_2, PWM_nsToTicks(420)); PWM_setTripZone( PWM_MOD_2, PWM_DCEVT, PWM_TPZ_CYCLE_BY_CYCLE ); PWM_setTripState( PWM_MOD_2, PWM_CH_A, GPIO_CLR ); PWM_setTripState( PWM_MOD_2, PWM_CH_B, GPIO_NO_ACTION ); #ifdef SILICON_REV0 ADC_config( ADC_MOD_3, ADC_SH_WIDTH_7, ADC_CH_B2, ADC_TRIG_EPWM2_SOCB ); #endif ADC_config( ADC_MOD_4, ADC_SH_WIDTH_9, ADC_CH_B2, ADC_TRIG_EPWM2_SOCB ); ADC_setCallback( ADC_MOD_4, IsrAdc3V, ADC_INT_2 ); CNTRL_2p2zInit(&ctrl3V,REF_3V,_IQ26(A1_3V),_IQ26(A2_3V),_IQ26(B0_3V),_IQ26(B1_3V),_IQ26(B2_3V),_IQ23(K_3V),MIN_DUTY,MAX_DUTY_3V ); CMP_config(CMP_MOD_2, CMP_ASYNC, GPIO_NON_INVERT, CMP_DAC ); Comp2Regs.DACVAL.all = 0; EALLOW; Comp2Regs.DACCTL.bit.FREE_SOFT = 0; Comp2Regs.DACCTL.bit.DACSOURCE = 1; Comp2Regs.DACCTL.bit.RAMPSOURCE = 1; EDIS; Comp2Regs.RAMPDECVAL_SHDW = DecVal_3V; CNTRL_2p2zSoftStartConfig( &ctrl3v, 20, ); /*End of the 3.3V supply initialization*/ 61

63 /*initialize the 1.2V supply*/ PWM_config( PWM_MOD_3, PWM_nsToTicks(period_ns), PWM_COUNT_UP ); PWM_setDutyA( PWM_MOD_3, PWM_nsToTicks(period_ns)*0.8); PWM_setDutyB( PWM_MOD_3, PWM_nsToTicks(period_ns-2600) ); PWM_setAdcSoc(PWM_MOD_3,PWM_CH_B, PWM_INT_CMPB_UP ); PWM_configBlanking( PWM_MOD_3, PWM_CMP_COMP1, GPIO_NON_INVERT, true ); PWM_setBlankingWindow(PWM_MOD_3, PWM_nsToTicks(420)); PWM_setTripZone( PWM_MOD_3, PWM_DCEVT, PWM_TPZ_CYCLE_BY_CYCLE ); PWM_setTripState( PWM_MOD_3, PWM_CH_A, GPIO_CLR ); PWM_setTripState( PWM_MOD_3, PWM_CH_B, GPIO_NO_ACTION ); #ifdef SILICON_REV0 ADC_config( ADC_MOD_5, ADC_SH_WIDTH_7, ADC_CH_B4, ADC_TRIG_EPWM3_SOCB ); #endif ADC_config( ADC_MOD_6, ADC_SH_WIDTH_9, ADC_CH_B4, ADC_TRIG_EPWM3_SOCB ); ADC_setCallback( ADC_MOD_6, IsrAdc1V, ADC_INT_3 ); CNTRL_2p2zInit(&ctrl1V,REF_1V,_IQ26(A1_1V),_IQ26(A2_1V),_IQ26(B0_1V),_IQ26(B1_1V),_IQ26(B2_1V),_IQ23(K_1V),MIN_DUTY,MAX_DUTY_1V ); CMP_config(CMP_MOD_1, CMP_ASYNC, GPIO_NON_INVERT, CMP_DAC ); Comp1Regs.DACVAL.all = 0; EALLOW; Comp1Regs.DACCTL.bit.FREE_SOFT = 0; Comp1Regs.DACCTL.bit.DACSOURCE = 1; Comp1Regs.DACCTL.bit.RAMPSOURCE = 2; //use EPWM3 as sync source EDIS; Comp1Regs.RAMPDECVAL_SHDW = DecVal_1V; CNTRL_2p2zSoftStartConfig( &ctrl1v, 20, ); /*End of the 1.2V supply initialization*/ /* Setup the PWM modules to be 120deg out of phase */ PWM_setPhase( PWM_MOD_1, 0 ); PWM_setPhase( PWM_MOD_2, 111 ); PWM_setPhase( PWM_MOD_3, 222 ); PWM_setSyncOutSelect( PWM_MOD_1, PWM_SYNCOSEL_ZERO ); PWM_setSyncOutSelect( PWM_MOD_2, PWM_SYNCOSEL_IN ); //PWM module 1 synchronizes with PWM module 2 when it reaches zero //PWM module 2 synchronizes with PWM module 3 when a sync pulse is received /* enable outputs on the PWM modules */ PWM_pin(PWM_MOD_1, PWM_CH_A, GPIO_NON_INVERT); PWM_pin(PWM_MOD_2, PWM_CH_A, GPIO_NON_INVERT); PWM_pin(PWM_MOD_3, PWM_CH_A, GPIO_NON_INVERT); // PWM_pin(PWM_MOD_1, PWM_CH_B, GPIO_NON_INVERT); // PWM_pin(PWM_MOD_2, PWM_CH_B, GPIO_NON_INVERT); // PWM_pin(PWM_MOD_3, PWM_CH_B, GPIO_NON_INVERT); INT_enableGlobal( true ); GPIO_set(GPIO_31); // Enable global interrupts // LED connected to GPIO_31 /* the 5.75 V supply is soft started */ while(x < 1500) { GPIO_clr(GPIO_31); CNTRL_2p2zSoftStartUpdate( &ctrl5v ); x++; } x=0; /* the 3.3 V and 1.2 V supplies are soft started */ while(x < 750) { CNTRL_2p2zSoftStartUpdate( &ctrl3v ); CNTRL_2p2zSoftStartUpdate( &ctrl1v ); x++; } GPIO_set(GPIO_31); PWM_setDutyA( PWM_MOD_4, PWM_nsToTicks(period_ns)); //Disable the start-up power supply while(1) { } } /* toggle the LED forever */ GPIO_set(GPIO_31); SYS_msDelay( 250 ); GPIO_clr(GPIO_31); SYS_msDelay( 250 ); 62

64 /* ISR for the 5.75 V supply */ interrupt void IsrAdc5V( void ) { // GPIO_set(GPIO_39); ADC_ackInt( ADC_INT_1 ); #ifdef SILICON_REV0 dummy = ADC_getValue(ADC_MOD_1); #endif ctrl5v.fdbk.m_int = ADC_getValue(ADC_MOD_2); CNTRL_2p2z(&ctrl5V); Comp3Regs.RAMPMAXREF_SHDW = ctrl5v.out.m_int; // Clear the interrupt flag // Discard first sample // Read the ADC value // Send it to the controller // Update the max value of the ramp generator // GPIO_clr(GPIO_39); } /* ISR for the 3.3 V supply */ interrupt void IsrAdc3V( void ) { // GPIO_set(GPIO_39); ADC_ackInt( ADC_INT_2 ); #ifdef SILICON_REV0 dummy = ADC_getValue(ADC_MOD_3); #endif ctrl3v.fdbk.m_int = ADC_getValue(ADC_MOD_4); CNTRL_2p2z(&ctrl3V); Comp2Regs.RAMPMAXREF_SHDW = ctrl3v.out.m_int; // GPIO_clr(GPIO_39); } /* ISR for the 1.2 V supply */ interrupt void IsrAdc1V( void ) { // GPIO_set(GPIO_39); ADC_ackInt( ADC_INT_3 ); #ifdef SILICON_REV0 dummy = ADC_getValue(ADC_MOD_5); #endif ctrl1v.fdbk.m_int = ADC_getValue(ADC_MOD_6); CNTRL_2p2z(&ctrl1V); Comp1Regs.RAMPMAXREF_SHDW = ctrl1v.out.m_int; // GPIO_clr(GPIO_39); } 63

65 Appendix 10. Start-up circuitry cost Comment Description Designator Footprint LibRef Quan tity Price in Total 100nF C31, C32, 50V Capacitor X7R 149C5 C34, C35 SM_0603 Cap 4 0,0444 0,1776 SM/C_ uf Capacitor C33, C36 10 Cap 2 0,0527 0,1054 BAT54S Schottky Barrier Double Diode D4, D5 SOT23_ N BAT54S 2 0,008 0,016 BC817 General Purpose Transistor NPN Silicon Q7, Q BC817-16LT1 2 0,0027 0,0054 BC327 Amplifier Transistor PNP Silicon Q8 SOT54_ mads BC ,0417 0,0417 2k2 R39 SM_0603 Res 1 0,001 0, k R40 SM_0603 Res 1 0,001 0,001 15k R41, R46 SM_0603 Res 2 0,001 0, R R42 SM_0603 Res 1 0,001 0,001 8k2 Resistor 1% - 126a2 R43 SM_0603 Res 1 0,001 0,001 12k R44 SM_0603 Res 1 0,001 0,001 1k2 R45 SM_0603 Res 1 0,001 0,001 Test point TP5, TP6 Test point Test point ITS4140N High side switch U8 SOT223-4 ITS4140 N 1 0,34 0,34 LM317T Three-Terminal Adjustable Output Positive Voltage Regulator U9 221A-06 LM317T 1 0,2352 0,2352 LM317LZ Three-Terminal Adjustable Output Positive Voltage Regulator U10 SOT54_ mads LM317LZ 1 0,1882 0,1882 mounting of SMD component 22 0,03 0,66 total 1,

66 Appendix 11. Test setups The test setup for measuring phase margin, load step response and voltage ripple When measuring phase margin the signal from the gain/phase analyser was injected into the voltage feedback path with a transformer made with a current probe with a secondary winding 65

67 Efficiency was calculated by measuring the output voltage and current of the three supplies and voltage and current of both the input voltages 66