SiC MOSFETs: Gate Drive Optimization

Transcription

1 TND6237/D Rev. 0, SEPTEMBER 2017 SiC MOSFETs: Gae Drive Opimizaion Semiconducor Componens Indusries, LLC, 2017 Sepember, 2017 Rev. 0 1 Publicaion Order Number: TND6237/D

2 SiC MOSFETs: Gae Drive Opimizaion ABSTRACT For high volage swiching power applicaions, silicon carbide or SiC MOSFETs bring noable advanages compared o radiional silicon MOSFETs and IGBTs. Swiching high volage power rails in excess of 1,000 V, operaing a hundreds of khz is non rivial and beyond he capabiliies of even he bes superjuncion silicon MOSFETs. IGBTs are commonly used bu are resriced o lower operaing frequencies due o heir ailing curren and slow urn off. As a resul, silicon MOSFETs are preferred for lower volage, high frequency operaion while IGBTs are beer suied for higher volage, high curren, low frequency applicaions. SiC MOSFETs offer he bes combinaion of high volage, high frequency, swiching performance benefis. They are volage conrolled, field effec devices capable of swiching he same high volages of an IGBT a or above he swiching frequencies of much lower volage silicon MOSFETs. SiC MOSFETs have unique gae drive requiremens. In general, hey require a 20 V, V DD gae drive during he on sae o provide lowes on resisance. Compared o heir silicon counerpars, hey exhibi lower ransconducance, higher inernal gae resisance and he gae urn on hreshold can be less han 2 V. As a resul, he gae mus be pulled below ground (ypically 5 V) during he off sae. Undersanding and opimizing he gae drive circuiry has a profound effec on reliabiliy and he overall swiching performance ha can be achieved. This paper highlighs he unique device characerisics associaed wih SiC MOSFETs. Criical design requiremens relaed o opimal gae drive design for maximizing SiC swiching performance will be described. Sysem level consideraions such as sar up, faul proecion and seady sae swiching will also be discussed. INTRODUCTION Silicon carbide (SiC) is par of he wide bandgap (WBG) family of semiconducor maerials used o fabricae discree power semiconducors. As shown in Table 1, convenional silicon (Si) MOSFETs have a bandgap energy of 1.12 ev compared o SiC MOSFETs possessing 3.26 ev. The wider bandgap energy associaed wih SiC and (GaN) Gallium Niride means ha i akes approximaely 3 imes he energy o move elecrons from heir valence band o he conducion band, resuling in a maerial ha behaves more like an insulaor and less like a conducor. This allows WBG semiconducors o wihsand much higher breakdown volages, highlighed by heir breakdown field robusness being 10 imes ha of silicon. A higher breakdown field enables a reducion in device hickness for a given volage raing which ranslaes o lower on resisance and higher curren capabiliy. SiC and GaN each have mobiliy parameers on he same order of magniude as silicon, making boh maerials well suied for high frequency swiching applicaions. However, he parameer mos differeniaing SiC is is hermal conduciviy being more han 3 imes greaer compared o silicon and GaN. Higher hermal conduciviy ranslaes o lower emperaure rise for a given power dissipaion. The guaraneed maximum operaing emperaure for commercially available SiC MOSFETs is 150 C < T J < 200 C. Comparaively, SiC juncion emperaures as high as 600 C are aainable bu mosly limied by bonding and packaging echniques. This makes SiC he superior WBG semiconducor maerial for high volage, high speed, high curren, high emperaure, swiching power applicaions. Table 1. SEMICONDUCTOR MATERIAL PROPERTIES Properies Si 4H SiC GaN Bandgap Energy (ev) Elecron Mobiliy (cm 2 /Vs) Hole Mobiliy (cm 2 /Vs) Breakdown Field (MV/cm) Thermal Conduciviy (W/cm C) Maximum Juncion Temperaure ( C) SiC MOSFETs are commonly available in he range of 650 V<B VDSS <1.7 kv, wih he majoriy focus being 1.2 kv and above. A he lower range of 650 V, radiional silicon MOSFETs and GaN ouperform SiC. However, one reason o consider lower volage SiC MOSFETs migh be o ake advanage of heir superior hermal characerisics. Alhough he dynamic swiching behavior of SiC MOSFETs is quie similar o sandard silicon MOSFETs, here are unique gae drive requiremens dicaed by heir device characerisics ha mus be aken ino consideraion. SIC MOSFET CHARACTERISTICS Transconducance A silicon MOSFET used in a swiching power supply swiches as quickly as possible beween one of wo operaing modes or regions. The cuoff region is defined where he gae source volage, V GS, is less han he gae hreshold volage, V TH and he semiconducor is in a high blocking sae. During cuoff, he drain source resisance, R DS, is high impedance and he drain curren, I D = 0 A. The sauraion region occurs when he MOSFET is fully enhanced, V GS >> V TH, and R DS(on) is a or near he minimum value, I D is maximum and he semiconducor is in a high conducion sae. As highlighed by he red race shown in Figure 1, he ransiion beween he linear (ohmic) 2

3 and sauraion regions is very sharp and disinc, so ha as soon as V GS > V TH, drain curren flows hrough a relaively low R DS. The ransconducance, g m, is he raio of he change in drain curren o he change in gae volage and defines he oupu o inpu gain of he MOSFET, which is he slope of he I V oupu characerisic curve for any given V GS. g m I d (eq. 1) V GS Si MOSFET Figure 1. SiC MOSFET Oupu Characerisics The slope for a silicon MOSFET I V curve is seep in he linear region (large ΔI D ) and nearly fla when operaing in sauraion so i experiences very high gain (high g m ) whenever V GS > V TH. The fac ha I D is fla for a given V GS means ha he silicon MOSFET behaves much like a non ideal curren source when operaing in sauraion. Conversely, i can be seen from he oupu characerisic curves shown in Figure 1, ha a SiC MOSFET does no exhibi a sharp ransiion beween he linear and sauraion operaing modes. In fac here is no defined sauraion region and from his poin of view a SiC MOSFET behaves more like a variable resisance han a non ideal curren source. The I V oupu characerisic of a SiC MOSFET does no exhibi a large ΔI D for a small ΔV GS, herefore, SiC MOSFETs are considered low gain (low g m ) devices. I D g m (V GS V TH ) (eq. 2) The only way o compensae for he low gain and force a large change in I D is o apply a very large V GS, which has a profound impac on R DS. To furher illusrae his poin, consider he wo operaing poins labeled A and B in Figure 1. R DS(A) 8.75 V 20 A 438 mω, (V GS 12 V) (eq. 3) R DS(B) 3.75 V 20 A 188 mω, (V GS 20 V) (eq. 4) A fixed drain curren of I D = 20 A, yields V DS = 8.75 V when V GS = 12 V compared o V DS = 3.75 V when V GS is increased o 20 V. Comparing he resuls of equaions (3) and A 4, shows ha he resisance and herefore, conducion loss is 2.3 imes higher when operaing a V GS = 12 V. As a resul, SiC MOSFETs perform bes when applying a maximum gae source volage beween 18 V < V GS < 20 V and some can even be as high as V GS = 25 V. Operaing a SiC MOSFET a low V GS can resul in hermal sress or possible failure due o high R DS. The exenuaing effec associaed wih he low g m canno be oversaed. I has a direc impac upon several imporan dynamic characerisics ha mus be considered when designing an adequae gae drive circui: specifically, on resisance, gae charge (Miller plaeau) and over curren (DESAT) proecion. On Resisance As a WBG semiconducor, a SiC MOSFET presens a lower associaed on resisance per uni area for a given volage. The on resisance of a MOSFET consiss of he conribuions from several inernal, V GS dependen, resisive elemens. Mos noable are he channel resisance (R CH ), JFET resisance (R J ) and drif region resisance (R DRIFT ). R CH has a negaive emperaure coefficien (NTC) and dominaes R DS a lower V GS. Conversely, R J and R DRIFT have a posiive emperaure coefficien (PTC) and are dominan a higher V GS levels. For V GS > 18 V, he on resisance has a disinc PTC characerisic. However, during lower V GS, he on resisance versus juncion emperaure characerisic appears parabolic as shown in Figure 2. Specifically a V GS = 14 V, where R CH is dominan, R DS appears o have a NTC characerisic where resisance is decreasing wih increasing emperaure. This unique disincion of a SiC MOSFET is direcly aribued o low g m. For a silicon MOSFET, whenever V GS > V TH, R DS always has a PTC. Figure 2. SiC MOSFET On Resisance vs. Juncion Temperaure The PTC aribue is heavily relied upon for curren balancing whenever wo or more MOSFETs are placed in parallel, as would be he case for mos high curren applicaions. During parallel operaion, when one MOSFET experiences a rise in juncion emperaure, he PTC causes 3

4 an increase in R DS, decreasing he curren and forcing he parallel MOSFET o ake on addiional curren unil a naural balance occurs. If wo or more SiC MOSFETs were placed in parallel while operaing wih low V GS (negaive NTC), he resul would be caasrophic. Therefore, parallel operaion beween SiC MOSFETs is only recommended when V GS is sufficien o ensure reliable NTC operaion (ypically V GS > 18 V). Inernal Gae Resisance The inernal gae resisance, R GI, is inversely proporional o die size and for a given breakdown volage, since a SiC MOSFET die is much smaller compared o a silicon MOSFET die, inernal gae resisance ends o be higher. The real benefi of he smaller SiC MOSFET die comes in he form of lower inpu capaciance, C ISS, which ranslaes o lower required gae charge, Q G. Table 2 highlighs several imporan parameer comparisons beween wo differen manufacurers of SiC MOSFETS (SiC_1 and SiC_2) and wo bes in class, 900 V and 650 V super juncion, Si MOSFETs (Si_1 and Si_2). designer more freedom o conrol V DS, dv/d ransiions by adding or reducing exernal gae resisance. Gae Charge When V GS is applied, a cerain amoun of charge is ransferred o change he gae volage beween V GS(MIN) (V EE ) and V GS(MAX) (V DD ) as fas as possible. Since he MOSFET inernal capaciances are non linear, a V GS versus gae charge (Q G ) curve is helpful o idenify how much charge mus be delivered for a given V GS level. A ypical gae charge curve for a SiC MOSFET is shown in Figure 3. Table 2. SEMICONDUCTOR MATERIAL PROPERTIES III. SiC_1 SiC_2 Si_1 SJ FET Si_2 SJ FET B VDSS (V) I D (A) R DS (mω) Q G (nc) Q GD (nc) C ISS (pf) C OSS (pf) V GS (V) 5 o 20 6 o 22 ±20 ±20 V GS(TH) (V) R GI (Ω) R GI xc ISS (ns) From a gae drive viewpoin, i is ineresing o compare he R GI xc ISS ime consans. The Si_2 device has he lowes ime consan of 35 ns bu is also a lower curren, lower volage raed MOSFET. For comparison purposes he 650 V, Si_2 MOSFET is ineresing because he 1200 V, SiC_1 sample has parameers closely mached bu has a significanly lower C ISS a nearly wice he raed B VDSS. In erms of B VDSS, he Si_1 sample is a closer comparison o eiher of he SiC samples. Because of he low Q G associaed wih SiC_1, he ime consans beween Si_1 and SiC_1 are closely mached even hough he inernal gae resisance of SiC_1 is 7 imes higher. Inernal gae resisance limis he gae drive curren ha can be injeced ino he C ISS. A high performance, SiC gae drive circui needs o provide exremely low oupu impedance so ha he driver does no become a limiing facor by adding o he already high R GI. This allows he Figure 3. SiC MOSFET, Gae Source Volage vs. Gae Charge I is ineresing ha he Miller plaeau for a SiC MOSFET occurs a higher V GS and is no fla as would be expeced for a silicon MOSFET. A non fla Miller plaeau implies ha V GS is no consan over he corresponding range of charge, Q G. This is anoher consequence arising from he low gm associaed wih SiC MOSFETs. I is also noable ha Q G = 0 nc does no occur a V GS = 0 V. V GS mus be pulled below ground ( 5 V in his case) o fully discharge he gae of a SiC MOSFET. A second reason o swich he gae negaive during urn off arises from he fac ha he worse case V TH can be as low as low as 1 V. Swiching V GS beween 0V < V GS < V DD, wih V TH ~ 1 V leaves no margin for inadveren urn on due o spurious gae noise or V DS, dv/d induced urn on. As a resul, nearly all SiC MOSFETs require a minimum V GS of 5 V < V GS(MIN) < 2 V bu some manufacurers specify as much as 10 V. DESAT Proecion DESAT proecion is a ype of over curren deecion ha originaed wih circuis used o drive IGBTs. During he on ime, if he IGBT could no longer be held in sauraion ( de sauraion ), he collecor emier volage would begin o rise while he full collecor curren was flowing. Obviously his would have a negaive impac on efficiency or in he wors case, could lead o failure of he IGBT. Possible reasons for his migh include: insufficien base curren due o bea olerance or emperaure effecs or shor 4

5 circui or overload operaion. The purpose of he so called DESAT funcion is o monior he collecor emier volage of he IGBT and deec whenever such a poenially desrucive condiion is presen. Alhough he faul mechanism is slighly differen, a SiC MOSFET can suffer a similar fae where V DS can rise while maximum I D is flowing. This undesirable condiion can arise if he maximum V GS during urn on is oo low or he gae drive urn on edge is oo slow or a shor circui or overload condiion exiss. The R DS can increase while he full I D is presen, causing an unexpeced bu slow rise in V DS. Because a SiC MOSFET does no operae in a clearly defined sauraion region, i never appears as consan curren source. This can be problemaic, as mos over curren proecion schemes depend on a MOSFET emulaing a non ideal, consan curren source during an over curren condiion. When a SiC MOSFET undergoes a de sauraion even, V DS responds very slowly, while he maximum drain curren coninues flowing hrough an increasing on resisance. As a resul, i can be possible ha he drain curren could reach a level imes he maximum raed pulse curren (during high R DS ), before he drain source volage can respond. For a high frequency power converer, numerous swiching cycles can occur before a de sauraion faul is recognized. DESAT is herefore an imporan and necessary proecion funcion ha should be assigned as par of he gae drive circuiry, in addiion o any over curren proecion ha migh also be par of he power supply conrol. V DD C DD R HI R GATE V EE G C GD R GI C GS Figure 4. SiC MOSFET Source Curren V DD ( 20 V) V GS V GS(MP) ( 8 V) V TH ( V) V EE ( 3 V) I G V DS D S I D C DS SIC MOSFET DYNAMIC SWITCHING Turn On The swiching profile for a SiC MOSFET is very similar o a Si MOSFET excep for he main difference being he 20 V gae drive ampliude during urn on and he fac ha he gae mus be pulled below ground during urn off. The urn on ransiion requires a large, peak, source curren capable of charging he SiC inernal gae capaciance as quickly as possible o minimize swiching loss. As an esimae, he enire urn on even should occur wihin Δ < 10 ns, for a full V GS swing of ΔV GS = 30 V and an esimaed C ISS = C GS + C GD = 1000 pf which yields a required peak curren, I G(SRC) =3 A according o equaion (5): (C GS C GD) V GS I G(SRC) (eq. 5) The urn on ransiion for a SiC MOSFET is defined by four disinc iming inervals, as shown in Figure 5. The iming inervals shown in Figure 5 and Figure 7 are represenaive of wha would be expeced from an ideal clamped inducive swiching applicaion, ypical of he operaing mode used in swiching power supplies. I D Figure 5. SiC MOSFET Turn On Sequence 0 1 : V GS ramps from V EE o V TH as he gae drive circui mus deliver a large peak of insananeous gae curren, I G(SRC), supplied primarily from he charge sored in he gae driver bulk capacior, C VDD. This ime inerval is ofen referred o as urn on delay since I D and V DS are unaffeced while V GS is below V TH. Mos of he gae curren is used o charge C GS and C GD. Noice from he schemaic diagram shown in Figure 4, he sourcing curren flows hrough hree resisors, R HI, R GATE and R GI. R HI is he equivalen inernal resisance of he driver source, R GATE is he resisance of he race impedance plus any addiional 5

6 added dampening resisance and R GI is he SiC MOSFET inernal gae resisance. R HI and R GATE are on he order of a few Ω s bu for a SiC MOSFET R GI can be on he order of 10 s of Ω s which is an order of magniude higher compared o a high volage, Si MOSFET. Since hese hree resisors form an RC ime consan wih he SiC inernal gae capaciance, sourcing adequae peak gae curren is necessary o assure a fas rising edge of he gae drive signal. 1 2 : As V GS coninues o ramp from V TH o he Miller plaeau, I D begins o increase hrough R J + R DRIFT since he R DS channel resisance is no fully enhanced a low V GS. V DS remains a is maximum level because he SiC inrinsic body diode is no ye in he blocking sae due o he low value of I D and he high resisive sae of R DS. I is advised no o operae a SiC MOSFET wih V GS < 13 V because of he risk of hermal runaway due o he high R DS a low V GS. Therefore, i is criical ha he gae drive circui be able o ransiion from V TH o V GS > 13 V as fas as possible. The ime spen for V TH < V GS < 13 V should be less han a few ns o minimize I D 2 xr DS dynamic power loss. 2 3 : V GS is a he Miller plaeau which happens around 8 V for a SiC MOSFET. During his ime he full load curren is flowing hrough R DS and he inrinsic body diode no longer in is blocking sae, allowing he drain volage o fall. The channel resisance coninues decreasing bu R DS is sill dominaed by R CH. Alhough he full load curren is flowing hrough he MOSFET drain, R DS remains quie high a his low V GS. Therefore, i is imperaive ha V GS ransiion hrough his region as quickly as possible. Since he speed of his ransiion is driven by I G, he peak drive curren capabiliy during he Miller plaeau (~ 1/2 V DD ) region should be more ineresing han he peak raing shown on any gae driver IC daa shees. 3 4 : A V GS(MP) jus near he end of he Miller plaeau, V DS falls o I D xr DS above zero. As V GS ransiions from ~8 V < V GS < 20 V, he channel resisance, R CH, coninues o decrease and now R J + R DRIFT are dominan over R CH, resuling in a proporional decrease in V DS. Mos SiC MOSFETs become fully enhanced when V GS > 16 V bu he lowes R DS value is ulimaely deermined by he final maximum value of V GS. The remaining gae curren, I G, is spli o fully charge C GD and C GS. V DD C DD R LO R GATE G C GD R GI C GS S V Figure 6. SiC MOSFET Sink Curren V DD ( 20 V) V GS V GS(MP) ( 8 V) V TH ( V) V EE ( 3 V) I G V DS I D Figure 7. SiC MOSFET Turn Off Sequence D I D C DS Turn Off The urn off procedure for a SiC MOSFET is essenially he reverse of he urn on sequence described previously. The role of he gae drive circui is o sink a large amoun of peak curren, capable of discharging he C GD and C GS capaciance of he SiC MOSFET as quickly as possible. In addiion, he gae driver impedance during urn off mus be as low as possible o hold he MOSFET gae low. This can be especially problemaic due o he low V TH associaed wih SiC MOSFETs. No only does his necessiae he SiC gae being pulled below ground bu he sink curren capabiliy of he gae driver mus also be significanly higher compared o he raed source curren. The flow of gae drive curren, I G(SINK), is highlighed in Figure : V GS ramps down from V DD o he Miller plaeau, V GS(MP). The sink curren, I G(SINK), is primarily supplied from he charge sored in C GD and C GS while he gae driver bulk capacior, C VDD, is recharged by V DD. The drain curren, I D, remains unchanged. As V GS is decreasing, he channel resisance is increasing causing a sligh increase in V DS by I D xr DS vols. The marginal increase in V DS would be hardly noiceable excep possibly near he end of he 0 1 ime inerval. 1 2: During his ime inerval, he provision of gae curren is dominaed by C GD since he C GS capacior sees a nearly consan V GS. Across he Miller plaeau, V DS increases from IDxRDS o he VDS rail volage where i is 6

7 clamped by he SiC inrinsic body diode. The drain curren, I D, remains unchanged from he previous inerval. Since RDS is increasing due o V GS <1 3 V and VDSxID simulaneously appear across he MOSFET, he gae drive circui should be raed o sink a significan amoun of curren during his ime inerval. During urn off, his is he porion of he gae drive curren ha is mos ineresing o designers since i is imperaive o ransiion hrough he Miller plaeau region as quickly as possible. 2 3 : As V GS coninues o decrease from he Miller plaeau oward V TH, I D is ramping down o near zero during his inerval. V DS is now fully clamped o he drain volage rail by he SiC inrinsic body diode which means he C GD capacior is fully charged. As a resul, mos of he sink curren is now flowing hrough C GS. 3 4 : I D and V DS remain unchanged. During he final urn off inerval, he SiC inernal inpu capaciors are no fully discharged unil V GS falls below 0 V. Since V TH is only ~1 V and o fully discharge C ISS, V GS mus complee he urn off sequence a a negaive volage. The imporance of he gae drive circui o provide as low impedance as possible canno be oversaed. This is especially rue for high volage, half bridge power opologies where he midpoin is pulled up by a high dv/d when he high side MOSFET conducs. A low impedance pull down is essenial for prevening inadveren, dv/d induced urn on. In summary, he urn on and urn off swiching saes for a SiC MOSFET involve four disinc ime inervals. The dynamic swiching waveforms shown in Figure 5 and Figure 7 are represenaive of ideal operaing condiions. In realiy, package parasiics such as lead and bond wire inducance, parasiic capaciances and PCB layou can have a profound effec on measured waveforms. Proper componen selecion, bes PCB layou pracices and an emphasis on providing a well designed gae drive circui are each essenial for opimizing performance of SiC MOSFETs used in swiching power applicaions. DISCRETE SIC GATE DRIVE Compensaing for he low gain while achieving efficien, high speed swiching imposes he following criical requiremens for a SiC gae drive circui: 1. A SiC MOSFET specifies an asymmerical max/min V GS near he range of +25 V/ 10 V. The gae drive circui mus be capable of providing nearly he full range of 35 V, V GS swing o ake full advanage of he SiC performance benefis. Mos SiC MOSFETs will perform bes when driven beween 5 V > V GS > 20 V. To cover he wides range of available SiC MOSFETs, he gae drive circui should be able o wihsand V DD = 25 V and V EE = 10 V 2. V GS mus have fas rise and fall edges, on he order of a few ns 3. Mus be able o source high peak gae curren on he order of several amps, across he enire Miller plaeau region 4. Sink curren capabiliy is driven by he need o provide a very low impedance hold down or clamp as he V GS falls below he Miller plaeau. The sink curren raing should exceed wha would be required by merely having o discharge he inpu capaciance of a SiC MOSFET. A minimum, peak sink curren raing on he order of 10 A should be considered appropriae o cover high performance, half bridge power opologies 5. Mus have V DD under volage lockou (UVLO) level ha is mached o he requiremen ha V GS > ~16 V before swiching begins 6. Mus have V EE UVLO monioring capabiliy o assure he negaive volage rail is wihin an accepable range 7. Mus have a de sauraion funcion capable of deecion, faul reporing and proecion for long erm reliable operaion of he SiC MOSFET 8. Low parasiic inducance for high speed swiching 9. Small driver package able o be locaed as close as possible o he SiC MOSFET Wihou excepion, he requiremens for driving a SiC MOSFET efficienly and reliably call for a very specific ype of gae driver. However, mos reference designs currenly shown in he indusry are designed based on using general purpose low side gae drivers. One such example is shown in Figure 8. 7

8 Figure 8. Sandard Low Side Driver, SiC Discree Gae Drive Design Example The circui shown is floaing wih respec o ground so i can be used as eiher a low side or high side referenced gae drive. For eiher case, in he even of a power sage failure, isolaion is desired o proec he conrol circuiry from he high volage seen a he power sage. Two isolaed dc dc converers, PS1 providing V DD = 24 V (pos regulaed o 20 V) and PS2 configured o regulae a V EE = 5 V, are used o provide he V DD and V EE volage rails. I should also be menioned ha hese converers are dedicaed o driving a single SiC load and so wo would be needed for each SiC load. This is especially rue for high side gae drive applicaions such as he upper swich in a half bridge, full bridge or moor drive applicaion. The volage seen by he main driver, U 1, is floaing by several hundred vols and is very suscepible o he high dv/d associaed wih a swiching SiC MOSFET. Assuming a dv/d=100 V/ns, wih jus 1 pf of sray parasiic capaciance across he isolaion barrier of he PS1 (or PS2) ransformer resuls in 100 ma of peak curren. 100 ma per pf emphasizes he need for low parasiic capaciance, low sray inducance and igh coupling beween he V EE (and V DD ) volage rails and he gae driver IC. The digial isolaor, U 2, isolaes he gae drive signal from he power sage and also provides he necessary level shifing. The secondary side of U 2 is hen used as he inpu o main driver, U 1. U 1 is a generic, low side gae driver bu mus be raed o handle he full V GS volage swing of 25 V ( 5 V < V GS < 20 V) and provides he desired source/sink curren levels. Since mos general purpose, low side gae drivers are raed for a maximum V DD = 20 V, may no provide adequae source/sink curren and may no be available in low inducance packages, selecion can be limied o only a few specific choices. These ypes of gae drivers are inended o drive silicon MOSFETs and from his poin of view, hey lack several imporan requiremens needed for SiC MOSFETs. For example, here is no over curren faul reporing or DESAT monioring funcion available from hese gae drivers. Also, he UVLO hresholds of generic gae drivers are ypically defined based on 5 V < V DD < 12 V. This could be problemaic since he safe V DD operaing level for a SiC MOSFET is approximaely V DD > ~16 V a sarup. And here is no UVLO monioring available for he V EE volage rail as shown in he reference design of Figure 8. Sandard Low Side Driver, SiC Discree Gae Drive Design Example. These volage rails would need o be moniored elsewhere o assure ha levels are accepable for driving he SiC MOSFET ino a low resisive sae during urn on and holding he gae below ground during urn off. Alhough he soluion shown in Figure 8 provides he necessary funcions for driving a SiC MOSFET, i is incomplee, a leas according o he gae drive requiremens saed a he beginning of secion Discree SIC Gae Drive. Noneheless, wihou a dedicaed SiC driver, mos SiC gae drive circuis are presenly designed his way. Any addiional funcions such as DESAT, volage rail monioring, sequencing, ec are eiher handled by addiional dedicaed circuis or ignored all ogeher. 8

9 NCP51705 SIC GATE DRIVER The NCP51705 is a SiC gae driver ha includes a high level of flexibiliy and inegraion making i fully compaible wih any SiC MOSFET in he marke. The NCP51705 op level block diagram, shown in Figure 9, includes many basic funcions common o wha migh be expeced from any general purpose gae driver, including: 1. V DD posiive supply volage up o 28 V 2. High peak oupu curren of 6 A source and 10 A sink 3. Inernal 5 V reference made accessible for biasing 5 V, low power loads up o 20 ma (digial isolaor, opo coupler, μc, ec) 4. Separae signal and power ground connecions 5. Separae source and sink oupu pins 6. Inernal hermal shudown proecion 7. Separae non invering and invering TTL, PWM inpus V5V UVSET 24 IN+ IN- XEN μa SGND 4 5V_OK VDD_OK VEE_OK 5 VEESET 5V REG 6 VCH UVLO PROTECTION LOGIC CHARGE PUMP REG CPCLK 7 C+ TSD CHARGE PUMP POWER STAGE VDD 18 OUTSRC 17 OUTSRC 14 OUTSNK 13 OUTSNK 15 PGND Figure 9. NCP51705 SiC Gae Driver Block Diagram RUN INPUT LOGIC 8 C- VEE VEE NCP51705 DESAT / CURRENT DRIVER LOGIC & LEVEL SHIFT PGND PGND 21 SVDD 22 DESAT /CS 20 VDD PGND In addiion, he NCP51705 is differeniaed by several unique feaures (lised a he beginning of secion Discree SIC Gae Drive) necessary for designing a reliable SiC MOSFET gae drive circui using minimal exernal componens. The advanages of he NCP51705 disinguishing feaures are deailed in he following secion. Over Curren Proecion DESAT The implemenaion of he NCP51705 DESAT funcion can be realized using only wo exernal componens. As shown in Figure 10, he drain source volage of he SiC MOSFET, Q 1 is moniored via he DESAT pin hrough R 1 and D 1. NCP51705 DESAT Funcion Q S Q R IN 3.3 V DESAT_FLT RUN_OK VDD UVLO VEE UVLO V5V_OK 200 μα 1.25 V VDD 100 k 20 k Remove (Opion) SiC Drive DESAT ns Timer Figure 10. NCP51705 DESAT Funcion 5 OUTSRC OUTSNK During he ime ha Q 1 is off several hundred vols can appear across he drain source erminals. Once Q 1 is urned on, he drain source volage rapidly falls and his ransiion from high volage o near zero volage is expeced o happen in less han a few hundred nano seconds. During he urn on ransiion, he leading edge of he DESAT signal is blanked by a 500 ns imer, consising of a 5 Ω, low impedance pull down resisance. This allows sufficien ime for V DS o fall while a he same ime ensuring DESAT is no inadverenly acivaed. Afer 500 ns, he DESAT pin is released and he 200 μa curren source provides a consan curren hrough R 1, D 1 and he SiC MOSFET on resisance. During he on ime, if he DESAT pin rises above 7.5 V, he DESAT comparaor oupu goes HIGH which riggers he clock inpu of an RS lach. Such a faul will auomaically erminae he railing edge of he Q_NOT oupu on a cycle by cycle basis. The gae drive o he SiC MOSFET is hereby effecively reduced by an amoun of ime proporional o he de sauraion faul ime. The 200 μa curren source is sufficien o ensure a predicable forward volage drop across D 1 while also allowing he volage drop across R 1 o be independen of V DS during he on ime of he SiC MOSFET. If desired, DESAT proecion can be disabled by connecing he DESAT pin o ground. Conversely, if he DESAT pin is lef floaing, or R 1 fails open, he 200 μa curren source flowing hrough he 20 kω resisor, pus a consan 4 V on he non invering inpu of he DESAT comparaor. This condiion essenially disables he gae drive o he SiC MOSFET. Some applicaions may prefer o sense he drain R1 D1 I Q1 VDS 9

10 curren using a curren sense ransformer and drive he DESAT pin exernally. In his case he NCP51705 includes an IC meal opion o remove he 20 kω resisor, allowing he DESAT pin o be used as a radiional pulse by pulse, over curren proecion funcion. The volage on he DESAT pin, V DESAT, is deermined by equaion (6) as: V DESAT (200 μa R 1) V D1 (I D R DS ) (eq. 6) C CH 5 6 VEESET VDD LDO V CH P 9 V NCP51705 VEE Charge Pump G LDO P ID Afer assigning he maximum value for I D (plus allowing any addiional design margin) R 1 and I D are seleced such ha V DESAT < 7.5 V. Rearranging equaion (6) and solving for R 1 gives: V DESAT V D (I D1 R DS) R 1 (eq. 7) 200 μa N C C 7 8 C F N V EE C VEE SiC Drive (SINK) OUTSNK Q 1 V DS In addiion o seing he maximum allowable V DESAT volage, R 1 also serves he dual purpose of limiing he insananeous curren hrough he juncion capaciance of D 1. Because he drain volage on he SiC MOSFET sees exremely high dv/d, he curren hrough he p n juncion capaciance of D 1 can become very high if R 1 is no sized appropriaely. Therefore, selecing a fas, high volage diode wih lowes juncion capaciance should be a prioriy. Typical values for R 1 will be near he range of 5 kω < R 1 < 10 kω bu his can vary according o he I D and R DS parameers of he seleced SiC MOSFET. If R 1 is much smaller han 5 kω, he insananeous curren ino he DESAT pin can be hundreds of milliamps. Conversely, if R 1 is much larger han 10 kω, a RC delay ensues as a produc of R 1 and he juncion capaciance of D 1. The delay can be on he order of 100 μs, resuling in an addiional delay ime responding o a DESAT faul. Charge Pump V EE (VEESET) The NCP51705 operaes from a single, posiive supply volage. Operaing from a single V DD supply volage implies he negaive V EE volage mus be generaed from he gae driver IC. The use of a swiched capacior charge pump is a naural choice for producing he required negaive V EE volage rail. There are many differen opions for archiecing a charge pump. The main challenges are mainaining accurae volage regulaion during ransien condiions, swiching a a frequency o decrease he size of capaciors and minimize exernal componen coun, hereby reducing cos and increasing reliabiliy. As can be seen from he charge pump funcional block diagram shown in Figure 11, only hree exernal capaciors are required o esablish he negaive V EE volage rail. The charge pump power sage essenially consiss of wo PMOS and wo NMOS swiches arranged in a bridge configuraion. Figure 11. NCP51705 V EE Charge Pump An exernal flying capacior, C F, is conneced beween he midpoins of each leg of he bridge as shown. The swich iming is such ha whenever he wo upper PMOS devices are conducing simulaneously, V DD appears across C F. Similarly whenever, he wo lower NMOS devices are conducing simulaneously, V EE appears across C F. The swiching frequency is inernally se a 390 khz, wih he wo upper PMOS devices swiching asynchronous wih respec o he wo lower NMOS devices. A 290 khz, IC meal opion is also available for applicaions desiring a lower charge pump swiching frequency. V EE is regulaed o he volage se a V CH which is deermined by he inernal low dropou regulaor (LDO) volage, programmable by VEESET. The volage presen a VEESET varies he gain (G LDO ) seen by he inernal LDO. If VEESET is lef floaing (a 100 pf bypass capacior from VEESET o SGND is recommended), hen V EE is se o regulae a 3 V. For a 5 V V EE volage, he VEESET pin should be conneced direcly o V5V (pin 23). If VEESET is conneced o any volage beween 9 V and V DD, hen V EE is clamped and se o regulae a he minimum charge pump volage of 8 V. The charge pump sars when V DD > 7.5 V and he V EE volage rail includes an inernally fixed UVLO se o 80% of he programmed V EE value. Since V DD and V EE are each moniored by independen UVLO circuis, he NCP51705 is smar enough o realize when boh volage rails are wihin limis deemed safe for a given SiC MOSFET load. Alernaively, 0 V < OUT < V DD swiching can be achieved by disabling he charge pump enirely. When VEESET is conneced o SGND he charge pump is 10

11 disabled. Wih he charge pump disabled and V EE ied direcly o PGND, he oupu swiches beween 0 V < OUT < V DD. I is imporan o noe ha whenever VEESET is ied o SGND, V EE mus be ied o PGND. During his mode of operaion he inernal V EE UVLO funcion is also disabled accordingly. Anoher possible configuraion is o disable he charge pump bu allow he use of an exernal negaive V EE volage rail. This opion permis V EE < OUT < V DD swiching wih a sligh savings in IC power dissipaion, since he charge pump is no swiching. Wih VEESET conneced o SGND, an exernal negaive volage rail can be conneced direcly beween V EE and PGND. A word of cauion, since VEESET is 0 V, he inernal V EE UVLO is disabled and herefore he NCP51705 is unaware if he V EE volage level is wihin he expeced range. This simple VEESET adjusmen enables he highes degree of flexibiliy using he fewes exernal componens while meeing he broades range of SiC MOSFET volage requiremens. For convenience, he configurabiliy of VEESET is summarized in Table 3. Table 3. SEMICONDUCTOR MATERIAL PROPERTIES VEESET COMMENT V EE (UVLO) V EE V DD 9 V < VEESET < V DD 8 V 6.4 V V5V 5 V 4 V OPEN Add C VEE 100 pf from VEESET o SGND 3 V 2.4 V GND GND Remove C VEE and connec V EE o PGND Connec V EE o exernal negaive volage supply 0 V NA V EXT Programmable Under Volage Lockou UVSET UVLO for a gae driver IC is imporan for proecing he MOSFET by disabling he oupu unil V DD is above a known hreshold. This no only proecs he load bu verifies o he conroller ha he applied V DD volage is above he urn on hreshold. Because of he low g m value associaed wih SiC MOSFETs, he opimal UVLO urn on hreshold is no a one size fis all. Allowing he driver oupu o swich a low V DD can be derimenal for one SiC MOSFET bu may be accepable for anoher depending on hea sinking, cooling and V DD sar up ime. The opimal UVLO urn on hreshold can also vary depending on how he V DD volage rail is derived. Some power sysems may have a dedicaed, housekeeping, bias supply while ohers migh rely on a V DD boosrapping echnique similar o Figure 13. The NCP51705 addresses his need hrough a programmable UVLO urn on hreshold ha can be se wih a single resisor beween UVSET and SGND. As shown in Figure 12, he UVSET pin is inernally driven by a 25 μa curren source wih a series gain of 6. NA The UVSET resisor, R UVSET, is chosen according o a desired UVLO urn on volage, V ON, as defined in equaion (8). NCP51705 UVSET Funcion UVLO V ON R UVSET 6 25 μa 25 μα V5V G UVSET =6 UVSET (eq. 8) Figure 12. NCP51705 UVSET Programmable UVLO 24 RUVSET The value for V ON is ypically deermined from he SiC MOSFET oupu characerisic curves, such as hose highlighed in Figure 1. Because he on resisance of a SiC MOSFET dramaically increases even for a sligh decrease in V GS, he allowable UVLO hyseresis mus be small. For his reason, he NCP51705 has a fixed 1 V hyseresis so ha he urn off volage, V OFF, is always 1 V less han he se V ON. For power supplies ha include a dedicaed housekeeping bias supply, V DD is assumed o be above he desired V ON hreshold before he power sysem iniiaes sof sar or resar due o a faul recovery. For such sysems, having a 1 V UVLO hyseresis is desirable and should no have any impac due o sar up consideraions. However, some power sysems sar from a high volage and hen rely on V DD from a boosrap winding as shown in Figure 13. HV PWM 17 V ON 9 V OFF V CC /V DD HV V CC V DD C NCP51705 V ON <V ON(PWM) V OFF =V ON 1 V Q 1 Figure 13. PWM Boosrap Sar Up Example 11

12 A PWM conroller wih high volage (HV) sar up capabiliy and fixed UVLO hresholds of V ON = 17 V and V OFF = 9 V is shown. As HV is applied, he inernal pass swich opens when HV = V ON = 17 V and he PWM conroller draws sar up curren from C VCC. During his ime, C VCC is discharging and Q 1 mus begin swiching o build up volage in he ransformer boosrap winding. This imposes a resricion on he allowable V ON ha can be programmed from R UVSET. UVSET mus be se o a value less han he UVLO V ON of he PWM conroller. These sar up deails are furher illusraed in Figure 14 where he PWM volage hresholds are shown in blue and he NCP51705 in red. V V ON/16 V OFF 12 VON /11 VOFF 1 V PWM(ON) V BOOT(MIN) Figure 14. Boosrap Sar Up Timing 2 V PWM(MAX) V SIC(MAX) V BOOT(REG) VPWM(OFF) For he purpose of swiching he SiC MOSFET wih he highes possible V GS, i is desired o se V ON as close o he UVLO urn on of he PWM conroller as possible. The rade off in doing so means ΔV = 1 V during Δ ( 2 1 ). The discharge of C VCC is very shallow so a large capacior value is required. For example, assuming he sar up curren o be 1 ma, Δ = 3 ms and ΔV = 1 V, a 3 μf capacior for C VCC is required. Conversely, if V ON is se o 1 V above he minimum boosrap discharge volage, V BOOT(MIN), C VCC is allowed o discharge over a wider ΔV (17 V 11 V) and a much smaller capacior value can be used. Given he same 1 ma, Δ = 3 ms and allowing ΔV = 6 V, he required C VCC capacior value is reduced o 500 nf; a reducion by a facor of 6. However, he incurred penaly can be quie severe as he SiC MOSFET will be swiching wih V GS = 11 V. Clearly, having he NCP51705 biased prior o sar up is he preferred approach. Digial Synchronizaion and Faul Reporing XEN The XEN signal is a 5 V digial represenaion of he inverse of V GS. For he purpose of reporing driver saus, i is considered more accurae ha he PWM inpu since i is derived from he SiC gae volage, propagaion delays are grealy decreased. The inen of his signal is ha i can be used in half bridge power opologies as a faul flag and synchronizaion signal as he basis for implemening cross conducion (overlap) proecion. Whenever XEN is HIGH, V GS is LOW and he SiC MOSFET is OFF. Therefore if XEN and he PWM inpu signal are boh HIGH, a faul condiion is deeced and can be digially assigned o ake whaever precauions migh be desired. Packaging WBG semiconducors have enabled high volage converers o operae much closer o low volage (less han 100 V) swiching frequencies. For low volage converers, he evoluion of semiconducor packaging played a key role oward he modern achievemen of swiching performance seen oday. Dual sided cooling, clip bonding, hermally enhanced power packages and lower inducance, leadless packages are a few examples of silicon MOSFET packaging advancemens. Similarly, he size of gae driver IC packages has undergone a remendous size reducion. Shorer die o lead, bond wire connecions combined wih molded leadless packages (MLP) have been essenial for minimizing parasiic inducance from he driver side. The co packaging of he driver and MOSFET (DrMOS) is he laes sep oward reducing parasiic inducance, raising efficiency and reducing board area. Advancemens such as DrMOS are achievable because of he comparable low volages involved. In he high volage converer realm, minimum spacing requiremens such as creepage and clearance have lef high performance SiC MOSFETs suck in low performance TO 220 and TO 247 ype packages. These packages are well esablished and have long been an indusry sandard. They are well suied for indusrial applicaions, robus and easy o hea sink bu have higher parasiic inducance due o heir long leads and inernal bond wires. SiC MOSFETs have now subjeced hese parasiic inducances o hermal sresses, frequencies and dv/d raes never before envisioned wih high volage, silicon ransisors. Suffice o say, SiC is providing he simulus for rehinking high volage discree packaging. Alhough no he case wih discree componens, a SiC gae driver is able o ake full advanage of he same 12

13 packaging advancemens used wih drivers inended for low volage converers. The NCP5170 die is packaged ino a 24 pin, 4 4 mm, hermally enhanced MLP as shown in Figure 15. IN+ XEN SGND 4 VEESET 5 VCH 6 UVSET V5V DESAT / CS NCP51705 (Top View) Figure 15. NCP pin, 4 4 mm, MLP Packaging and Pin Ou 24 7 C C 22 9 PGND SVDD VDD PGND VEE VEE VDD 18 OUTSRC 17 OUTSRC 16 PGND 15 PGND 14 OUTSNK 13 OUTSNK All he high curren, power pins are doubled and locaed on he righ half of he IC. In addiion o doubling he pins, each doubled pin connecs o he die hrough inernal double bond wires for achieving he lowes possible inducance. All low power, digial signals are single pins only and are locaed on he lef half of he IC, providing a convenien, direc inerface o he PWM or digial conroller. The boom of he NCP51705 package consiss of an elecrically isolaed, hermally conducive, exposed pad. This pad is no conneced o PGND or SGND bu is inended o be conneced hrough hermal vias o an isolaed copper PCB land for hea sinking. If hermal dissipaion becomes a concern, specific aenion should be paid o four dominan power dissipaion conribuors: 1. OUTSRC and OUTSNK losses associaed wih driving he exernal SiC MOSFET. These are gae charge relaed losses proporional o swiching frequency. Reducing swiching frequency will decrease power dissipaion 2. LDO beween V DD and V5V, capable of sourcing up o 20 ma. Do no load he V5V any more han biasing a digial isolaor or opocoupler 3. LDO beween V DD and VCH which is par of he inernal charge pump 4. Inernal charge pump power swiches which can be disabled and replaced wih an exernal negaive bias, as menioned in secion Charge Pump VEE (VEESET) applied (non swiching), V DD(UVLO) = 12 V and no load on he V5V regulaor. For 7 V < V DD < 22 V, I DD was measured o be 0.6 ma < I DD < 2.3 ma. The fla line across he middle is a ~1 ma increase in I DD curren when V DD crosses he UVLO hreshold. The red race represen he case where a 100 khz, 50% pulsed inpu was applied o IN+ while he inernal charge pump is disabled. A 4.99 Ω nf load was used which is he equivalen inpu for a ypical SiC MOSFET. The exernal source and sink resisance was 3Ω.. For 12 V < V DD < 22 V, I DD was measured o be 3.7 ma < I DD < 5.5 ma. VDD(V) NCP51705, V DD vs I DD I_V5V = 0 ma, OUT_Load = 3 Ω Ω nf Non Swiching 0 V<OUT<VDD, 100 khz, 50% I DD(mA) Figure 16. V DD versus I DD, Non Swiching versus Swiching The sar up waveform shown in Figure 17 shows IN + appearing prior o V DD. V DD is rising from 0 V o 20 V, wih UVSET = 2 V (no shown) which equaes o V DD(UVLO) = 12 V. V EE is se o regulae a 5 V wih VEESET = V5V (no shown) which equaes o V EE(UVLO) = 4 V. The oupu is enabled when VEE = 4 V, even hough V DD > 12 V (V DD = 15 V). Noice also ha OUT (V GS ) is less han 20 V for almos 100 μs. Depending on he dv/d rae of V DD sar up, his ime could be longer and herefore, he hermal sress o he SiC MOSFET should be aken ino consideraion when programming UVSET. SYSTEM PERFORMANCE For V DD > 7 V, he quiescen curren ramps up linearly unil he se UVLO hreshold is crossed. The blue race shown in Figure 16, represens V DD versus I DD wih no inpu 13

14 Figure 17. CH1 IN+, CH2 V DD, CH3 OUT, CH4 V EE ; V DD(UVLO ) = 12 V, V EE(UVLO) = 4 V The same sar up waveform is shown in Figure 18 bu UVSET = 3 V (no shown) which equaes o V DD(UVLO) = 18 V. In his case, OUT (V GS ) is enabled when V DD = 18 V, even hough V EE < 4 V (V EE = 5 V). Which UVLO is dominan will depend on he dv/d rae of V DD versus V EE. The key poin is ha he NCP51705 oupu is disabled unil boh, V DD and V EE are above and below heir respecive UVLO hresholds. Compared o Figure 17, noice he effec ha a higher UVLO seing has on OUT (V GS ), where he firs OUT pulse appears near 20 V and 5 V. Figure 19. V EE Sar Up Shudown operaion is smooh wih no gliches. As shown in Figure 20, OUT ceases swiching and racks V EE which is unloaded. The discharge ime from 5 V o 0 V for V EE is approximaely 300 ms. Figure 20. CH1 IN+, CH2 V DD, CH3 OUT, CH4 V EE ; Shu Down Figure 18. CH1 IN+, CH2 V DD, CH3 OUT, CH4 V EE ; V DD(UVLO ) = 18 V, V EE(UVLO) = 4 V The NCP51705 inernal charge pump has a slow conrol loop and he effec of his is seen by he sligh undershoo and <400 μs correcion observed during V EE sar up shown in Figure 19. Beyond 400 μs, he V EE volage seles o he regulaion se poin of 3 V, 5 V or 8 V. A zoom of he ime base from Figure 20 is shown in Figure 21. UVSET is configured for 3 V (V DD(UVLO) = 18 V) and he inernal V DD UVLO hyseresis is inernally fixed a 1 V. The curser posiion reveals ha V DD = 17 V (18 V 1 V hyseresis), when he oupu is disabled, even hough V EE = 4.5 V (VEESET = V5V) and is sill acive according i s 4 V UVLO. Alhough he decay of V DD is slow, a clean erminaion of he las oupu pulse can also be observed wih no spurious pulses or gliches afer UVLO_OFF. 14

15 Figure 21. CH1 IN+, CH2 V DD, CH3 OUT, CH4 V EE ; Shu Down, V DD _UVLO(OFF) = 17 V The urn on propagaion delay is measured from 90% IN+ rising o 10% OUT rising. Alhough a SiC driver will operae a higher V DD, mos MOSFET propagaion delays are specified swiching ino a 1 nf load wih V DD = 12 V. Figure 22 shows he measured urn on, propagaion delay, under hese sandard es condiions, o be 19 ns. Figure 23. CH1 IN+, CH2 V DD, CH4 OUT; Falling Edge Prop Delay The DESAT and XEN waveforms are shown in Figure 24 and Figure 25 respecively. Since esing was done o verify IC validaion only (no power sage), a 100 pf, fixed capacior is conneced o he DESAT pin. The waveforms shown in Figure 24 indicae DESAT is below he 7.5 V hreshold and he oupu is swiching under normal operaion. If he IN+ frequency is decreased (increased on ime), he 100 pf DESAT capacior will be allowed o charge o a higher volage. This is shown in Figure 25 where he DESAT volage has reached he 7.5 V hreshold. The oupu railing edge is erminaed before he inpu volage swiches LOW. A shallow DESAT ramp is used o highligh he fac ha no gliches appear on he erminaed OUT pulse. In a swiching power supply applicaion, a small (<100 pf) exernal capacior can be used on he DESAT pin for high frequency noise filering. The XEN signal is he inverse of he OUT signal. Wheher he driver is operaing normal or under a DESAT faul, he XEN signal is shown o accuraely rack he inverse OUT signal for eiher case. Figure 22. CH1 IN+, CH2 V DD, CH4 OUT; Rising Edge Prop Delay Similarly, he urn off propagaion delay is measured from 10% IN+ falling o 90% OUT falling. Figure 23 shows he measured urn off, propagaion delay under he same sandard es condiions is 22 ns. The oupu rise and fall imes for each edge are approximaely 5 ns. 15

16 Several fundamenal applicaion examples highlighing he NCP5170 are shown as follows. Figure 24. CH1 IN+, CH2 OUT, CH3 DESAT, CH4 XEN; V DESAT < 7.5 V Low Side Swiching Figure 26 shows a op level schemaic highlighing he NCP51705 used in a low side swiching applicaion. No isolaion is shown so he inerface beween he conroller and driver is direc, hough his may no always be he case. This schemaic is shown o raise awareness of how few exernal componens are required o provide a fully funcional, reliable and robus SiC gae drive circui. I should also be menioned ha alhough only a single VDD volage rail is required i should be raed for a leas 50 V/ns o preven spurious curren pulses described in he discree gae drive descripion in secion Discree SIC Gae Drive. If he VDD volage rail is provided by a dedicaed auxiliary housekeeping power supply, special aenion should be given o design a ransformer feauring ulra low, primary secondary sray capaciance. 20 V Figure 25. CH1 IN+, CH2 OUT, CH3 DESAT, CH4 XEN; V DESAT = 7.5 V Conroller VEESET=SGND VEESET=OPEN VEESET=V5V VEESET=SVDD IN+ 1 IN 2 XEN 3 SGND 4 VEESET 5 VCH 6 OFF 3.5 V 5 V 8 V C UVSET C 8 23 V5V PGND 9 22 DESAT PGND SVDD VEE VDD VEE VDD NCP51705 (Top View) OUTSRC 18 OUTSRC 17 PGND 16 PGND OUTSNK OUTSNK 13 Figure 26. Low Side Swiching Example APPLICATIONS SiC MOSFETs can penerae any applicaion spaces where IGBTs are presenly used. Some of he more common uses include high volage swiching power supplies, hybrid and elecric vehicle chargers, elecric railway ransporaion, welders, lasers, indusrial equipmen and environmens where high emperaure operaion is criical. Two areas ha are paricularly ineresing for SiC are solar inverers and high volage daa ceners. Higher dc volages are beneficial for reducing wire gauge hickness, juncion boxes, inerconnecions and ulimaely minimizing conducion loss hereby increasing efficiency. Mos large scale, phoovolaic sysems currenly operae from a 1 kv dc bus and he rend is moving oward a 1.5 kv bus. Similarly, daa ceners using a 380 V disribuion nework can boos dc volages as high as 800 V. Half Bridge Concep A more realisic use of SiC MOSFETs can be found in half bridge power opologies such as he one shown in Figure 27. High power applicaions end o prefer isolaed drivers for boh, he high side and low side. This implies he need for wo digial isolaors. Depending on he amoun of IO crossing he isolaion boundary, a srong debae for secondary side conrol could be made for such applicaions. In his simplified example, IN+ and IN (Enable) are he only wo signals sourced from he digial conroller and XEN is read back from he NCP XEN is can be used as he iming informaion basis for developing gae drive iming, cross conducion prevenion, dead ime adjusmen and faul deecion. In addiion, emperaure sensing, hermal managemen (fan conrol) and higher levels of faul 16

17 response may also be done by he digial conroller. The V5V from he NCP51705 can be used o power he secondary side of each digial isolaor as shown Figure 27. CONTROLLER BIAS (3.3 V or 5 V) Digial Conroller FAULT_HS FAULT_LS PWM_HS XEN_HS ENABLE PWM_LS ISOLATOR BIAS Digial Isolaors ISOLATOR BIAS 20 V BIAS (isolaed) Quasi Resonan (QR) Flyback A 100 W, QR flyback converer operaing from a wide inpu range of 300 V < V IN < 1 kv was designed using he NCP1340B1 conroller and NCP51705 SiC driver. Converers of his class can ypically be found in phoovolaic and indusrial applicaions bu when based on IGBT power sages, swiching frequencies are in he range of 65 khz. The schemaic shown in Figure 28 is a QR flyback and he frequency is varying beween 377 khz < F S < 430 khz, from 100% o 25% load, a V IN = 300 V. XEN_LS Isolaion Boundary Figure 27. Half Bride Concep 17

18 Figure V o 24 V, 100 W, 400 khz, QR Flyback 18

19 For V IN = 300 V, he drain source volage waveform is he sum of he inpu volage and he refleced oupu volage. The waveform shown in Figure 29 highlighs he converer operaing a full duy cycle operaion (V IN = 300 V) wih 720 V appearing on drain source of he SiC MOSFET. The V DS rising ransiion is ~30 ns which equaes o dv DS /d = 24 V/ns. The NCP1340B1, QR conrol enables a sof, resonan ransiion and valley swiching ( near ZVS urn on a minimum V DS resonance) on he V DS falling edge and his is clearly visible on he blue waveform. Because he QR flyback is a low side only applicaion and he falling dv DS /d edge is resonan, i may be possible for he SiC MOSFET o reliably swich beween 0 V < V GS < 20 V. Noneheless, he design shown in Figure 28 oped for swiching beween 5 V < V GS < 20 V resuling in more robus swiching a he sligh penaly of increased gae charge. Figure 30. NCP5170 Mini EVB Schemaic Figure 29. CH3 = V DS, CH4 = V GS ; V IN = 300 V, V OUT = 24 V, I OUT = 4 A, F S = 377 khz General Purpose NCP5170 Cusomer EVB A general purpose evaluaion board (EVB) has been designed for he purpose of evaluaing he NCP51705 performance in new or exising designs. The EVB does no include a power sage and is generic from he poin of view ha i is no dedicaed o any paricular opology. I can be used in any low side or high side power swiching applicaion. For bridge configuraions wo or more of hese EVBs can be used a each SiC MOSFET in a oem pole ype drive configuraion. The EVB can be considered as an isolaor + driver + TO 247 discree module. The EVB schemaic is shown in Figure 30. The focus is o provide an ulra compac design, where he leads of a TO 247 SiC MOSFET can be conneced direcly o he prined circui board (PCB). Figure 31 shows simulaneous, op and boom views of he EVB nex o an adjacen TO 247 package for size scaling. Figure 31. NCP5170 Mini EVB Top View (35 mm x 15 mm) When mouning ino an exising power supply design and here is available PCB area in fron of he TO 247, he EVB can be insalled horizonally o he main power board, as shown in Figure 32. If possible, his should is he preferred mouning mehod. 19