An All-analog Time-walk Free SCA for Event Counting Pixel Detectors

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1 An All-analog ime-walk Free SCA for Event Counting Pixel Detectors M. A. ABDALLA 1,2, C. FRÖJDH 1, C. S. PEERSSON 2 1 Mitthögskolan, IE, S Sundsvall, Sweden 2 Kungl ekniska Högskolan, Inst för Elektronik, Electrum 229, S Kista, Sweden Abstract: - A new concept of an all-analog integrating single channel analyzer (SCA) for radiation pixel detectors is proposed. he principal idea is to output an analog signal that corresponds to the event counts during exposure time. Output signals from a window discriminator in the pixel control the charging/discharging a storage capacitor by a current source/sink depending on the pulse height. A very low noise performance is expected since no digital noise is involved. In addition, since no digital counter is included in the pixel a significant reduction in area and power concumption is obtained. he window discriminator is insensitive to the rise time of the pulse. Circuit constrains are discussed, and a performance simulation is presented for a design example. Key -words: SCA, window discriminator, pixel detector, photon counting, radiation imaging 1. Introduction Pixel sensors for event counting are widely used in high energy physics and other applications for different types of measurements, e.g., medical imaging, particle tracking and beam profiling [1, 2, 3]. Event counting is very advantageous over inetgrating type radiation measurement because of its high dynamic range and energy resolving capability. For many applications, especially in medical radiology and material science, it is vital to measure the absorption of radiation in a certain evergy range after passing through the X-ray medium. his is usually acheived by employing energy discrimination circuits. In radiation imaging, since all the analog and digital processing channels circuitry for a linear pulse signal is accomodated in each pixel, area constrains is the main challenge in the pixel design because spatial resolution is a prime image property. he analog circuit in each pixel consists of a preamplifier, a pulse shaping amplifier in addition to comparators for pulse height discrimination. On the other hand, the digital part includes the necessary pulse discrimination logic together with a digital counter and associated readout logic. he pixel also should include an active sensing area or a space for a bonding pad if chip bonding is used in the case of a hybridized semiconductor pixel detector. he analog and digital circuitries almost equally share most of the pixel area. For a wide dynamic range the digital counter has to be more that 14-bit for most typical applications. Using dynamic logic in the counter implementation necessiates a large number of transistors in addition to a refresh signal overhead. o avoid the time-walk effect that might result in spurious pulses that cause faulty counts, complex circuitries are used [4, 5]. Some designs even use a pair of counters to achieve window discrimination by subtracting, off-chip, the contents of the two counters[6, 7]. he simplest topology for implementing the counter uses the linear feedback shift register technique[8]. Here the shift counter outputs an pseudorandom code that needs additional software overhead for decoding using, e.g., lookup tables. he refresh signal for the dynamic logic adds to the system deadtime. On the other hand, the noise performance of mixed mode operation puts hard constrains on the pixel design. Moreover, the fast clocking of the digital readout adds high transient noise and significant power consumption. In this paper we are proposing a new single channel analyzer where no in-pixel digital counter is used. he event count is instead represented by an integrated current on a storage capacitor for later readout. he window discriminator is allanalog that generates signals that control the current integration, positively or negatively, on the

2 capacitor. he total final charge will then correspond to the total number of events incident on the detector. he number of events can then be extracted by an off-chip analog-to-digital conversion. 2. Circuit Description he proposed circuit consists of two integral discriminators, two monostable multivibrators, a current source/sink control and a storage capacitor. he schematic diagram together with timing diagram is shown in Fig.1. Prior to each measurement the capacitor C i is charged by the Reset signal applied to the gate of transistor Mr. When a linear pulse arrives at the discriminators s, the lower-level discriminator (LLD) switches on if the pulse amplitude is greater than the lower threshold level. he monostable MS1 is thus edge triggered and a digital pulse is generated for a fixed duration,. he transistor M1 is switched on to operate the current sink, I ref1. he capacitor C i is in effect discharged with a constant current I ref1 for the period. If the signal amplitude peaks below the upper threshold level, then the capacitor remains discharged an amount of charge equivalent to an event incremental count. Otherwise, the linear pulse height exceeds the upper threshold, and the output of the upper-level discriminator (ULD) swings high triggering monostable MS2. MS2 will then generate a digital pulse of the same duration as MS1, i.e. with duration. Consequently, transistor M2 is switched on to operate the current source I ref2 (I ref2 =I ref1 ), which will recharge the capacitor C i an amount of charge equivalent to an event representing a decrimental count as an opposite effect to the current discharge by I ref1. In this manner, the capacitor discharge when the pulse is higher than the lower threshold is cancelled by the capacitor recharge if the linear pulse lies off the discriminators window, i.e., higher than the upper threshold. he capacitor charging and discharging operation is anologous to an increment and decrement of a digital counter. In this scheme the net charge on the capacitor, C i, after a certain measurement time will be equivalent to the number of linear pulses (events) that arrived at the discriminators s. With the use of the two separate monostables (MS1 and MS2) the time walk, that is the time the linear pulse takes to rise from the lower-level threshold and the upper-level threshold (denoted D in the timing digram in Fig.1b), is automatically avoided. his time walk has always been a serious limitation in window discriminators design because it needs complicated circuitries to eleminate. upper threshold lower threshold (a) ULD LLD Upper threshold Lower threshold LLD output ULD output MS1 output MS2 output (b) MS2 MS1 VDD VSS 3. Precision Requirements he charge capacitor in each pixel, C i, is the key performance factor, since it determines the dynamic range of the pixel. In this design, if we assume a dynamic range equivalent to a 14-bits counter, then the corresponding number of discharging pulses is If we design a 1pF capacitor and a monostable relaxation time,, equals to 50ns, then the current value required to charge or discharge the capacitor from 0 to 5 volts I ref2 I ref1 M2 M1 Mr SCA output (voltage on the capacitor) C i Reset Fig. 1 a) Schematic diagram of the proposed SCA. b) functional timing diagram. D

3 is equal to 60nA. In a high capacitor CMOS process, a capacity of 1770pF/mm 2 is available, which means in such process a 1pF capacitor will occupy an area equals to 24x24µm 2. Compared to the area needed to implement equivalent 14-bits digital counter and associated logic this capacitor area is significantly small. he accuracy and uniformity of the pixel parameters over an entire pixel array, in addition to the stability of the charging and discharging currents, are the main constrains governing the circuit performance. Since the low discharge currents values are low (nano ampere), the corresponding sourcing (sinking) transistors might work in nonsaturation modes where they will be sensitive to threshold and temperature variations. Methods for stablizing the circuit output such as those described in [9, 10] can be utilized. As described in ref [9], N replica of a mirror transistor will reduce the variation of transistor output significantly if the mirror transistors are biased in the same manner as should be implemented in the bias network box in Fig.2. he use of these methods enables the implementation of small size transistors in the pixel. he use of a high charge storage capability linear ploy/ poly capacitor that is available in some CMOS process greatly reduces the mismatch and accuracy problems if a careful layout design technique is followed. Another source of output nonlinearity is the transistors parameters such like short channel effects in mirror circuits. his can be significantly reduced by using special mirror configurations like Wilson mirrors or cascode current mirrors. Unlike Wilson and the standard cascode configurations, the low voltage cascode can be used for a more efficient operation, because of its lower minimum saturation voltage [11]. his feature is important since it results in a higher dynamic range on the storage capacitor. he two current generators, I ref1 and I ref2, should be used to tune the charging and discharging currents to equal values. In addition, the storage capacitor C i should be reset to about 4 volts to allow the operation of the PMOS mirrors. he NMOS transistor will also operate properly till the voltage on the capacitor reaches below 1 volt. hus the linear dynamic range is in effect equals to 3 volts. he output resultant circuit should thus become as shown in Fig.2. In a pixel array implementation, there will be a single bias circuit external to the array which provides the I ref currents to all the pixels. A careful design will allow the use of a minimum size feature for all the transistors Mn1, Mn2, Mp1, Mp2, M1, M2 and Mr. upper threshold lower threshold ULD LLD MS2 MS1 VDD VSS 4. Simulation Results o verify the feasibility of this proposed SCA, a circuit was designed and simulated using Mentor Graphics tools under Austria Microsystems (AMS) CMOS 0.8µm process environment. Fig.3 displays the output response when a train of linear triangler pulses was applied to the discriminators s with a charging current of 100nA and a monosable relaxation time,, equals to approximately 65nS. he pulse amplitude was set to be higher than the discriminators window. he output clearly remained constant as a result of precise charging and descharging operation. A zoomed-in plot also shows the charging and discharging currents. I ref Mn1&Mn2 N. replica of Mp1&Mp2 N. replica of Bias n-work I ref Vb Mp1 M2 M1 Mr Mn1 C i 4volts Reset Fig. 2 Schematic diagram of the SCA showing the low voltage cascode mirror and biasing circuit. time Fig. 3 Output signal for a train of pulses that are higher than the both the lower-level and upperlevel threshols, i.e., lie off the discriminators window. Mn2 Mp2

4 On the other hand, Fig.4 shows the capacitor voltage when the pulse lies within the discriminators window. he figure shows the linearity of the output till ~ 1 volt for two different process parameters. his includes low, high and typical capacitance and resistance cases in the process. Despite the amplitude shift, there is small variation in the slopes which indicates the little effect from the process variations. his variations could cause fixed-pattern noise in a pixel array response, which can be corrected using gain map techniques[12]. However, the curve bending at lower capacitor voltage is due to the current mirror response for low output voltages(minimum saturation voltage). Nevertheless, nonlinearity can always be calibrated. Fig. 4 he output signal for a train of pulses that are within the discriminators window for two process parameters. at higher temperature at lower temperature Fig. 5 he output signal for a train of pulses that are within the discriminators window at different temperatures.(-60 o C to 30 o C) In Fig.5 the output response simulated for different temperatures (-60 o C to 30 o C) is shown. his temperature change represents a 180mv threshold change. It is also clear that despite the amplitude shift, the slope exhibits a negligible change. However, since this simulation was done on an example design, a more precise and careful design of the replica bias circuit in a practical prototype is expected to further improve the response. Nevertheless, this example circuit helps demonstrate the principle circuit concept. 5. Conclusions We have presented in this paper a proposed concept of an all-analog single channel analyzer for single photon counting pixel sensors. he principal concept stems on the control of a charging and discharging an in-pixel capacitor depending on the pulse height of a linear pulse. he capacitor is discharged a certain amount of charge dictated by monostables pulse widths and discharging currents. his circuit solution eleminates completely the digital counter and associated logic which results in dramatic area saving that is a pivotal challenge in pixel detectors. For example, a 14-bit counter implemented with the simplest topology(shift counter) and dynamic logic would require about 84 transistors with 6 transistors per flip-flop; which corresponds to an estimated area greater than 14000µm 2 in a typical 0.8µm CMOS process. A 2pF capacitor, in contrast, will occupy only a 500µm 2 if a high capacitor CMOS process is used (AMS CYE technology). Moreover, since there is no digital circuit within the pixels, the digital noise and power consumption will highly be reduced. In addition, all the mixed-mode design complications will be eleminated. A very important feature of this design is the time-walk free response since the response of the two monostables give two independent signals irrespective of the rise time of the pulse. he main critical design constrains are the expected nonuniformity of the output of a pixel array due to process and temperature variations. hese effect will be relatively high when using very small charging/discharging current. However, using appropriate current values will result in a safer circuit performance. Otherwise, special biasing techniques can be implemented [9, 10]. 6. Acknowledgement he support from Mid-Sweden University is gratefully acknowledged.

5 7. References [1] Colby D. Boles, et. al., "A multimode digital detector readout for solid-stse medical imaging detectors", IEEE jssc, vol 33, no. 5, May [2] M. Campbell, et. al., "A readout chip for a 64x64 pixel matrix with 15-bit single photon counting", IEEE trans. on Nucl. Sci., Vol 45, No.3, june [3] Ch. Brönnimann, et. al., "Synchrotron beam test with a photon-counting pixel detector", J Synchrotron Rad. (2000), 7, [4] B.. urko, R. C. Smith, "A precision timing discriminator for high density detector systems", IEEE trans. on Nucl. Sci., Vol 39, No.5, Oct [5] M. L. Simpson, et. al., "An integrated CMOS constant-fraction timing discriminator for multichannel detector system", IEEE trans. on Nucl. Sci., Vol 42, No.4, Aug [6] P. Fischer, et. al., "A photon counting pixel chip with energy windowing", IEEE trans. on Nucl. Sci., Vol 47, No.3, pp , [7] F. Pengg, et al., "Pixel fronend electronics in a radiation hard technology for hybrid and monolithic applications", IEEE trans. on Nucl. Sci., Vol 43, No.3, June [8] John F. Wakerly, Digital design principles and practices, ISBN , 3rd Ed., pp.730 [9] P. O Connor, et. al., " CMOS preamplefier with high linearity and ultra low noise for X- ray spectroscopy", IEEE trans. on Nucl. Sci [10]M. Abdalla, et. al., "A new biasing method for preamplifier-shapers", Proc. of IEEE ICECS 2K. [11]Erik Bruun, Peter Shah, " Dynamic range of low-voltage cascode current mirrors", Proc. of IEEE ISCAS vol.2, pp [12]R. Irsigler, et. al., "Evaluation of 329x240 pixel LEC GaAs schottky barrier X-ray imaging arrays hybridized to CMOS readout circuit based on charge integration", Nucl. Inst. and Meth., vol. 434, issue 1, pp24-29, sept

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