An All-analog Time-walk Free SCA for Event Counting Pixel Detectors
|
|
- Marcus Phelps
- 6 years ago
- Views:
Transcription
1 An All-analog ime-walk Free SCA for Event Counting Pixel Detectors M. A. ABDALLA 1,2, C. FRÖJDH 1, C. S. PEERSSON 2 1 Mitthögskolan, IE, S Sundsvall, Sweden 2 Kungl ekniska Högskolan, Inst för Elektronik, Electrum 229, S Kista, Sweden Abstract: - A new concept of an all-analog integrating single channel analyzer (SCA) for radiation pixel detectors is proposed. he principal idea is to output an analog signal that corresponds to the event counts during exposure time. Output signals from a window discriminator in the pixel control the charging/discharging a storage capacitor by a current source/sink depending on the pulse height. A very low noise performance is expected since no digital noise is involved. In addition, since no digital counter is included in the pixel a significant reduction in area and power concumption is obtained. he window discriminator is insensitive to the rise time of the pulse. Circuit constrains are discussed, and a performance simulation is presented for a design example. Key -words: SCA, window discriminator, pixel detector, photon counting, radiation imaging 1. Introduction Pixel sensors for event counting are widely used in high energy physics and other applications for different types of measurements, e.g., medical imaging, particle tracking and beam profiling [1, 2, 3]. Event counting is very advantageous over inetgrating type radiation measurement because of its high dynamic range and energy resolving capability. For many applications, especially in medical radiology and material science, it is vital to measure the absorption of radiation in a certain evergy range after passing through the X-ray medium. his is usually acheived by employing energy discrimination circuits. In radiation imaging, since all the analog and digital processing channels circuitry for a linear pulse signal is accomodated in each pixel, area constrains is the main challenge in the pixel design because spatial resolution is a prime image property. he analog circuit in each pixel consists of a preamplifier, a pulse shaping amplifier in addition to comparators for pulse height discrimination. On the other hand, the digital part includes the necessary pulse discrimination logic together with a digital counter and associated readout logic. he pixel also should include an active sensing area or a space for a bonding pad if chip bonding is used in the case of a hybridized semiconductor pixel detector. he analog and digital circuitries almost equally share most of the pixel area. For a wide dynamic range the digital counter has to be more that 14-bit for most typical applications. Using dynamic logic in the counter implementation necessiates a large number of transistors in addition to a refresh signal overhead. o avoid the time-walk effect that might result in spurious pulses that cause faulty counts, complex circuitries are used [4, 5]. Some designs even use a pair of counters to achieve window discrimination by subtracting, off-chip, the contents of the two counters[6, 7]. he simplest topology for implementing the counter uses the linear feedback shift register technique[8]. Here the shift counter outputs an pseudorandom code that needs additional software overhead for decoding using, e.g., lookup tables. he refresh signal for the dynamic logic adds to the system deadtime. On the other hand, the noise performance of mixed mode operation puts hard constrains on the pixel design. Moreover, the fast clocking of the digital readout adds high transient noise and significant power consumption. In this paper we are proposing a new single channel analyzer where no in-pixel digital counter is used. he event count is instead represented by an integrated current on a storage capacitor for later readout. he window discriminator is allanalog that generates signals that control the current integration, positively or negatively, on the
2 capacitor. he total final charge will then correspond to the total number of events incident on the detector. he number of events can then be extracted by an off-chip analog-to-digital conversion. 2. Circuit Description he proposed circuit consists of two integral discriminators, two monostable multivibrators, a current source/sink control and a storage capacitor. he schematic diagram together with timing diagram is shown in Fig.1. Prior to each measurement the capacitor C i is charged by the Reset signal applied to the gate of transistor Mr. When a linear pulse arrives at the discriminators s, the lower-level discriminator (LLD) switches on if the pulse amplitude is greater than the lower threshold level. he monostable MS1 is thus edge triggered and a digital pulse is generated for a fixed duration,. he transistor M1 is switched on to operate the current sink, I ref1. he capacitor C i is in effect discharged with a constant current I ref1 for the period. If the signal amplitude peaks below the upper threshold level, then the capacitor remains discharged an amount of charge equivalent to an event incremental count. Otherwise, the linear pulse height exceeds the upper threshold, and the output of the upper-level discriminator (ULD) swings high triggering monostable MS2. MS2 will then generate a digital pulse of the same duration as MS1, i.e. with duration. Consequently, transistor M2 is switched on to operate the current source I ref2 (I ref2 =I ref1 ), which will recharge the capacitor C i an amount of charge equivalent to an event representing a decrimental count as an opposite effect to the current discharge by I ref1. In this manner, the capacitor discharge when the pulse is higher than the lower threshold is cancelled by the capacitor recharge if the linear pulse lies off the discriminators window, i.e., higher than the upper threshold. he capacitor charging and discharging operation is anologous to an increment and decrement of a digital counter. In this scheme the net charge on the capacitor, C i, after a certain measurement time will be equivalent to the number of linear pulses (events) that arrived at the discriminators s. With the use of the two separate monostables (MS1 and MS2) the time walk, that is the time the linear pulse takes to rise from the lower-level threshold and the upper-level threshold (denoted D in the timing digram in Fig.1b), is automatically avoided. his time walk has always been a serious limitation in window discriminators design because it needs complicated circuitries to eleminate. upper threshold lower threshold (a) ULD LLD Upper threshold Lower threshold LLD output ULD output MS1 output MS2 output (b) MS2 MS1 VDD VSS 3. Precision Requirements he charge capacitor in each pixel, C i, is the key performance factor, since it determines the dynamic range of the pixel. In this design, if we assume a dynamic range equivalent to a 14-bits counter, then the corresponding number of discharging pulses is If we design a 1pF capacitor and a monostable relaxation time,, equals to 50ns, then the current value required to charge or discharge the capacitor from 0 to 5 volts I ref2 I ref1 M2 M1 Mr SCA output (voltage on the capacitor) C i Reset Fig. 1 a) Schematic diagram of the proposed SCA. b) functional timing diagram. D
3 is equal to 60nA. In a high capacitor CMOS process, a capacity of 1770pF/mm 2 is available, which means in such process a 1pF capacitor will occupy an area equals to 24x24µm 2. Compared to the area needed to implement equivalent 14-bits digital counter and associated logic this capacitor area is significantly small. he accuracy and uniformity of the pixel parameters over an entire pixel array, in addition to the stability of the charging and discharging currents, are the main constrains governing the circuit performance. Since the low discharge currents values are low (nano ampere), the corresponding sourcing (sinking) transistors might work in nonsaturation modes where they will be sensitive to threshold and temperature variations. Methods for stablizing the circuit output such as those described in [9, 10] can be utilized. As described in ref [9], N replica of a mirror transistor will reduce the variation of transistor output significantly if the mirror transistors are biased in the same manner as should be implemented in the bias network box in Fig.2. he use of these methods enables the implementation of small size transistors in the pixel. he use of a high charge storage capability linear ploy/ poly capacitor that is available in some CMOS process greatly reduces the mismatch and accuracy problems if a careful layout design technique is followed. Another source of output nonlinearity is the transistors parameters such like short channel effects in mirror circuits. his can be significantly reduced by using special mirror configurations like Wilson mirrors or cascode current mirrors. Unlike Wilson and the standard cascode configurations, the low voltage cascode can be used for a more efficient operation, because of its lower minimum saturation voltage [11]. his feature is important since it results in a higher dynamic range on the storage capacitor. he two current generators, I ref1 and I ref2, should be used to tune the charging and discharging currents to equal values. In addition, the storage capacitor C i should be reset to about 4 volts to allow the operation of the PMOS mirrors. he NMOS transistor will also operate properly till the voltage on the capacitor reaches below 1 volt. hus the linear dynamic range is in effect equals to 3 volts. he output resultant circuit should thus become as shown in Fig.2. In a pixel array implementation, there will be a single bias circuit external to the array which provides the I ref currents to all the pixels. A careful design will allow the use of a minimum size feature for all the transistors Mn1, Mn2, Mp1, Mp2, M1, M2 and Mr. upper threshold lower threshold ULD LLD MS2 MS1 VDD VSS 4. Simulation Results o verify the feasibility of this proposed SCA, a circuit was designed and simulated using Mentor Graphics tools under Austria Microsystems (AMS) CMOS 0.8µm process environment. Fig.3 displays the output response when a train of linear triangler pulses was applied to the discriminators s with a charging current of 100nA and a monosable relaxation time,, equals to approximately 65nS. he pulse amplitude was set to be higher than the discriminators window. he output clearly remained constant as a result of precise charging and descharging operation. A zoomed-in plot also shows the charging and discharging currents. I ref Mn1&Mn2 N. replica of Mp1&Mp2 N. replica of Bias n-work I ref Vb Mp1 M2 M1 Mr Mn1 C i 4volts Reset Fig. 2 Schematic diagram of the SCA showing the low voltage cascode mirror and biasing circuit. time Fig. 3 Output signal for a train of pulses that are higher than the both the lower-level and upperlevel threshols, i.e., lie off the discriminators window. Mn2 Mp2
4 On the other hand, Fig.4 shows the capacitor voltage when the pulse lies within the discriminators window. he figure shows the linearity of the output till ~ 1 volt for two different process parameters. his includes low, high and typical capacitance and resistance cases in the process. Despite the amplitude shift, there is small variation in the slopes which indicates the little effect from the process variations. his variations could cause fixed-pattern noise in a pixel array response, which can be corrected using gain map techniques[12]. However, the curve bending at lower capacitor voltage is due to the current mirror response for low output voltages(minimum saturation voltage). Nevertheless, nonlinearity can always be calibrated. Fig. 4 he output signal for a train of pulses that are within the discriminators window for two process parameters. at higher temperature at lower temperature Fig. 5 he output signal for a train of pulses that are within the discriminators window at different temperatures.(-60 o C to 30 o C) In Fig.5 the output response simulated for different temperatures (-60 o C to 30 o C) is shown. his temperature change represents a 180mv threshold change. It is also clear that despite the amplitude shift, the slope exhibits a negligible change. However, since this simulation was done on an example design, a more precise and careful design of the replica bias circuit in a practical prototype is expected to further improve the response. Nevertheless, this example circuit helps demonstrate the principle circuit concept. 5. Conclusions We have presented in this paper a proposed concept of an all-analog single channel analyzer for single photon counting pixel sensors. he principal concept stems on the control of a charging and discharging an in-pixel capacitor depending on the pulse height of a linear pulse. he capacitor is discharged a certain amount of charge dictated by monostables pulse widths and discharging currents. his circuit solution eleminates completely the digital counter and associated logic which results in dramatic area saving that is a pivotal challenge in pixel detectors. For example, a 14-bit counter implemented with the simplest topology(shift counter) and dynamic logic would require about 84 transistors with 6 transistors per flip-flop; which corresponds to an estimated area greater than 14000µm 2 in a typical 0.8µm CMOS process. A 2pF capacitor, in contrast, will occupy only a 500µm 2 if a high capacitor CMOS process is used (AMS CYE technology). Moreover, since there is no digital circuit within the pixels, the digital noise and power consumption will highly be reduced. In addition, all the mixed-mode design complications will be eleminated. A very important feature of this design is the time-walk free response since the response of the two monostables give two independent signals irrespective of the rise time of the pulse. he main critical design constrains are the expected nonuniformity of the output of a pixel array due to process and temperature variations. hese effect will be relatively high when using very small charging/discharging current. However, using appropriate current values will result in a safer circuit performance. Otherwise, special biasing techniques can be implemented [9, 10]. 6. Acknowledgement he support from Mid-Sweden University is gratefully acknowledged.
5 7. References [1] Colby D. Boles, et. al., "A multimode digital detector readout for solid-stse medical imaging detectors", IEEE jssc, vol 33, no. 5, May [2] M. Campbell, et. al., "A readout chip for a 64x64 pixel matrix with 15-bit single photon counting", IEEE trans. on Nucl. Sci., Vol 45, No.3, june [3] Ch. Brönnimann, et. al., "Synchrotron beam test with a photon-counting pixel detector", J Synchrotron Rad. (2000), 7, [4] B.. urko, R. C. Smith, "A precision timing discriminator for high density detector systems", IEEE trans. on Nucl. Sci., Vol 39, No.5, Oct [5] M. L. Simpson, et. al., "An integrated CMOS constant-fraction timing discriminator for multichannel detector system", IEEE trans. on Nucl. Sci., Vol 42, No.4, Aug [6] P. Fischer, et. al., "A photon counting pixel chip with energy windowing", IEEE trans. on Nucl. Sci., Vol 47, No.3, pp , [7] F. Pengg, et al., "Pixel fronend electronics in a radiation hard technology for hybrid and monolithic applications", IEEE trans. on Nucl. Sci., Vol 43, No.3, June [8] John F. Wakerly, Digital design principles and practices, ISBN , 3rd Ed., pp.730 [9] P. O Connor, et. al., " CMOS preamplefier with high linearity and ultra low noise for X- ray spectroscopy", IEEE trans. on Nucl. Sci [10]M. Abdalla, et. al., "A new biasing method for preamplifier-shapers", Proc. of IEEE ICECS 2K. [11]Erik Bruun, Peter Shah, " Dynamic range of low-voltage cascode current mirrors", Proc. of IEEE ISCAS vol.2, pp [12]R. Irsigler, et. al., "Evaluation of 329x240 pixel LEC GaAs schottky barrier X-ray imaging arrays hybridized to CMOS readout circuit based on charge integration", Nucl. Inst. and Meth., vol. 434, issue 1, pp24-29, sept
Circuit Architecture for Photon Counting Pixel Detector with Threshold Correction
Circuit Architecture for Photon Counting Pixel Detector with Threshold Correction Dr. Amit Kr. Jain Vidya college of Engineering, Vidya Knowledge Park, Baghpat Road, Meerut 250005 UP India dean.academics@vidya.edu.in
More informationCircuit Architecture for Photon Counting Pixel Detector with Thresholds Correction
International Journal of Electronics and Electrical Engineering Vol. 3, No. 6, December 2015 Circuit Architecture for Photon Counting Pixel Detector with Thresholds Correction Suliman Abdalla1, arwa ekki2,
More informationCDTE and CdZnTe detector arrays have been recently
20 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 44, NO. 1, FEBRUARY 1997 CMOS Low-Noise Switched Charge Sensitive Preamplifier for CdTe and CdZnTe X-Ray Detectors Claudio G. Jakobson and Yael Nemirovsky
More informationThe Medipix3 Prototype, a Pixel Readout Chip Working in Single Photon Counting Mode with Improved Spectrometric Performance
26 IEEE Nuclear Science Symposium Conference Record NM1-6 The Medipix3 Prototype, a Pixel Readout Chip Working in Single Photon Counting Mode with Improved Spectrometric Performance R. Ballabriga, M. Campbell,
More informationChromatic X-Ray imaging with a fine pitch CdTe sensor coupled to a large area photon counting pixel ASIC
Chromatic X-Ray imaging with a fine pitch CdTe sensor coupled to a large area photon counting pixel ASIC R. Bellazzini a,b, G. Spandre a*, A. Brez a, M. Minuti a, M. Pinchera a and P. Mozzo b a INFN Pisa
More informationAnalysis of 1=f Noise in CMOS Preamplifier With CDS Circuit
IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 49, NO. 4, AUGUST 2002 1819 Analysis of 1=f Noise in CMOS Preamplifier With CDS Circuit Tae-Hoon Lee, Gyuseong Cho, Hee Joon Kim, Seung Wook Lee, Wanno Lee, and
More informationA Prototype Amplifier-Discriminator Chip for the GLAST Silicon-Strip Tracker
A Prototype Amplifier-Discriminator Chip for the GLAST Silicon-Strip Tracker Robert P. Johnson Pavel Poplevin Hartmut Sadrozinski Ned Spencer Santa Cruz Institute for Particle Physics The GLAST Project
More informationAnalog CMOS Interface Circuits for UMSI Chip of Environmental Monitoring Microsystem
Analog CMOS Interface Circuits for UMSI Chip of Environmental Monitoring Microsystem A report Submitted to Canopus Systems Inc. Zuhail Sainudeen and Navid Yazdi Arizona State University July 2001 1. Overview
More informationX-ray Detectors: What are the Needs?
X-ray Detectors: What are the Needs? Sol M. Gruner Physics Dept. & Cornell High Energy Synchrotron Source (CHESS) Ithaca, NY 14853 smg26@cornell.edu 1 simplified view of the Evolution of Imaging Synchrotron
More informationFront-End and Readout Electronics for Silicon Trackers at the ILC
2005 International Linear Collider Workshop - Stanford, U.S.A. Front-End and Readout Electronics for Silicon Trackers at the ILC M. Dhellot, J-F. Genat, H. Lebbolo, T-H. Pham, and A. Savoy Navarro LPNHE
More informationA high speed and low power CMOS current comparator for photon counting systems
F. Borghetti, L. Farina, P. Malcovati, F. Maloberti: "A high speed and low power CMOS current comparator for photon counting systems"; Proc. of the 2004 Int. Symposium on Circuits and Systems, ISCAS 2004,
More informationA flexible compact readout circuit for SPAD arrays ABSTRACT Keywords: 1. INTRODUCTION 2. THE SPAD 2.1 Operation 7780C - 55
A flexible compact readout circuit for SPAD arrays Danial Chitnis * and Steve Collins Department of Engineering Science University of Oxford Oxford England OX13PJ ABSTRACT A compact readout circuit that
More informationK. Desch, P. Fischer, N. Wermes. Physikalisches Institut, Universitat Bonn, Germany. Abstract
ATLAS Internal Note INDET-NO-xxx 28.02.1996 A Proposal to Overcome Time Walk Limitations in Pixel Electronics by Reference Pulse Injection K. Desch, P. Fischer, N. Wermes Physikalisches Institut, Universitat
More informationSUMMARY/DIALOGUE 2 PRESHAPE PIXEL OVERVIEW 3 BRIEF OPERATING INSTRUCTIONS 3 PRESHAPE PIXEL SIMULATION: EXAMPLE OPERATION 4 PRESHAPE PIXEL SIMULATION:
SUMMARY/DIALOGUE 2 PRESHAPE PIXEL OVERVIEW 3 BRIEF OPERATING INSTRUCTIONS 3 PRESHAPE PIXEL SIMULATION: EXAMPLE OPERATION 4 PRESHAPE PIXEL SIMULATION: SMALL SIGNALS AROUND THRESHOLD 5 PRESHAPE PIXEL SIMULATION:
More informationDifference between BJTs and FETs. Junction Field Effect Transistors (JFET)
Difference between BJTs and FETs Transistors can be categorized according to their structure, and two of the more commonly known transistor structures, are the BJT and FET. The comparison between BJTs
More informationDead-Time Control System for a Synchronous Buck dc-dc Converter
Dead-Time Control System for a Synchronous Buck dc-dc Converter Floriberto Lima Chipidea Microelectronics berto@chipidea.com Marcelino Santos IST / INESC-ID marcelino.santos@ist.utl.pt José Barata IST,
More informationA new class AB folded-cascode operational amplifier
A new class AB folded-cascode operational amplifier Mohammad Yavari a) Integrated Circuits Design Laboratory, Department of Electrical Engineering, Amirkabir University of Technology, Tehran, Iran a) myavari@aut.ac.ir
More informationA Current Mirroring Integration Based Readout Circuit for High Performance Infrared FPA Applications
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 50, NO. 4, APRIL 2003 181 A Current Mirroring Integration Based Readout Circuit for High Performance Infrared FPA
More informationSemiconductor Detector Systems
Semiconductor Detector Systems Helmuth Spieler Physics Division, Lawrence Berkeley National Laboratory OXFORD UNIVERSITY PRESS ix CONTENTS 1 Detector systems overview 1 1.1 Sensor 2 1.2 Preamplifier 3
More informationMulti-Element Si Sensor with Readout ASIC for EXAFS Spectroscopy 1
Multi-Element Si Sensor with Readout ASIC for EXAFS Spectroscopy 1 Gianluigi De Geronimo a, Paul O Connor a, Rolf H. Beuttenmuller b, Zheng Li b, Antony J. Kuczewski c, D. Peter Siddons c a Microelectronics
More informationUltra fast single photon counting chip
Ultra fast single photon counting chip P. Grybos, P. Kmon, P. Maj, R. Szczygiel Faculty of Electrical Engineering, Automatics, Computer Science and Biomedical Engineering AGH University of Science and
More informationElectronic Circuits EE359A
Electronic Circuits EE359A Bruce McNair B206 bmcnair@stevens.edu 201-216-5549 1 Memory and Advanced Digital Circuits - 2 Chapter 11 2 Figure 11.1 (a) Basic latch. (b) The latch with the feedback loop opened.
More informationALTHOUGH zero-if and low-if architectures have been
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 6, JUNE 2005 1249 A 110-MHz 84-dB CMOS Programmable Gain Amplifier With Integrated RSSI Function Chun-Pang Wu and Hen-Wai Tsao Abstract This paper describes
More informationElectronic Instrumentation for Radiation Detection Systems
Electronic Instrumentation for Radiation Detection Systems January 23, 2018 Joshua W. Cates, Ph.D. and Craig S. Levin, Ph.D. Course Outline Lecture Overview Brief Review of Radiation Detectors Detector
More informationComparison between Analog and Digital Current To PWM Converter for Optical Readout Systems
Comparison between Analog and Digital Current To PWM Converter for Optical Readout Systems 1 Eun-Jung Yoon, 2 Kangyeob Park, 3* Won-Seok Oh 1, 2, 3 SoC Platform Research Center, Korea Electronics Technology
More informationA PSEUDO-CLASS-AB TELESCOPIC-CASCODE OPERATIONAL AMPLIFIER
A PSEUDO-CLASS-AB TELESCOPIC-CASCODE OPERATIONAL AMPLIFIER M. Taherzadeh-Sani, R. Lotfi, and O. Shoaei ABSTRACT A novel class-ab architecture for single-stage operational amplifiers is presented. The structure
More informationA Readout ASIC for CZT Detectors
A Readout ASIC for CZT Detectors L.L.Jones a, P.Seller a, I.Lazarus b, P.Coleman-Smith b a STFC Rutherford Appleton Laboratory, Didcot, OX11 0QX, UK b STFC Daresbury Laboratory, Warrington WA4 4AD, UK
More informationLow noise Amplifier, simulated and measured.
Low noise Amplifier, simulated and measured. Introduction: As a study project a low noise amplifier shaper for capacitive detectors in AMS 0.6 µm technology is designed and realised. The goal was to design
More informationReadout electronics for LumiCal detector
Readout electronics for Lumial detector arek Idzik 1, Krzysztof Swientek 1 and Szymon Kulis 1 1- AGH niversity of Science and Technology Faculty of Physics and Applied omputer Science racow - Poland The
More informationCHAPTER 7 A BICS DESIGN TO DETECT SOFT ERROR IN CMOS SRAM
131 CHAPTER 7 A BICS DESIGN TO DETECT SOFT ERROR IN CMOS SRAM 7.1 INTRODUCTION Semiconductor memories are moving towards higher levels of integration. This increase in integration is achieved through reduction
More informationPulse Shape Analysis for a New Pixel Readout Chip
Abstract Pulse Shape Analysis for a New Pixel Readout Chip James Kingston University of California, Berkeley Supervisors: Daniel Pitzl and Paul Schuetze September 7, 2017 1 Table of Contents 1 Introduction...
More informationDesign and Test of a 65nm CMOS Front-End with Zero Dead Time for Next Generation Pixel Detectors
Design and Test of a 65nm CMOS Front-End with Zero Dead Time for Next Generation Pixel Detectors L. Gaioni a,c, D. Braga d, D. Christian d, G. Deptuch d, F. Fahim d,b. Nodari e, L. Ratti b,c, V. Re a,c,
More informationClass-AB Low-Voltage CMOS Unity-Gain Buffers
Class-AB Low-Voltage CMOS Unity-Gain Buffers Mariano Jimenez, Antonio Torralba, Ramón G. Carvajal and J. Ramírez-Angulo Abstract Class-AB circuits, which are able to deal with currents several orders of
More informationFast CMOS Transimpedance Amplifier and Comparator circuit for readout of silicon strip detectors at LHC experiments
Fast CMOS Transimpedance Amplifier and Comparator circuit for readout of silicon strip detectors at LHC experiments Jan Kaplon - CERN Wladek Dabrowski - FPN/UMM Cracow Pepe Bernabeu IFIC Valencia Carlos
More informationPreamplifier shaper: The preamplifier. The shaper. The Output.
Preamplifier shaper: In previous simulations I just tried to reach the speed limits. The only way to realise this was by using a lot of current, about 1 ma through the input transistor. This gives in the
More informationLow Noise Amplifier for Capacitive Detectors.
Low Noise Amplifier for Capacitive Detectors. J. D. Schipper R Kluit NIKHEF, Kruislaan 49 198SJ Amsterdam, Netherlands jds@nikhef.nl Abstract As a design study for the LHC eperiments a 'Low Noise Amplifier
More informationIEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 59, NO. 6, DECEMBER A Switcher ASIC Design for Use in a Charge-Pump Detector
IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 59, NO. 6, DECEMBER 2012 3205 A Switcher ASIC Design for Use in a Charge-Pump Detector Zhi Yong Li, Gianluigi De Geronimo, D. Peter Siddons, Durgamadhab Misra,
More informationDesign of Low Power CMOS Startup Charge Pump Based on Body Biasing Technique
Design of Low Power CMOS Startup Charge Pump Based on Body Biasing Technique Juliet Abraham 1, Dr. B. Paulchamy 2 1 PG Scholar, Hindusthan institute of Technology, coimbtore-32, India 2 Professor and HOD,
More informationAn Analog Phase-Locked Loop
1 An Analog Phase-Locked Loop Greg Flewelling ABSTRACT This report discusses the design, simulation, and layout of an Analog Phase-Locked Loop (APLL). The circuit consists of five major parts: A differential
More informationSingle Photon X-Ray Imaging with Si- and CdTe-Sensors
Single Photon X-Ray Imaging with Si- and CdTe-Sensors P. Fischer a, M. Kouda b, S. Krimmel a, H. Krüger a, M. Lindner a, M. Löcker a,*, G. Sato b, T. Takahashi b, S.Watanabe b, N. Wermes a a Physikalisches
More informationDesign of a Capacitor-less Low Dropout Voltage Regulator
Design of a Capacitor-less Low Dropout Voltage Regulator Sheenam Ahmed 1, Isha Baokar 2, R Sakthivel 3 1 Student, M.Tech VLSI, School of Electronics Engineering, VIT University, Vellore, Tamil Nadu, India
More information電子電路. Memory and Advanced Digital Circuits
電子電路 Memory and Advanced Digital Circuits Hsun-Hsiang Chen ( 陳勛祥 ) Department of Electronic Engineering National Changhua University of Education Email: chenhh@cc.ncue.edu.tw Spring 2010 2 Reference Microelectronic
More informationA radiation tolerant, low-power cryogenic capable CCD readout system:
A radiation tolerant, low-power cryogenic capable CCD readout system: Enabling focal-plane mounted CCD read-out for ground or space applications with a pair of ASICs. Overview What do we want to read out
More informationDesign and characterisation of a capacitively coupled HV-CMOS sensor for the CLIC vertex detector
CLICdp-Pub-217-1 12 June 217 Design and characterisation of a capacitively coupled HV-CMOS sensor for the CLIC vertex detector I. Kremastiotis 1), R. Ballabriga, M. Campbell, D. Dannheim, A. Fiergolski,
More informationESD-Transient Detection Circuit with Equivalent Capacitance-Coupling Detection Mechanism and High Efficiency of Layout Area in a 65nm CMOS Technology
ESD-Transient Detection Circuit with Equivalent Capacitance-Coupling Detection Mechanism and High Efficiency of Layout Area in a 65nm CMOS Technology Chih-Ting Yeh (1, 2) and Ming-Dou Ker (1, 3) (1) Department
More informationAssoc. Prof. Dr. Burak Kelleci
DEPARTMENT OF ELECTRICAL &ELECTRONICS ENGINEERING ANALOG-TO-DIGITAL AND DIGITAL- TO-ANALOG CONVERTERS Assoc. Prof. Dr. Burak Kelleci Fall 2018 OUTLINE Nyquist-Rate DAC Thermometer-Code Converter Hybrid
More informationFinal Results from the APV25 Production Wafer Testing
Final Results from the APV Production Wafer Testing M.Raymond a, R.Bainbridge a, M.French b, G.Hall a, P. Barrillon a a Blackett Laboratory, Imperial College, London, UK b Rutherford Appleton Laboratory,
More informationELEN6350. Summary: High Dynamic Range Photodetector Hassan Eddrees, Matt Bajor
ELEN6350 High Dynamic Range Photodetector Hassan Eddrees, Matt Bajor Summary: The use of image sensors presents several limitations for visible light spectrometers. Both CCD and CMOS one dimensional imagers
More informationThe Architecture of the BTeV Pixel Readout Chip
The Architecture of the BTeV Pixel Readout Chip D.C. Christian, dcc@fnal.gov Fermilab, POBox 500 Batavia, IL 60510, USA 1 Introduction The most striking feature of BTeV, a dedicated b physics experiment
More informationDESIGN & IMPLEMENTATION OF SELF TIME DUMMY REPLICA TECHNIQUE IN 128X128 LOW VOLTAGE SRAM
DESIGN & IMPLEMENTATION OF SELF TIME DUMMY REPLICA TECHNIQUE IN 128X128 LOW VOLTAGE SRAM 1 Mitali Agarwal, 2 Taru Tevatia 1 Research Scholar, 2 Associate Professor 1 Department of Electronics & Communication
More informationThe Concept of LumiCal Readout Electronics
EUDET The Concept of LumiCal Readout Electronics M. Idzik, K. Swientek, Sz. Kulis, W. Dabrowski, L. Suszycki, B. Pawlik, W. Wierba, L. Zawiejski on behalf of the FCAL collaboration July 4, 7 Abstract The
More informationAnalysis and Design of Analog Integrated Circuits Lecture 8. Cascode Techniques
Analysis and Design of Analog Integrated Circuits Lecture 8 Cascode Techniques Michael H. Perrott February 15, 2012 Copyright 2012 by Michael H. Perrott All rights reserved. Review of Large Signal Analysis
More informationDevelopment of an analog read-out channel for time projection chambers
Journal of Physics: Conference Series PAPER OPEN ACCESS Development of an analog read-out channel for time projection chambers To cite this article: E Atkin and I Sagdiev 2017 J. Phys.: Conf. Ser. 798
More informationA Multichannel Pipeline Analog-to-Digital Converter for an Integrated 3-D Ultrasound Imaging System
1266 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 7, JULY 2003 A Multichannel Pipeline Analog-to-Digital Converter for an Integrated 3-D Ultrasound Imaging System Kambiz Kaviani, Student Member,
More informationMEASUREMENT OF TIMEPIX DETECTOR PERFORMANCE VICTOR GUTIERREZ DIEZ UNIVERSIDAD COMPLUTENSE DE MADRID
MEASUREMENT OF TIMEPIX DETECTOR PERFORMANCE VICTOR GUTIERREZ DIEZ UNIVERSIDAD COMPLUTENSE DE MADRID ABSTRACT Recent advances in semiconductor technology allow construction of highly efficient and low noise
More informationAnalog-to-Digital-Converter User Manual
7070 Analog-to-Digital-Converter User Manual copyright FAST ComTec GmbH Grünwalder Weg 28a, D-82041 Oberhaching Germany Version 2.0, July 7, 2005 Software Warranty FAST ComTec warrants proper operation
More informationCHAPTER 6 DIGITAL INSTRUMENTS
CHAPTER 6 DIGITAL INSTRUMENTS 1 LECTURE CONTENTS 6.1 Logic Gates 6.2 Digital Instruments 6.3 Analog to Digital Converter 6.4 Electronic Counter 6.6 Digital Multimeters 2 6.1 Logic Gates 3 AND Gate The
More informationTRIANGULATION-BASED light projection is a typical
246 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 1, JANUARY 2004 A 120 110 Position Sensor With the Capability of Sensitive and Selective Light Detection in Wide Dynamic Range for Robust Active Range
More informationStatus of Front End Development
Status of Front End Development Progress of CSA and ADC studies Tim Armbruster tim.armbruster@ziti.uni-heidelberg.de CBM-XYTER Family Planning Workshop Schaltungstechnik und 05.12.2008 Introduction Previous
More informationA10-Gb/slow-power adaptive continuous-time linear equalizer using asynchronous under-sampling histogram
LETTER IEICE Electronics Express, Vol.10, No.4, 1 8 A10-Gb/slow-power adaptive continuous-time linear equalizer using asynchronous under-sampling histogram Wang-Soo Kim and Woo-Young Choi a) Department
More informationCMOS 0.35 µm Low-Dropout Voltage Regulator using Differentiator Technique
CMOS 0.35 µm Low-Dropout Voltage Regulator using Differentiator Technique 1 Shailika Sharma, 2 Himani Mittal, 1.2 Electronics & Communication Department, 1,2 JSS Academy of Technical Education,Gr. Noida,
More informationOperational Amplifier with Two-Stage Gain-Boost
Proceedings of the 6th WSEAS International Conference on Simulation, Modelling and Optimization, Lisbon, Portugal, September 22-24, 2006 482 Operational Amplifier with Two-Stage Gain-Boost FRANZ SCHLÖGL
More informationAdvanced Operational Amplifiers
IsLab Analog Integrated Circuit Design OPA2-47 Advanced Operational Amplifiers כ Kyungpook National University IsLab Analog Integrated Circuit Design OPA2-1 Advanced Current Mirrors and Opamps Two-stage
More informationIN RECENT years, low-dropout linear regulators (LDOs) are
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 52, NO. 9, SEPTEMBER 2005 563 Design of Low-Power Analog Drivers Based on Slew-Rate Enhancement Circuits for CMOS Low-Dropout Regulators
More informationThe Compact Muon Solenoid Experiment. Conference Report. Mailing address: CMS CERN, CH-1211 GENEVA 23, Switzerland
Available on CMS information server CMS CR -2017/385 The Compact Muon Solenoid Experiment Conference Report Mailing address: CMS CERN, CH-1211 GENEVA 23, Switzerland 25 October 2017 (v2, 08 November 2017)
More informationLow Power Design of Schmitt Trigger Based SRAM Cell Using NBTI Technique
Low Power Design of Schmitt Trigger Based SRAM Cell Using NBTI Technique M.Padmaja 1, N.V.Maheswara Rao 2 Post Graduate Scholar, Gayatri Vidya Parishad College of Engineering for Women, Affiliated to JNTU,
More informationCopyright 2007 Year IEEE. Reprinted from ISCAS 2007 International Symposium on Circuits and Systems, May This material is posted here
Copyright 2007 Year IEEE. Reprinted from ISCAS 2007 International Symposium on Circuits and Systems, 27-30 May 2007. This material is posted here with permission of the IEEE. Such permission of the IEEE
More informationImproved Pre-Sample pixel
Improved Pre-Sample pixel SUMMARY/DIALOGUE 2 PRESAMPLE PIXEL OVERVIEW 3 PRESAMPLE PIXEL SIMULATION: EXAMPLE OPERATION 4 PRESAMPLE PIXEL SIMULATION: SMALL SIGNALS AROUND THRESHOLD 6 PRESAMPLE PIXEL SIMULATION:
More informationAn ambient-light sensor system with startup. correction, LTPS TFT, LCD
LETTER IEICE Electronics Express, Vol.11, No.5, 1 7 An ambient-light sensor system with startup correction for LTPS-TFT LCD Ilku Nam 1 and Doohyung Woo 2a) 1 Dept of EE and also with PNU LG Smart Control
More informationStudies on MCM D interconnections
Studies on MCM D interconnections Speaker: Peter Gerlach Department of Physics Bergische Universität Wuppertal D-42097 Wuppertal, GERMANY Authors: K.H.Becks, T.Flick, P.Gerlach, C.Grah, P.Mättig Department
More informationARTICLE IN PRESS. Nuclear Instruments and Methods in Physics Research A
Nuclear Instruments and Methods in Physics Research A 614 (2010) 308 312 Contents lists available at ScienceDirect Nuclear Instruments and Methods in Physics Research A journal homepage: www.elsevier.com/locate/nima
More informationTL494 Pulse - Width- Modulation Control Circuits
FEATURES Complete PWM Power Control Circuitry Uncommitted Outputs for 200 ma Sink or Source Current Output Control Selects Single-Ended or Push-Pull Operation Internal Circuitry Prohibits Double Pulse
More informationAn 11 Bit Sub- Ranging SAR ADC with Input Signal Range of Twice Supply Voltage
D. Aksin, M.A. Al- Shyoukh, F. Maloberti: "An 11 Bit Sub-Ranging SAR ADC with Input Signal Range of Twice Supply Voltage"; IEEE International Symposium on Circuits and Systems, ISCAS 2007, New Orleans,
More informationKLauS4: A Multi-Channel SiPM Charge Readout ASIC in 0.18 µm UMC CMOS Technology
1 KLauS: A Multi-Channel SiPM Charge Readout ASIC in 0.18 µm UMC CMOS Technology Z. Yuan, K. Briggl, H. Chen, Y. Munwes, W. Shen, V. Stankova, and H.-C. Schultz-Coulon Kirchhoff Institut für Physik, Heidelberg
More informationFractional- N PLL with 90 Phase Shift Lock and Active Switched- Capacitor Loop Filter
J. Park, F. Maloberti: "Fractional-N PLL with 90 Phase Shift Lock and Active Switched-Capacitor Loop Filter"; Proc. of the IEEE Custom Integrated Circuits Conference, CICC 2005, San Josè, 21 September
More informationRESISTOR-STRING digital-to analog converters (DACs)
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 53, NO. 6, JUNE 2006 497 A Low-Power Inverted Ladder D/A Converter Yevgeny Perelman and Ran Ginosar Abstract Interpolating, dual resistor
More informationA PIPELINE VOLTAGE-TO-TIME CONVERTER FOR HIGH RESOLUTION SIGNAL EXTRACTION OFF-CHIP
A PIPELINE VOLTAGE-TO-TIME CONVERTER FOR HIGH REOLUTION IGNAL EXTRACTION OFF-CHIP John Hogan *, Ronan Farrell Department of Electronic Engineering National University of Ireland, Maynooth * jhogan@eeng.may.ie,
More informationECEN689: Special Topics in Optical Interconnects Circuits and Systems Spring 2016
ECEN689: Special Topics in Optical Interconnects Circuits and Systems Spring 2016 Lecture 10: Electroabsorption Modulator Transmitters Sam Palermo Analog & Mixed-Signal Center Texas A&M University Announcements
More informationA CMOS CURRENT CONTROLLED RING OSCILLATOR WITH WIDE AND LINEAR TUNING RANGE
A CMOS CURRENT CONTROLLED RING OSCILLATOR WI WIDE AND LINEAR TUNING RANGE Abstract Ekachai Leelarasmee 1 1 Electrical Engineering Department, Chulalongkorn University, Bangkok 10330, Thailand Tel./Fax.
More informationHigh-Speed Serial Interface Circuits and Systems
High-Speed Serial Interface Circuits and Systems Design Exercise4 Charge Pump Charge Pump PLL ɸ ref up PFD CP LF VCO down ɸ out ɸ div Divider Converts PFD phase error pulse (digital) to charge (analog).
More informationMultivibrators. Department of Electrical & Electronics Engineering, Amrita School of Engineering
Multivibrators Multivibrators Multivibrator is an electronic circuit that generates square, rectangular, pulse waveforms. Also called as nonlinear oscillators or function generators. Multivibrator is basically
More informationAN increasing number of video and communication applications
1470 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 9, SEPTEMBER 1997 A Low-Power, High-Speed, Current-Feedback Op-Amp with a Novel Class AB High Current Output Stage Jim Bales Abstract A complementary
More informationHIGH LOW Astable multivibrators HIGH LOW 1:1
1. Multivibrators A multivibrator circuit oscillates between a HIGH state and a LOW state producing a continuous output. Astable multivibrators generally have an even 50% duty cycle, that is that 50% of
More informationHigh Speed Analog CMOS Pipeline System for the Recording of Fast Signals from Cherenkov Telescopes
High Speed Analog COS Pipeline System for the Recording of Fast Signals from Cherenkov Telescopes CRISTIAN CHIŢU ; and WERNER HOFANN ASIC Labor Universität Heidelberg Schröderstr.90, D-690Heidelberg ax-planck-institut
More informationDesigning Of A New Low Voltage CMOS Schmitt Trigger Circuit And Its Applications on Reduce Power Dissipation
IJISET - International Journal of Innovative Science, Engineering & Technology, Vol. Issue 1, December 015. www.ijiset.com ISSN 348 7968 Designing Of A New Low Voltage CMOS Schmitt Trigger Circuit And
More informationA 3-10GHz Ultra-Wideband Pulser
A 3-10GHz Ultra-Wideband Pulser Jan M. Rabaey Simone Gambini Davide Guermandi Electrical Engineering and Computer Sciences University of California at Berkeley Technical Report No. UCB/EECS-2006-136 http://www.eecs.berkeley.edu/pubs/techrpts/2006/eecs-2006-136.html
More informationIntroduction to IC-555. Compiled By: Chanakya Bhatt EE, IT-NU
Introduction to IC-555 Compiled By: Chanakya Bhatt EE, IT-NU Introduction SE/NE 555 is a Timer IC introduced by Signetics Corporation in 1970 s. It is basically a monolithic timing circuit that produces
More informationECEN 474/704 Lab 5: Frequency Response of Inverting Amplifiers
ECEN 474/704 Lab 5: Frequency Response of Inverting Amplifiers Objective Design, simulate and layout various inverting amplifiers. Introduction Inverting amplifiers are fundamental building blocks of electronic
More informationSimulation of Charge Sensitive Preamplifier using Multisim Software
International Journal of Current Engineering and Technology E-ISSN 2277 4106, P-ISSN 2347 5161 2015 INPRESSCO, All Rights Reserved Available at http://inpressco.com/category/ijcet Research Article Niharika
More informationA High Speed CMOS Current Comparator in 90 nm CMOS Process Technology
A High Speed CMOS Current Comparator in 90 nm CMOS Process Technology Adyasha Rath 1, Sushanta K. Mandal 2, Subhrajyoti Das 3, Sweta Padma Dash 4 1,3,4 M.Tech Student, School of Electronics Engineering,
More informationACURRENT reference is an essential circuit on any analog
558 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 2, FEBRUARY 2008 A Precision Low-TC Wide-Range CMOS Current Reference Guillermo Serrano, Member, IEEE, and Paul Hasler, Senior Member, IEEE Abstract
More informationUniversity of California at Berkeley Donald A. Glaser Physics 111A Instrumentation Laboratory
Published on Instrumentation LAB (http://instrumentationlab.berkeley.edu) Home > Lab Assignments > Digital Labs > Digital Circuits II Digital Circuits II Submitted by Nate.Physics on Tue, 07/08/2014-13:57
More informationPARTICLE DETECTORS (V): ELECTRONICS
Monday, April 13, 2015 1 PARTICLE DETECTORS (V): ELECTRONICS Zhenyu Ye April 13, 2015 Monday, April 13, 2015 2 References Techniques for Nuclear and Particle Physics Experiments by Leo, Chapter 15-17 Particle
More informationRECENTLY, low-voltage and low-power circuit design
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 55, NO. 4, APRIL 2008 319 A Programmable 0.8-V 10-bit 60-MS/s 19.2-mW 0.13-m CMOS ADC Operating Down to 0.5 V Hee-Cheol Choi, Young-Ju
More informationA radiation-hardened optical receiver chip
This article has been accepted and published on J-STAGE in advance of copyediting. Content is final as presented. A radiation-hardened optical receiver chip Xiao Zhou, Ping Luo a), Linyan He, Rongxun Ling
More informationA Variable-Frequency Parallel I/O Interface with Adaptive Power Supply Regulation
WA 17.6: A Variable-Frequency Parallel I/O Interface with Adaptive Power Supply Regulation Gu-Yeon Wei, Jaeha Kim, Dean Liu, Stefanos Sidiropoulos 1, Mark Horowitz 1 Computer Systems Laboratory, Stanford
More informationDESIGN OF MULTIPLYING DELAY LOCKED LOOP FOR DIFFERENT MULTIPLYING FACTORS
DESIGN OF MULTIPLYING DELAY LOCKED LOOP FOR DIFFERENT MULTIPLYING FACTORS Aman Chaudhary, Md. Imtiyaz Chowdhary, Rajib Kar Department of Electronics and Communication Engg. National Institute of Technology,
More informationEECS3611 Analog Integrated Circuit Design. Lecture 3. Current Source and Current Mirror
EECS3611 Analog ntegrated Circuit Design Lecture 3 Current Source and Current Mirror ntroduction Before any device can be used in any application, it has to be properly biased so that small signal AC parameters
More informationResults of FE65-P2 Pixel Readout Test Chip for High Luminosity LHC Upgrades
for High Luminosity LHC Upgrades R. Carney, K. Dunne, *, D. Gnani, T. Heim, V. Wallangen Lawrence Berkeley National Lab., Berkeley, USA e-mail: mgarcia-sciveres@lbl.gov A. Mekkaoui Fermilab, Batavia, USA
More informationCMOS Detectors Ingeniously Simple!
CMOS Detectors Ingeniously Simple! A.Schöning University Heidelberg B-Workshop Neckarzimmern 18.-20.2.2015 1 Detector System on Chip? 2 ATLAS Pixel Module 3 ATLAS Pixel Module MCC sensor FE-Chip FE-Chip
More information