2N6400 Series. Silicon Controlled Rectifiers. Reverse Blocking Thyristors. SCRs 16 AMPERES RMS 50 thru 800 VOLTS
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1 Silicon Controlled Rectifiers Reverse Blocking Thyristors Designed primarily for half-wave ac control applications, such as motor controls, heating controls and power supplies; or wherever halfwave silicon gatecontrolled, solidstate devices are needed. Features Glass Passivated Junctions with Center Gate Geometry for Greater Parameter Uniformity and Stability Small, Rugged, Thermowatt Construction for Low Thermal Resistance, High Heat Dissipation and Durability Blocking Voltage to 800 V These are PbFree Devices SCRs 6 AMPERES RMS thru 800 VOLTS A G K MAXIMUM RATINGS* (T J = 25 C unless otherwise noted) Rating Symbol Value Unit Peak Repetitive OffState Voltage (Note ) (T J = 40 to 25 C, Sine Wave to 60 Hz; Gate Open) 2N6400 2N640 2N6402 2N6403 2N6404 2N6405 V DRM, V RRM V 4 TO220AB CASE 22A STYLE 3 MARKING DIAGRAM 2N640xG AYWW On-State Current RMS (80 Conduction Angles; T C = C) I T(RMS) 6 A 2 3 Average On-State Current (80 Conduction Angles; T C = C) Peak Non-repetitive Surge Current (/2 Cycle, Sine Wave 60 Hz, T J = 25 C) I T(AV) A I TSM 60 A Circuit Fusing Considerations (t = 8.3 ms) I 2 t 45 A 2 s Forward Peak Gate Power (Pulse Width s, T C = C) Forward Average Gate Power (t = 8.3 ms, T C = C) Forward Peak Gate Current (Pulse Width s, T C = C) P GM 20 W P G(AV) 0.5 W I GM A Operating Junction Temperature Range T J 40 to +25 Storage Temperature Range T stg 40 to + Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.. V DRM and V RRM for all types can be applied on a continuous basis. Ratings apply for zero or negative gate voltage; however, positive gate voltage shall not be applied concurrent with negative potential on the anode. Blocking voltages shall not be tested with a constant current source such that the voltage ratings of the devices are exceeded. C C 2 3 x = 0,, 2, 3, 4 or 5 A = Assembly Location Y = Year WW = Work Week G = PbFree Package PIN ASSIGNMENT Cathode Anode Gate 4 Anode ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. Semiconductor Components Industries, LLC, 202 November, 202 Rev. 6 Publication Order Number: 2N6400/D
2 THERMAL CHARACTERISTICS Characteristic Symbol Max Unit Thermal Resistance, JunctiontoCase R JC.5 C/W Maximum Lead Temperature for Soldering Purposes /8 in from Case for Seconds T L 260 C ELECTRICAL CHARACTERISTICS (T C = 25 C unless otherwise noted.) Characteristic Symbol Min Typ Max Unit OFF CHARACTERISTICS * Peak Repetitive Forward or Reverse Blocking Current (V AK = Rated V DRM or V RRM, Gate Open) T J = 25 C T J = 25 C ON CHARACTERISTICS *Peak Forward OnState Voltage (I TM = 32 A Peak, Pulse Width ms, Duty Cycle 2%) V TM.7 V * Gate Trigger Current (Continuous dc) T C = 25 C I GT ma (V D = 2 Vdc, R L = ) T C = 40 C 60 * Gate Trigger Voltage (Continuous dc) (V D = 2 Vdc, R L = ) T C = 25 C T C = 40 C Gate NonTrigger Voltage (V D = 2 Vdc, R L = ), T C = +25 C V GD 0.2 V * Holding Current T C = 25 C I H 8 40 ma (V D = 2 Vdc, Initiating Current = 200 ma, Gate Open) *T C = 40 C 60 Turn-On Time (I TM = 6 A, I GT = 40 madc, V D = Rated V DRM ) t gt s Turn-Off Time (I TM = 6 A, I R = 6 A, V D = Rated V DRM ) t q s T C = 25 C T J = +25 C 5 35 DYNAMIC CHARACTERISTICS Critical RateofRise of Off-State Voltage (V D = Rated V DRM, Exponential Waveform) T J = +25 C *Indicates JEDEC Registered Data. I DRM, I RRM V GT A ma dv/dt V/ s V 2
3 Voltage Current Characteristic of SCR + Current Anode + Symbol V DRM I DRM V RRM I RRM V TM I H Parameter Peak Repetitive Off State Forward Voltage Peak Forward Blocking Current Peak Repetitive Off State Reverse Voltage Peak Reverse Blocking Current Peak On State Voltage Holding Current I RRM at V RRM on state Reverse Blocking Region (off state) Reverse Avalanche Region V TM I H + Voltage I DRM at V DRM Forward Blocking Region (off state) Anode T C, MAXIMUM CASE TEMPERATURE ( C) α α = CONDUCTION ANGLE 4 α = I T(AV), AVERAGE ON STATE FORWARD CURRENT (AMPS) dc P (AV), AVERAGE POWER (WATTS) T J 25 C α = 30 α α = CONDUCTION ANGLE I T(AV), AVERAGE ON STATE FORWARD CURRENT (AMPS) dc Figure. Average Current Derating Figure 2. Maximum OnState Power Dissipation 3
4 i TM, INSTANTANEOUS ON-STATE FORWARD CURRENT (AMPS) T J = 25 C 25 C v TM, INSTANTANEOUS ON-STATE VOLTAGE (VOLTS) Figure 3. OnState Characteristics I TSM, PEAK SURGE CURRENT (AMP) T J = 25 C f = 60 Hz SURGE IS PRECEDED AND FOLLOWED BY RATED CURRENT NUMBER OF CYCLES CYCLE Figure 4. Maximum NonRepetitive Surge Current r(t), TRANSIENT THERMAL RESISTANCE (NORMALIZED) Z JC(t) = R JC r(t) k k 3.0 k 5.0 k k t, TIME (ms) Figure 5. Thermal Response 4
5 TYPICAL CHARACTERISTICS, PEAK GATE CURRENT (ma) i GT OFF STATE VOLTAGE = 2 V R L = T J = -40 C 25 C 25 C, GATE TRIGGER CURRENT (ma) I GT PULSE WIDTH (ms) T J, JUNCTION TEMPERATURE ( C) Figure 6. Typical Gate Trigger Current versus Pulse Width Figure 7. Typical Gate Trigger Current versus Junction Temperature, GATE TRIGGER VOLTAGE (VOLTS) I H, HOLDING CURRENT (ma) VGT T J, JUNCTION TEMPERATURE ( C) T J, JUNCTION TEMPERATURE ( C) Figure 8. Typical Gate Trigger Voltage versus Junction Temperature Figure 9. Typical Holding Current versus Junction Temperature 5
6 ORDERING INFORMATION 2N6400G Device Package Shipping TO220AB (PbFree) 2N640G 2N6402G 2N6403G 2N6403TG 2N6404G 2N6405G TO220AB (PbFree) TO220AB (PbFree) TO220AB (PbFree) TO220AB (PbFree) TO220AB (PbFree) TO220AB (PbFree) 0 Units / Box Units / Rail 0 Units / Box 6
7 PACKAGE DIMENSIONS TO220 CASE 22A07 ISSUE O H Q Z L V G B N D A K F T U C T SEATING PLANE S R J NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y4.5M, CONTROLLING DIMENSION: INCH. 3. DIMENSION Z DEFINES A ZONE WHERE ALL BODY AND LEAD IRREGULARITIES ARE ALLOWED. INCHES MILLIMETERS DIM MIN MAX MIN MAX A B C D F G H J K L N Q R S T U V Z STYLE 3: PIN. CATHODE 2. ANODE 3. GATE 4. ANODE ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC s product/patent coverage may be accessed at SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 563, Denver, Colorado 8027 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative 2N6400/D
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Preferred Device Darlington Complementary Silicon Power Transistors This package is designed for generalpurpose amplifier and low frequency switching applications. Features High DC Current Gain h FE =
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MBRM12ET1G, NRVBM12ET1G, MBRM12ET3G, NRVBM12ET3G Surface Mount Schottky Power Rectifier Power Surface Mount Package The Schottky employs the Schottky Barrier principle with a barrier metal and epitaxial
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