OBSOLETE. Four-Channel, Four-Quadrant Analog Multiplier MLT04 REV. B. Figure 1. Gain & Phase vs. Frequency Response

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1 THD NOISE % a FEATURES Four Independent Channels Voltage IN, Voltage OUT No External Parts Required 8 MHz Bandwidth Four-Quadrant Multiplication Voltage Output; W = (X Y)/.5 V.% Typical Linearity Error on X or Y Inputs Excellent Temperature Stability:.5% ±.5 V Analog Input Range Operates from ±5 upplies Low Power Dissipation: 5 mw typ Spice Model Available APPLICATIONS Geometry Correction in High-Resolution CRT Displays Waveform Modulation & Generation Voltage Controlled Amplifiers Automatic Gain Control Modulation and Demodulation GENERAL DESCRIPTION The MLT is a complete, four-channel, voltage output analog multiplier packaged in an 8-pin DIP or SOIC-8. These complete multipliers are ideal for general purpose applications such as voltage controlled amplifiers, variable active filters, zipper noise free audio level adjustment, and automatic gain control. Other applications include cost-effective multiple-channel power calculations (I V), polynomial correction generation, and low frequency modulation. The MLT multiplier is ideally suited for generating complex, high-order waveforms especially suitable for geometry correction in high-resolution CRT display systems. Av GAIN db V CC = 5V V EE = 5V X & Y MEASUREMENTS SUPERIMPOSED: X = mv RMS, Y =.5V DC Y = mv RMS, X =.5V DC Four-Channel, Four-Quadrant Analog Multiplier MLT FUNCTIONAL BLOCK DIAGRAM 8-Lead Epoxy DIP (P Suffix) 8-Lead Wide Body SOIC (S Suffix) Fabricated in a complementary bipolar process, the MLT includes four -quadrant multiplying cells which have been lasertrimmed for accuracy. A precision internal bandgap reference normalizes signal computation to a. scale factor. Drift over temperature is under.5%/ C. Spot noise voltage of. µv/ Hz results in a THD Noise performance of.% (LPF = khz) for the lower distortion Y channel. The four 8 MHz channels consume a total of 5 mw of quiescent power. The MLT is available in 8-pin plastic DIP, and SOIC-8 surface mount packages. All parts are offered in the extended industrial temperature range ( C to 85 C).. W GND X Y V CC Y X GND W V CC = 5V V = 5V EE MLT- MLT W = (X Y)/.5V Av (X OR Y) Ø (X OR Y) 8.MHz db k k k M M M Ø Phase Degrees LPF = 5kHz THDX: X =.5VP, Y =.5V DC THDY: Y =.5VP, X =.5V DC. k k k M W GND X Y V EE Y X GND W Figure. Gain & Phase vs. Frequency Response Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Figure. THD Noise vs. Frequency One Technology Way, P.O. Box, Norwood. MA -, U.S.A. Tel: 7/-7 Fax: 7/-87

2 MLT SPECIFICATIONS (V CC = 5 V, V EE = 5 V, = ±.5 V P, R L = kω, unless otherwise noted.) Parameter Symbol Conditions Min Typ Max Units MULTIPLIER PERFORMANCE Total Error X E X.5 V < X <.5 V, Y =.5 V 5 ± 5 % FS Total Error Y E Y.5 V < Y <.5 V, X =.5 V 5 ± 5 % FS Linearity Error X LE X.5 V < X <.5 V, Y =.5 V ±. % FS Linearity Error Y LE Y.5 V < Y <.5 V, X =.5 V ±. % FS Total Error Drift TCE X X =.5 V, Y =.5 V, = C to 85 C.5 %/ C Total Error Drift TCE Y Y =.5 V, X =.5 V, = C to 85 C.5 %/ C Scale Factor K X = ±.5 V, Y = ±.5 V, = C to 85 C.8.. /V Output Offset Voltage Z OS X = V, Y = V, = C to 85 C 5 ± 5 mv Output Offset Drift TCZ OS X = V, Y = V, = C to 85 C 5 µv/ C Offset Voltage, implied. X X OS X = V, Y = ±.5 V, = C to 85 C 5 ±.5 5 mv Offset Voltage, Y Y OS Y = V, X = ±.5 V, = C to 85 C 5 ±.5 5 mv DYNAMIC PERFORMANCE Small Signal Bandwidth BW UT =. V rms 8 MHz Slew Rate SR UT = ±.5 V 5 V/µs Settling Time t S UT =.5 V to % Error Band µs AC Feedthrough FC X = V, Y = V f = khz 5 db khz CC X = Y = V rms Applied to Adjacent Channel db OUTPUTS Audio Band Noise E N f = Hz to 5 khz 7 µv rms Wide Band Noise E N Noise BW =. MHz 8 µv rms Spot Noise Voltage e N f = khz. µv/ Hz Total Harmonic Distortion THD X f = khz, LPF = khz, Y =.5 V. % THD Y f = khz, LPF = khz, X =.5 V. % Open Loop Output Resistance R OUT Ω Voltage Swing V PK V CC = 5 V, V EE = 5 V ±. ±. V P Short Circuit Current I SC ma INPUTS Analog Input Range IVR GND = V.5.5 V Bias Current I B X = Y = V. µa Resistance R IN MΩ Capacitance C IN pf SQUARE PERFORMANCE Total Square Error E SQ X = Y = 5 % FS POWER SUPPLIES Positive Current I CC V CC = 5.5 V, V EE = 5.5 V 5 ma Negative Current I EE V CC = 5.5 V, V EE = 5.5 V 5 ma Power Dissipation P DISS Calculated = 5 V I CC 5 V I EE 5 mw Supply Sensitivity PSSR X = Y = V, V CC = 5% or V EE = 5% mv/v Supply Voltage Range V RANGE For V CC & V EE ±.75 ± 5.5 V NOTES Specifications apply to all four multipliers. Error is measured as a percent of the ±.5 V full scale, i.e., % FS = 5 mv. Scale Factor K is an internally set constant in the multiplier transfer equation W = K X Y. Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS* ORDERING INFORMATION* Supply Voltages V CC, V EE to GND ± 7 V Inputs X I, Y I V CC, V EE Temperature Package Package Outputs W I V CC, V EE Model Range Description Option section of this specification are not Operating Temperature Range C to 85 C MLTGP C to 85 C 8-Pin P-DIP N-8 Maximum Junction Temperature (T J max) 5 C MLTGS C to 85 C 8-Lead SOIC SOL-8 Storage Temperature 5 C to 5 C MLTGS-REEL C to 85 C 8-Lead SOIC SOL-8 Lead Temperature (Soldering, sec) C MLTGBC 5 C Die Package Power Dissipation (T J max )/θ JA Thermal Resistance θ JA PDIP-8 (N-8) 7 C/W *For die specifications contact your local Analog sales office. The MLT contains transistors. SOIC-8 (SOL-8) 8 C/W *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational

3 FUNCTIONAL DESCRIPTION The MLT is a low cost quad, -quadrant analog multiplier with single-ended voltage inputs and voltage outputs. The functional block diagram for each of the multipliers is illustrated in Figure. Due to packaging constraints, access to internal nodes for externally adjusting scale factor, output offset voltage, or additional summing signals is not provided. Figure. Functional Block Diagram of Each MLT Multiplier Each of the MLT s analog multipliers is based on a Gilbert cell multiplier configuration, a. V bandgap reference, and a unityconnected output amplifier. Multiplier scale factor is determined through a differential pair/trimmable resistor network external to the core. An equivalent circuit for each of the multipliers is shown in Figure. V CC INTERNAL BIAS X IN GND X, X, X, X G, G, G, G Y IN V EE Y, Y, Y, Y k µa µa. k Figure. Equivalent Circuit for the MLT Details of each multiplier s output-stage amplifier are shown in Figure 5. The output stages idles at µa, and the resistors in series with the emitters of the output stage are 5 Ω. The output stage can drive load capacitances up to 5 pf without oscillation. For loads greater than 5 pf, the outputs of the MLT should be isolated from the load capacitance with a Ω resistor. MLT k W, W, W, W µa µa µa µa SCALE FACTOR W OUT ANALOG MULTIPLIER ERROR SOURCES Multiplier errors consist primarily of input and output offsets, scale factor errors, and nonlinearity in the multiplying core. An expression for the output of a real analog multiplier is given by: = (K K){( X OS )( Y OS ) Z OS f (X, Y )} where: K = Multiplier Scale Factor K = Scale Factor Error = X-Input Signal X OS = X-Input Offset Voltage = Y-Input Signal Y OS = Y-Input Offset Voltage Z OS = Multiplier Output Offset Voltage ƒ(x, Y) = Nonlinearity MLT Executing the algebra to simplify the above expression yields expressions for all the errors in an analog multiplier: Term Description Dependence on Input K True Product Goes to Zero As Either or Both Inputs Go to Zero K Scale-Factor Error Goes to Zero at, = Y OS Linear X Feedthrough Proportional to Due to Y-Input Offset X OS Linear Y Feedthrough Proportional to Due to X-Input Offset X OS Y OS Output Offset Due to X-, Independent of, Y-Input Offsets Z OS Output Offset Independent of, ƒ(x, Y) Nonlinearity Depends on Both,. Contains Terms Dependent on,, Their Powers and Cross Products As shown in the table, the primary static errors in an analog multiplier are input offset voltages, output offset voltage, scale factor, and nonlinearity. Of the four sources of error, only two are externally trimmable in the MLT: the X- and Y-input offset voltages. Output offset voltage in the MLT is factory-trimmed to ±5 mv, and the scale factor is internally adjusted to ±.5% of full scale. Input offset voltage errors can be eliminated by using the optional trim circuit of Figure. This scheme then reduces the net error to output offset, scale-factor (gain) error, and an irreducible nonlinearity component in the multiplying core. V CC 5Ω 5Ω W OUT 5kΩ 5kΩ I ±mv FOR X, Y TRIM OS OS CONNECT TO SUM NODE OF AN EXT OP AMP Figure. Optional Offset Voltage Trim Configuration V EE Figure 5. Equivalent Circuit for MLT Output Stages

4 VERTICAL 5mV/DIV VERTICAL 5mV/DIV VERTICAL 5mV/DIV VERTICAL 5mV/DIV VERTICAL 5mV/DIV VERTICAL 5mV/DIV MLT Feedthrough In the ideal case, the output of the multiplier should be zero if either input is zero. In reality, some portion of the nonzero input will feedthrough the multiplier and appear at the output. This is caused by the product of the nonzero input and the offset voltage of the zero input. Introducing an offset equal to and opposite of the zero input offset voltage will null the linear component of the feedthrough. Residual feedthrough at the output of the multiplier is then irreducible core nonlinearity. Typical X- and Y-input feedthrough curves for the MLT are shown in Figures 7 and 8, respectively. These curves illustrate MLT feedthrough after zero input offset voltage trim. Residual X-input feedthrough measures.8% of full scale, whereas residual Y-input feedthrough is almost immeasurable. % Figure 7. X-Input Feedthrough with Y OS Nulled % X-INPUT: Hz Y OS NULLED HORIZONTAL.5V/DIV Y-INPUT: Hz X OS NULLED HORIZONTAL.5V/DIV Figure 8. Y-Input Feedthrough with X OS Nulled Nonlinearity Multiplier core nonlinearity is the irreducible component of error. It is the difference between actual performance and best-straightline theoretical output, for all pairs of input values. It is expressed as a percentage of full scale with all other dc errors nulled. Typical X- and Y-input nonlinearities for the MLT are shown in Figures through. Worst-case X-input nonlinearity measured less than.%, and Y-input nonlinearity measured better than.%. For modulator/demodulator or mixer applications it is, therefore, recommended that the carrier be connected to the X-input while the signal is applied to the Y-input. % X-INPUT: Hz Y-INPUT:.5V Y OS NULLED HORIZONTAL.5V/DIV Figure. X-Input Y =.5 V % X-INPUT: Hz Y-INPUT:.5V Y OS NULLED HORIZONTAL.5V/DIV Figure. X-Input Y =.5 V % Y-INPUT: Hz X-INPUT:.5V X OS NULLED HORIZONTAL.5V/DIV Figure. Y-Input X =.5 V % Y-INPUT: Hz X-INPUT:.5V X OS NULLED HORIZONTAL.5V/DIV Figure. Y-Input X =.5 V

5 NOISE DENSITY nv/ Hz AV GAIN db OUTPUT NOISE VOLTAGE 5µV/DIV OUTPUT NOISE VOLTAGE µv/div GAIN db PHASE Degrees Typical Performance Characteristics MLT = mv =.5V 8 5 NBW = Hz 5kHz GAIN 5 % Figure. Broadband Noise % TIME = ms/div TIME = ms/div NBW =.MHz Figure. Broadband Noise GAIN db PHASE PHASE = 7. MHz 8 k k M M Figure. X-Input Gain and Phase vs. Frequency Figure 7. Y-Input Gain and Phase vs. Frequency 8 8 R L = k NO C L C L = pf C L = pf C L = pf =.5V = mv GAIN PHASE C L = 5pF 5 5 PHASE = MHz 8 k k M M PHASE Degrees k k k M k k k M M M Figure 5. Noise Density vs. Frequency Figure 8. Amplitude Response vs. Capacitive Load 5

6 VERTICAL V/DIV AV GAIN db VERTICAL V/DIV CROSSTALK db VERTICAL 5mV/DIV FEEDTHROUGH db VERTICAL 5mV/DIV MLT Typical Performance Characteristics ΩX-INPUT =.5V R L = kω = V = V pk % 8 k 8 k k k = V = V pk M Figure. Feedthrough vs. Frequency k k = 5 C M Figure. Crosstalk vs. Frequency Y = mv RMS X =.5VDC X = mv RMS Y =.5VDC M = ±.5V pk =.5VDC Ω R L = kω M % TIME ns/div Figure. Y-Input Small-Signal Transient Response, C L = pf % TIME ns/div ΩX-INPUT:.5V R L = kω TIME = ns/div ΩX-INPUT =.5V R L = kω Figure. Y-Input Small-Signal Transient Response, C L = pf Figure. Y-Input Large-Signal Transient Response, C L = pf. k k k M M M Figure. Gain Flatness vs. Frequency % ΩX-INPUT:.5V R L = kω TIME = ns/div Figure 5. Y-Input Large-Signal Transient Response, C L = pf

7 db-bandwidth MHz db BW Degrees OUTPUT SWING Volts LINEARTY ERROR % THD NOISE % db-bandwidth MHz db BW Degrees MLT. X-INPUT Y =.5VDC 8 db BW =.5V = mv Ω R L = kω f O = khz FLPF = khz Y-INPUT X =.5VDC.. INPUT SIGNAL LEVEL Volts P-P Figure. THD Noise vs. Input Signal Level..... =.5V,.5V.5V =.5V,.5V.5V V s Figure 7. Linearity Error vs. Temperature 8 7 db BW db BW V S = mv =.5V Figure. Y-Input Gain Bandwidth vs. Temperature MAXIMUM OUTPUT SWING Volts p-p k db BW Figure. Maximum Output Swing vs. Frequency Ω R L = kω k POSITIVE SWING k % DISTORTION M NEGATIVE SWING M k k ΩLOAD RESISTANCE Ω Figure 8. X-Input Gain Bandwidth vs. Temperature Figure. Maximum Output Swing vs. Resistive Load 7

8 UNITS OUTPUT OFFSET VOLTAGE mv S mv UNITS UNITS SCALE FACTOR /V MLT 5 SS = MULTIPLIERS X = ±.5V.7. NO LOAD X Y = ±.5V Y X = ±.5V OFFSET VOLTAGE mv Figure. Offset Voltage Distribution Figure 5. Scale Factor vs. Temperature Y OS, X = ±.5V Figure. Offset Voltage vs. Temperature Figure. Output Offset Voltage (Z OS ) Distribution SS = MULTIPLIERS T A 5 SS = MULTIPLIERS = = V X OS, Y = ±.5V OUTPUT OFFSET VOLTAGE mv 5 5 V s SCALE FACTOR /V Figure. Scale Factor Distribution Figure 7. Output Offset Voltage (Z OS ) vs. Temperature 8 REV.B

9 LINEARITY ERROR % POWER SUPPLY REJECTION db SCALE FACTOR /V SUPPLY CURRENT ma OUTPUT VOLTAGE OFFSET mv MLT 7 NO LOAD = = 5 σx σ Figure 8. Supply Current vs. Temperature 8 k PSRR PSRR k k Figure. Power Supply Rejection vs. Frequency σx σ X M 5 8 HOURS OF OPERATION AT 5 C Figure. Output Voltage Offset (Z OS ) Distribution Accelerated by Burn-in.8 8 HOURS OF OPERATION AT 5 C Figure. Scale Factor (K) Distribution Accelerated by Burn-in X σx σ σx σ X σx σ.75. σx σ.5 8 HOURS OF OPERATION AT 5 C Figure. Linearity Error (LE) Distribution Accelerated by Burn-in

10 MLT APPLICATIONS The MLT is well suited for such applications as modulation/ demodulation, automatic gain control, power measurement, analog computation, voltage-controlled amplifiers, frequency doublers, and geometry correction in CRT displays. Multiplier Connections Figure llustrates the basic connections for multiplication. Each of the four independent multipliers has single-ended voltage inputs (X, Y) and a low impedance voltage output (W). Also, each multiplier has its own dedicated ground connection (GND) which is connected to the circuit s analog common. For best performance, circuit layout should be compact with short component leads and well-bypassed supply voltage feeds. In applications where fewer than four multipliers are used, all unused analog inputs must be returned to the analog common. 5V.µF W X Y Y X W W GND X W GND X 8 7 Y MLT Y V CC Y X V EE Y X 8 GND W GND W W =. (X Y ) Figure. Basic Multiplier Connections Squaring and Frequency Doubling As shown in Figure, squaring of an input signal,, is achieved by connecting the X-and Y-inputs in parallel to produce an output of /.5 V. The input may have either polarity, but the output will be positive. X GND Y. 5V 5V.µF / MLT.µF Figure. Connections for Squaring When the input is a sine wave given by sin ωt, the squaring circuit behaves as a frequency doubler because of the trigonometric identity: W W X Y Y X W.µF W =. 5V The equation shows a dc term at the output which will vary strongly with the amplitude of the input,. The output dc offset can be eliminated by capacitively coupling the MLT s output with a high-pass filter. For optimal spectral performance, the filter s cutoff frequency should be chosen to eliminate the input fundamental frequency. A source of error in this configuration is the offset voltages of the X and Y inputs. The input offset voltages produce cross products with the input signal to distort the output waveform. To circumvent this problem, Figure 5 illustrates the use of inverting amplifiers configured with an OP85 to provide a means by which the X- and Y-input offsets can be trimmed. ΩP 5kΩ 5V 5V X OS TRIM ΩR5 5kΩ R k R k A A, A = / OP85 5 A 7 R k R ΩR k 5kΩ Y OS TRIM 5V 5V ΩP 5kΩ Figure 5. Frequency Doubler with Input Offset Voltage Trims Feedback Divider Connections The most commonly used analog divider circuit is the inverted multiplier configuration. As illustrated in Figure, an inverted multiplier analog divider can be configured with a multiplier operating in the feedback loop of an operational amplifier. The general form of the transfer function for this circuit configuration is given by: =.5 V R R / MLT C pf. W ΩR L kω Here, the multiplier operates as a voltage-controlled potentiometer that adjusts the loop gain of the op amp relative to a control signal,. As the control signal to the multiplier decreases, the output of the multiplier decreases as well. This has the effect of reducing negative feedback which, in turn, decreases the amplifier s loop gain. The result is higher closed-loop gain and reduced circuit bandwidth. As is increased, the output of the multiplier increases which generates more negative feedback closed-loop gain drops and circuit bandwidth increases. An example of an inverted multiplier analog divider frequency response is shown in Figure 7. ( sin ωt ).5V = V IN.5V ( cos ωt )

11 GAIN db MLT W / MLT. X GND D N8 W / MLT. X R k R k OP =.5V Figure. Inverted-Multiplier Configuration for Analog Division =.5V =.5V =.5V A VOL OP Figure 7. Signal-Dependent Feedback Makes Variables Out of Amplifier Bandwidth and Stability Although this technique works well with almost any operational amplifier, there is one caveat: for best circuit stability, the unitygain crossover frequency of the operational amplifier should be equal to or less than the MLT s 8 MHz bandwidth. k k k M M Connection for Square Rooting Another application of the inverted multiplier configuration is the square-root function. As shown in Figure 8, both inputs of the MLT are wired together and are used as the output of the circuit. Because the circuit configuration exhibits the following generalized transfer function: Y R k R k = OP Voltage-Controlled Low-Pass Filter The circuit in Figure illustrates how to construct a voltagecontrolled low-pass filter with an analog multiplier. The advantage with this approach over conventional active-filter configurations is that the overall characteristic cut-off frequency, ω O, will be directly proportional to a multiplying input voltage. This permits the construction of filters in which the capacitors are adjustable (directly or inversely) by a control voltage. Hence, the frequency scale of a filter can be manipulated by means of a single voltage without affecting any other parameters. The general form of the circuit s transfer function is given by: = R R RR s.5rc R In this circuit, the ratio of R to R sets the passband gain, and the break frequency of the filter, ω LP, is given by: R V ω LP = X R R.5RC.5V X / MLT GND W. R k Y A C 8pF =.5 R R the input signal voltage is limited to the range.5 V <. To prevent circuit latchup due to positive feedback or input signal polarity reversal, a N8-type junction diode is used in series with the output of the multiplier. Figure 8. Connections for Square Rooting R k Y R k = V S 5RC IN f LP = ; f LP = =.5V ππrc A = / OP85 Figure. A Voltage-Controlled Low-Pass Filter For example, if R = R = kω, R = kω, and C = 8 pf,

12 GAIN db MLT then the output of the circuit has a pole at frequencies from khz to khz for ranging from 5 mv to.5 V. The performance of this low-pass filter is illustrated in Figure. OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 8-Lead Epoxy DIP (P Suffix) V =.5V.5V.5V X k k k M M Figure 5. Low-Pass Cutoff Frequency vs. Control Voltage, With this approach, it is possible to construct parametric biquad filters whose parameters (center frequency, passband gain, and Q) can be adjusted with dc control voltages. PIN. (5.) MAX. (.).5 (.) PIN 8. (.558). (.5).5 (.).85 (.7). (.5) BSC.8 (7.). (.) 8-Lead Wide-Body SOL (S Suffix) 8.5 (.75). (.5).8 (.).5 (.7). (.) BSC.7 (.77).5 (.5). (7.). (7.).5 (.8) MIN. (.) MIN SEATING PLANE. (.5).7 (.). (.5). (.5) 8. (.).5 (.).8 (.5). (.).5 (8.5). (7.) 5. (.7).8 (.5) x 5.5 (.8).8 (.).5 (.7).57 (.) PRINTED IN U.S.A. C85 8 /