DWM-PUF: A Low-Overhead, Memory-based Security Primitive

Transcription

1 DWM-PUF: A Low-Overhead, Memory-based Securiy Primiive Anirudh Iyengar Kenneh Ramclam Swaroop Ghosh Compuer Science and Engineering Compuer Science and Engineering Compuer Science and Engineering Universiy of Souh Florida Universiy of Souh Florida Universiy of Souh Florida anirudh@mail.usf.edu kramclam@mail.usf.edu sghosh@cse.usf.edu Absrac Physically Unclonable Funcion (PUF) is a securiy primiive o address hardware securiy issues such as chip auhenicaion, Inellecual Propery (IP) proecion ec. Convenional CMOS PUFs are buil on delay (inverer chains, scan chains ec.) or memory srucures (like SRAM). In his paper, we propose a novel PUF which works on he principles of spinronic Domain Wall Memory (DWM). Convenional DWM is limied by pinning due o process variaions induced surface roughness of he nanowire. We exploi his limiaion owards chip-auhenicaion. We propose wo flavors of PUFs namely relay-puf and memory-puf. The proposed PUFs show excellen enropy (measured by Hamming Disance). We also analyze merics such as robusness, area and power of he DWM-PUFs. The memory-puf indicaed up o an order of magniude reducion in power compared o SRAM PUF. Keywords Domain Wall Memory; Hardware Securiy; Physically Unclonable Funcion; Spinronic PUF; DWM-PUF. I. INTRODUCTION A. Physically Unclonable Funcions The manufacuring of he presen day inegraed circuis (IC) are mosly ousourced o exernal companies. Under his business model he design is exposed o ampering and cloning by he hird pary breaching he Inellecual Propery (IP). IC cloning also siphons off he economic benefis of he produc. Due o high ech faciliies employed by adversaries, isolaing he fake chips from he genuine ones is becoming increasingly difficul ask. Tradiionally, unique keys are generaed by he ICs for imporan applicaions such as IP securiy, couner-plagiarism ec. These keys are hen sored on he on-chip non-volaile memory ha is hough o be impervious o illegal access and duplicaion. However adversaries can decode he secre key hrough Reverse Engineering (RE). The duplicaed chip wih he key obained hrough RE canno be disinguished from genuine chip. In order o address hese issues an auxiliary circui i.e. Physically Unclonable Funcion (PUF) is incorporaed in he auhenic chips. PUFs are designed o exploi he physical properies of he chip (e.g., process) o generae is unique idenificaion key. PUF is unclonable as he duplicae of his circui will no provide he same idenificaion ag as original even if he ICs are funcionally idenical. PUFs work on he foundaion of challenge-response proocol, which funcions on he basis of complex and variable physical process. B. Types of PUFs PUFs fall under wo basic caegories: elecronic and nonelecronic [19]. Elecronic PUF s are based on elecronic properies ha deermine he challenge-response proocols, such as gae delay, hreshold volage swiching imes ec. The mos popular ones are: Arbier PUF [1-2], Ring Oscillaor PUF [1-4] and SRAM PUF [5]. The nano-elecronic PUFs e.g., memrisor based PUF [6-11] is also invesigaed due o is enhanced securiy feaure. The non-elecronic PUFs e.g., opical PUF, magneic PUF, and acousical PUF [19] use non-elecrical challenge-response mechanism for heir operaion. Convenional CMOS PUFs suffer from power, limied randomness offered by silicon subsrae and resriced number of challenge-response pairs. This brings he need o invesigae emerging echnologies such as memrisors, spinronic devices ec. The experimenal resuls on spin valves, magneic-unnel juncions (MTJ), domain wall memory (DWM) ec. [12-18] have creaed enormous ineres in spin based compuaions. The mos promising effec is curren induced modulaion of magneizaion dynamics discovered in MTJ and DWM as i opens door o energy-efficien logic and memory design. Ineracion beween injeced curren and local magneizaion creaes several Spin-Transfer Torque (STT) mechanisms ha are excellen sources of enropy in he magne. We noe ha he nonlinear dynamics of domain walls (DWs) in he physical magneic sysem can be leveraged for hardware securiy and auhenicaion. To he bes of our knowledge, his is he firs effor owards employing spinronics for designing PUFs. The primary conribuions of his paper are as follows: We provide analysis of DW pinning in he nanowire (NW) due o process variaions. We propose wo flavors of PUF models ha exploi DW pinning and offer higher degree of randomness. Our invesigaion revealed ha DWM PUF can be effecive in generaing unique idenificaion keys a he cos of low-power consumpion. We also propose novel approaches o expand challengeresponse pairs which are unique o DWM. The res of he paper is organized as follows. We describe he background on DWM and pinning effec in Secion II. The proposed PUF designs and simulaion resuls are described in Secion III. Conclusions are drawn in Secion IV. II. BASICS OF DWM In his Secion, we provide he basics DWM and he impac of process variaion on DW pinning. We also esablish he relaionship beween variaion induced pinning and PUF design. A. Brief Inroducion Magneic memory is promising due o is high-densiy, lowpower and non-volailiy. DWM is a flavor of magneic memory ha provides he above benefis due o is abiliy o sore muliple bis per bicell for high-densiy [12-14]. Addiionally, /14/$31. c 14 IEEE 154

2 (a) Righ Shif (RS) (b) Fig. 1. (a)schemaic of DWM and governing equaions and, (b) definiion of q &. i provides low sandby power (due o non-volailiy), fas access, good endurance and reenion [15]. DWM consiss of hree componens: (a) wrie head, (b) read head and, (c) magneic nanowire (Fig. 1(a)). The read and wrie heads are similar o convenional MTJ whereas NW holds he bis in erms of magneic polariy. The mos ineresing effec in he NW is he formaion of DW beween domains of opposie polariies. The dynamics of NW is governed by he dynamics of DW. The DWs can be shifed forward and backward by injecing charge curren from lef-shif (LS) and righ-shif (RS) conacs. In essence, he NW is analogous o a shif regiser. The new domains are injeced by firs pushing curren hrough shif conacs o move he bis in locksep fashion in order o bring he desired bi under wrie head. Nex spin polarized curren is injeced hrough wrie MTJ (using wbl and SL) in posiive or negaive direcion o wrie a 1 or (up-spin or down-spin) in he NW. Read is performed by bringing he desired bi under he read head using shif and sensing he resisance of MTJ formed by DW under he read head (using rbl). I can be noed ha his new access mechanism makes shifing of DWs criical o he funcionaliy of he memory. The robusness, speed and power consumpion of he memory has a significan dependency on DW dynamics. Various facors affec he DW moion such as shif curren magniude, phase and physical properies of he NW. The DW posiion and il angle is deermined by solving he Landau- Lifshiz Gilber (LLG) equaion which is a orque balancing equaion (Fig. 1(b)). Where and are uni vecors represening local magneic momen of DW and curren flow respecively, is he effecive field, is damping consan, is nonadiabaic spin orque ransfer erm and u is a scalar quaniy having he unis of velociy. Term u depends on he curren densiy J, he spin polarizaion P, sauraion magneizaion and Bohr Magneon as follows:, WL Read Biline (rbl) GND Read head (MTJ) q DW Wrie Biline (wbl) Wrie head (MTJ) Source Line (SL) Lef Shif (LS) Domain wall TABLE I. MAGNETIC CONSTANTS USED FOR DW DYNAMICS Parameer Value Varied (.1 -.2) Varied (. -.1) Bohr magneon( B) 9.27e -24 J/T M s 8e 5 A/m Exchange Consan (A) 1.3e -11 J/m. Lengh(l)/Widh(w)/Thickness() of NW 1e -6 m/1e -9 m/1e -9 m 1.76e 11 /G s Demagneizaion Field (Hk) 16~18 Oe. In he above expression, is reduced plank s consan, e is elecron charge and m e is elecron mass. The final expressions of moion are given by [17] Where, and are he ime derivaives of he domain wall posiion and il angle respecively. We model he posiion (q) and il angle () of DW using Verilog-A. Wih consans provided in Table 1. B. Process Variaion Modeling and Analysis Noe ha he above expressions don consider he effec of process variaion induced roughness of he NW on he DW dynamics. The variaions in he NW could creae unwaned physical noches ha could pin he DW or degrade is velociy. The magniude of pinning energy is dependen on noch dimensions (Fig. 2(a). We model he pinning energy as follows [16-17]: Where q pin is he pinning sie, V pin is he pinning poenial a ha paricular locaion and d is pinning widh. Muliple pinning sies are modeled by changing q pin accordingly. The LLG is solved wih he pinning sies in order o observe he impac of DW dynamics. In pracice, several echniques have been suggesed o miigae he effec of variaions []. However, we demonsrae ha i can be exploied o generae challenge-response pairs for auhenicaion. To undersand he impac of variaions we conduc wo experimens. Firs, we fix he pinning locaions (q 1, q 1/q 2 and q 1/q 2/q 3) and se he pinning poenial o be equal o J/m 3 [17]. This condiion is se o simulae he inenional pinning and depinning o sudy is impac on shif curren. Nex, we disribue he pinning poenial o wo and hree equal and smaller pinning sies o simulae he impac of uninenional noches due o process variaions. For simulaion we assume a NW lengh of 2um and fix he pinning sies a q 1=.5um, q 2=1um and q 3=1.5um (Fig. 2(a)). The pinning widh (d) is assumed o be 15nm. Fig. 2(b) shows he vs. q plo of DW (for pinning sie a q 1 and V pin=j/m 3 ) for hree differen magniudes of injeced shif currens. The DW 14 IEEE Inernaional Symposium on Hardware-Oriened Securiy and Trus (HOST) 155

3 l d Noch widh (d) Process Variaion q 1 q 2 q 3 n Noch deph (n) (deg) (a) (b) (c) (d) Fig. 2. Domain wall pinning: (a) nanowire wih pinning sies a q 1, q 2 and q 3. The noch deph and widh is d, n respecively. Modeling of process variaion in d, n is also shown, (b) vs. q plo of DW for pinning a q 1. The DW depins wih u=1m/s, (c) vs q of DW for one and wo noches wih Vpin = J/m 3 and wo noches wih V pin =1 J/m 3, (d) plo showing ransien velociy for one deep pinning and wo cases of shallow pinning. Here =.1, =.2 and =25nm is used. ges pinned in he firs wo cases (u=8m/s and 9m/s) bu dislodges successfully wih u=1m/s. This plo indicaes he need of higher curren (i.e., higher power) o dislodge he DW. Fig. 2(c) and (d) illusraes he resuls wih pinning a wo sies (a q 1, q 2, wih V pin1= V pin2=j/m 3 ). Wih u=1m/s he DW ges depinned from q 1 bu ges pinned a q 2. This indicaes ha velociy degradaion due o firs noch (even hough unpinned) can cause pinning in he nex noch. The same curren successfully dislodges wo noches of half he pinning poenial (i.e., V pin=1j/m 3 ). This is due o he locaion of pinning sies. If muliple noches are locaed close o each oher hey can pin he DW, due o DW velociy degradaion by he noches. If he new noch arrives before he full recovery of DW velociy from he previous noch hen i becomes prone o ge pinned. I can be observed ha he average velociy of he DW can be affeced significanly due o presence of uninenional variaion induced noches. In order o sudy he impac of variaions we firs model he relaionship beween depinning magneic field (H h) and is dependency on noch deph (n) for he NW [17,18,]. Nex we sudy he presence of single noch a q pin= under process variaion induced noch widh (d) and deph (n) flucuaions. The variaions in d and n is assumed o be Gaussian wih mean () and sigma () of ( d, d) = (, 6.66nm) and ( n, n) = (, 5nm). Supply volage of he shif circui is swep from o 3V and minimum volage o dislodge he DW is ploed in Fig. 3(a) for 1 runs of Mone Carlo simulaion. The unwaned pinning of DW is dominaed by he long ail of he disribuion which indicaes ha random process variaions can have a considerable impac on he velociy of DW. C. Relaionship beween DW Pinning and PUF Pinning of DW creaes randomness in he DW velociy ha can be exploied o generae auhenicaion key. The basic premise is o rigger a DW race beween NWs in he array. Due o variaion in speed he DWs will reach he read head a differen imes. If he read iming edge is fixed, some NWs will read and he ohers will read 1 a he end of shif and read operaion. This random paern in he DWM is used as he signaure (memory-puf). Process variaions being random and unique o every IC, he key generaed will vary die-o-die. The paern generaed hrough DW race is unclonable because of is Vs Q for one Pinning Sie U=8m/s -4 U=9m/s U=1m/s Q(Um) Psi(deg) Curren driven Variaion of Psi Vs Q U = 1m/s noch 1 Noch -3 1,2 = J/m 3 2 Noch 1 2" Noch 2 = 1J/m 3 3" Noches 2" Noch Q(Um) Time(ns) dependence on inheren process. The similar principle can also be used o creae a relay-puf. Fig. 3(b) shows he dependency of shif volage pulse widh and pulse magniude o dislodge he DW from hree differen pinning poenials. I is ineresing o observe ha a wider pulse can depin he DW wih smaller magniude of pulse. However as he pulse widh becomes narrower, he magniude of pulse needed o depin goes up. For he sake of clariy, pulse magniude for DC inpu condiion is also shown in x-axis. Noe ha here are wo condiions, volage magniude and pulse widh ha direcly affec he DW velociy. This provides us wo exra knobs (challenge) o manipulae he DW moion, hus, enabling us o use hese wo facors as challenges for our DWM-PUF. III. DMW-PUF In he previous secion we inroduced he basics of DW and he effecs of inenional and variaion induced pinning. In his secion, we explain he circui deails o design wo flavors of PUFs namely relay-puf and memory-puf. A. DWM Relay-PUF This is similar o an arbier based PUF, where we combine muliple dual NW sages wih a muxing circui in beween each sage o oggle pahs (Fig. 4). The DWs are firs nucleaed in all he NWs, and are raced agains each oher by he applicaion of shif curren. The swiching circuiry is used o oggle beween pahs in accordance o a challenge paern (selec signal). An arbier block is placed a he end o compare he arrival imes of he respecive DWs. More he number of sages, higher is he degree of randomness in he signaure. In he following Depinning Volage disribuion under Process Variaions 1 LOW 8 MEDIUM 6 HIGH 4 Velociy (m/s) Volage (V) Variaion of Velociy Vs Time Vpin 1 = Vpin 2" = 2X1 Vpin 3"= 3X667 Relaionship beween Pulse widh and Magniude 2.5 Vpin DC8 Pulse Duraion (ns) (a) (b) Fig. 3. (a) Disribuion of depinning volage under process variaion and, (b) dependence of shif pulse magniude on pulse duraion for differen amoun of pinning poenials. Volage (V) PINNING POTENTIAL DECREASES IEEE Inernaional Symposium on Hardware-Oriened Securiy and Trus (HOST)

4 DW Nucleaion Read Signal Challenge Pulse Widh Challenge Volage Levels Wrie Signal NW1 + - NW3 Arbier NW2 + - NW4 DW D W Challenge DW D W Fig. 4. Overview of he relay-puf comprising of muliple sages of parallel NWs, wrie and read heads, sensing circuiry, swiching block and an arbier. paragraphs, we provide a deailed explanaion of he DWM relay-puf. Challenge: In conras o convenional delay-puf where only muxing is used as challenge, he relay-puf also provides wo addiional ses of challenges namely shif pulse magniude (PM) and pulse widh (PW). These new challenges can be employed o increase he size of challenge- response pairs wih low area overhead. This is mainly due o he fac ha less number of sages can generae large se of challenge-response pairs by mixing differen challenges. DW nucleaion and relay race: Each NW has fixed dimension. In order o obain adequae amoun of randomness, a long chain of such NWs are used. Firs he DWs are nucleaed in all he NWs by applying a pulsed (+ & -) curren and acivaing he wrie word line (wwl). Nex, he shif signal of sage-1 is acivaed ha riggers he DW race in wo parallel pahs. The read head is acivaed by pulsing he read word line (rwl). As soon as he resisance sensed by he read head changes, he shifing of he curren sage is sopped and he shif signal of he following sage is fired. Hence he DW race is relayed o he nex sage. This is idenical o signal propagaion in delay-puf. The mux selec deermines wheher he upper or lower DW will be fired in he following sage. The sequence of evens is illusraed in Fig. 5. Response: The response of he relay-puf is deermined by an arbier ha decides he early arrival of DWs in parallel NWs. If he op (boom) DW reaches firs he response of he PUF is (1). The NW-NW variaion of size and locaion of surface roughness affec he DW velociy increasing he randomness of he oucome of he race. Depending on he pah, a fas DW in one NW can ravel hrough a NW wih higher surface roughness slowing down is speed. On he conrary he slow DW can ravel hrough a smooher NW in he following sage increasing is speed. The response is also dependen on shif pulse challenges. Higher pulse widh and magniude will change he speed of DW and will increase he randomness in response. Simulaion Resuls: Firs we demonsrae he relay race beween wo DWs due o process variaions. For his simulaion we assume wo parallel NWs each conaining wo sages. The lengh of each NW is 2um and he process variaion is modeled by assuming hree pinning noches a.5um, 1um and 1.5um along he lengh of he NW. The values of pinning poenials are assumed o be 1, 75 and 5 J/m 3 for he op NW and 5, 75 and 1 J/m 3 for he boom NW. Fig. 6(a) shows he DW posiion in wo NWs w.r. ime. I can be observed ha DWs race a differen speeds due o difference in pinning poenials. The DW in he boom NW (i.e., NW2) arrives earlier han he op NW (i.e., NW1). The relay of he DWs from one sage o anoher hrough he challenge mux is shown in Fig. 6(b). NW1 finishes he race and he sense amplifier riggers he shifing of DW in NW3. A he end of race in second sage NW4 finishes much earlier ha NW3 due o cumulaive relay effec. Fig.6(c) shows he read head funcionaliy. The sense amplifier is designed o oupu a defaul high value. When he DW arrives he oupu is oggled o low. I can be observed ha RL2 oggles before RL1 indicaing early arrival of DW2. The nex sage oupus RL3 and RL4 ha oggle a he end of he race. Signal RL4 ransiions o a low value much before RL3 winning he race. I mus be noed ha, he behavior of his PUF can be alered by changing he challenge. For he deailed simulaion, we exend he relay-puf o a 2 parallel pah, 6 sage design. The oal number of challenges in his PUF is 2 5 i.e., 32. Therefore 32 differen pah combinaions are possible, which can rigger wwl Shif Signal Sage 1 Shif Signal Sage 2 rwl Vols Ohms Resisance Sensed by Read Head DW Nucleaion Relay Fig. 5. Timing diagram represening he wwl, he shif signals for each sage, he rwl and he variaion of resisance sensed by he read head. 14 IEEE Inernaional Symposium on Hardware-Oriened Securiy and Trus (HOST) 157

5 DW Time(ns) Nanowire Lengh(um) DW Time(ns) Challenge(Bi) (a) (b) (c) (d) Fig. 6. (a) Shows he NW race beween 2 NWs (NW1 & NW2), (b) he DW informaion being relayed o he nex NW sage (NW3 & NW4), (c) shows he sense amplifier oupu a he end of DW arrival a each sage. This is signal is acive low and riggers he race in he following sages and, (d) response of 6- sage relay-puf for 32 challenges for 32 differen dies. he race by producing a one bi response. As described in Secion II, process variaion wihin each NW can resul in differen pinning poenials for each noch. For his simulaion he pinning locaions in he NW is kep same as before. However he mean pinning poenial is assumed o be 5J/m 3 and a variaion of 15 J/m 3 (3 sigma) is added o model, o incorporae he effec of process variaion-induced pinning poenials. The relay-puf s responses for all 32 possible challenges are simulaed. Nex, new ses of process variaions are applied o he PUF o simulae iner-die responses. Fig. 6(d) shows he PUF response obained from 32 differen dies (y-axis) and 32 challenges (x-axis). I can be seen in he bi map ha process variaion wihin he nanowires can cause he arbier oupus o change. The challenge also riggers a change in he PUF response. The average die-o-die Hamming Disance (HD) is found o be 47%. B. Memory-PUF This PUF is similar o SRAM based PUF where he enire memory bank is poenially used o obain he auhenicaion key unique o he chip a hand. The DWs in all NWs in he memory banks are fired simulaneously. The race concludes when he read signal is assered. The DWs winning he race are se o 1 whereas he ohers are se o. In conras o relay-puf, his design does no require any circui overhead. Due o nonvolaile naure of he bicell his PUF is also low-power. Challenge: In conras o SRAM-PUF where he memory paern is solely dependen on power up and variaions, he DWM memory-puf depends on boh variaions and shif pulse characerisics (magniude and widh). The challenges are he address of he array wwl Shif Signal rwl Nanowire DW Race Vols Nanowire NW1 NW2 DW Time(ns) DW Nucleaion Mean Race Time Fig.7. Timing diagram represening he wwl, he shif signal and he rwl. 5 DW is relayed from NW1 o 4 NW3 o coninue race 3 1 Nanowire DW Relay Nanowire Lengh(um) Nanowire NW1 NW2 NW3 NW4 and shif pulse. DW nucleaion and race: Similar o relay-puf, firs a single DW is nucleaed in all NWs presen in he array (Fig. 7). Nex, he DWs are shifed/raced by a shif pulse challenge. The rwl is fired afer a conservaive ReadLine(V) 1 Nanowire DW Race ReadLine.5 RL1 RL2 RL3 RL DW Race Bi Map ime o screen he pinned DWs a he end of he race for deermining he oucome. Response: The response of his PUF is he oupu of he array when a cerain address is accessed for a paricular pulse seing. The value of he bicell is 1 ( ) if a high (low) resisance is read from he read head as discussed before. Simulaion Resuls: For his PUF flavor, we consider 1x1 array of DWM. The inra-die variaion is modeled by varying he pinning deph and widh as Gaussian disribuion wih ( d, d) o be (, 5nm) and ( n, n) o be (, 2nm). Three noches are assumed per NW a.5um, 1um, 1.5um. The pinning poenials are deermined from he noch dimensions. The simulaion a 1V shif pulse shows ha only 34 ou of 1 NWs ge he DWs pinned (Fig. 8(a)). Considering he fac ha he pinned DWs will resul in a response, his race condiion will produce uneven 1 s and s. In order o balance he and 1 we reduce he shif pulse volage, and noe ha shifing a.25v roughly produces 59% of 1 (i.e., he DWs ha win he race). By operaing he memory-puf a his volage, here is no need o correcly manage he reference read ime as he DWs ha ge pinned will always loose he race. The problem wih his mehod is is suscepibiliy o variaions in emperaure. The NWs resisance is direcly proporional o he increase in emperaure [17]. This impacs he amoun of shif curren and affecs he DW velociy. Fig. 8(b) shows he DW arrival ime disribuion a.25v for wo emperaures 25C and 125C. I can be observed ha high emperaure pins more DWs (49 vs 498) and changes he signaure of memory-puf. To mainain he PUF robusness we propose shif volage boos a high emperaure o negae he Occurrences Arrival ime disribuion V.25V.3V.4V.5V 1V 1.5V Arrival Time (ns) Arrival Time (ns) (a) (b) Fig. 8. Arrival ime disribuion for (a) differen shif volage seings a 25C and, (b) wo volages seings a 25C and 125C. The successful NWs and he oal number are also shown for 1 runs of Mone Carlo. Occurrences DW Race(PV) Arrival ime disribuion V-125C.25V-25C.286V-125C V-25C IEEE Inernaional Symposium on Hardware-Oriened Securiy and Trus (HOST)

6 Mean Velociy disribuion under PV 4 Fas Typical Velociy (m/s) Velociy (V) Velociy (V) Velociy (V) (a) (b) (c) (d) Fig. 9. (a) Velociy disribuion in he memory array for fas and ypical corners. A memory array bimap comprising of 1X1 bis showing, (b) fas corner, (c) ypical corner and, (d) differences in he signaure beween fas and ypical die. effec of exra DWs pinning. Our simulaion indicaes ha boosing by 36.2mV brings back he number of pinned DWs back o 48 a 125C. To analyze he die-o-die uniqueness in response we model he iner-die process corners (fas and ypical) by skewing he NW widh and hickness by a facor of 1% i.e. fas corner is (-1%, -1%). Fig. 9(a) shows he disribuion of velociy for ypical and fas corners. Again he reference is seleced o screen he pinned DWs for he wo corners. Fig. 9(b) shows he /1 paern obained for a fas NW. This paern or signaure is he device ideniy which varies from die-o-die. We compare he bi paern for he fas corner wih he ypical die. Fig. 9(c) shows he bimap paern for a ypical NW and, Fig. 9(d) shows he XORed paern for fas-ypical case. I is eviden ha he signaure differs from one anoher and ~44% Hamming disance is achieved. So far we have only described a NW wih one read and one wrie head. However, i is possible o have muliple read heads on a NW, which are individually seleced by a wordline (WL). This enables he use of he head selecion as anoher challenge ier. Applying his o our memory PUF based design, we can achieve a larger number of responses for he same size array or mainain he number of responses and reduce he size of he memory array. I is Breakeven poin >1X power reducion Fig. 1. Power vs # of heads for DW memory-puf. More han 1X power saving is possible compared o convenional SRAM-PUF imporan o noe ha he selecion of heads mus be done in an orderly fashion (i.e. head1- head2-head3 ) o avoid he need o rese he DWs before every analysis. Addiionally, since he shif power is dependen on he lengh of he NW, he use of muliple heads in he NW (Fig. 1) will dramaically reduce he power consumed. By increasing he number of heads, a power reducion of ~1X over SRAM can be achieved for he same number of challenge response pairs. IV. CONCLUSIONS Memory map for a Fas Chip under PV We presened he applicaion of spinronics for hardware securiy and auhenicaion. Two novel spinronic PUFs were Memory map for a Typical Chip under PV described namely; relay-puf and memory-puf. Boh PUFs exploi he process variaion induced DW pinning and slowdown o generae he response. The proposed designs provide addiional knobs e.g., shif pulse, number of access pors o expand he se of challenge-response pairs. Due o nonvolaile naure of he srucure, he proposed memory PUF is low-power compared o SRAM PUF. V. ACKNOWLEDGEMENTS This paper is based on work suppored by Semiconducor Research Corporaion (#2442.1). VI. REFERENCES XORed Fas and Typical bi map [1] B. Gassend e al. Idenificaion and Auhenicaion of Inegraed Circuis Concurrency and Compuaion: Pracice and Experience, 4. [2] J. W. Lee e al. A Technique o Build a Secre Key in Inegraed Circuis for Idenificaion and Auhenicaion Applicaion, VLSIC, 4 [3] B. Gassend e al. Physical Random Funcions, M.S. hesis, Massachuses Insiue of Technology (MIT), 3. [4] B. Gassend, e al. Silicon Physical Random Funcions, CCS, 2. [5] J. Guajardo, e al. FPGA Inrinsic PUFs and Their Use for IP Proecion, CHES, 7. [6] S. Garre e al., "Nanoelecronics and Hardware Securiy." NSC, 14. [7] S. Garre e al., "Foundaions of memrisor based PUF archiecures." NANOARCH, 13. [8] S. Garre e al.,"hardware securiy sraegies exploiing nanoelecronic circuis." ASP-DAC, 13. [9] R. Karri e al. "Nano-PPUF: A Memrisor-based Securiy Primiive." ISVLSI, 12. [1] J. Rajendran e al. "Nanoelecronic Soluions for Hardware Securiy." IACR, 12. [11] S. Garre e al. "A wrie-ime based memrisive PUF for hardware securiy applicaions." ICCAD, 13. [12] S. Parkin, e al. "Magneic domain -wall racerack memory." Science, 8. [13] S. Ghosh, "Pah o a TeraBye of on-chip memory for peabi per second bandwidh wih< 5was of power." DAC, 13. [14] A. J. Annunziaa e al., Racerack memory cell array wih inegraed magneic unnel juncion readou, IEDM 11. [15] M. Kryder e al., Afer hard drives wha comes nex?, TMag, 9. [16] A. Thiaville, e al. "Domain-Wall Dynamics in Nanowires and Nanosrips." Spin dynamics in confined magneic srucures III, 6. [17] M. Hayashi, "Curren driven dynamics of magneic domain walls in permalloy nanowires." PhD diss., Sanford Universiy, 6. [18] T. Suzuki, e al. "Analysis of curren-driven domain wall moion from pinning sies in nanosrips wih perpendicular magneic anisoropy." JAP, 8 [19] hp://rijndael.ece.v.edu/puf/background.hml [] A. Iyengar e. al., Modeling and analysis of domain wall dynamics for robus and low-power embedded memory, DAC, IEEE Inernaional Symposium on Hardware-Oriened Securiy and Trus (HOST) 159