Implementing a Voltage Scaling Reference Flow Based on ARM s IEM. Giorgio Parapini Cadence ICD Product Engineer
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1 Implementing a Voltage Scaling Reference Flow Based on ARM s IEM Giorgio Parapini Cadence ICD Product Engineer
2 Abstract Relative to ARM's IEM technology, this session describes a reference flow to implement voltage scaling along with dormant mode to shutdown the standard cell circuitry on an ARM1176JZF-S processor core. We focus on the low power features leveraged from Cadence Encounter Platform, including multiple supply voltage, DVFS implementation with multi-corner libraries, and variable VDD and ECSM-based sign-off. The entire flow is based on a single specification of the design power intent, including power domains, power modes, level shifting and isolation rules. This session also helps attendees understand RTL and library support required for IEM implementation.
3 Agenda ARM and Cadence Collaboration irm ARM1176JZF-S IEM ARM Artisan Library Support ARM1176JZF-S IEM implementation flow using Cadence Encounter Platform Conclusion
4 ARM and Cadence Collaboration
5 ARM Alliance ARM and Cadence Alliance History Multi-year partnership to: Address design challenges Optimize ARM offerings for design and implementation Increase productivity and IP use predictability June 00 June 03 Sept 03 Mar 05/ June 06 Sept 06 May 06 Nov 07 May 07 Verification AHB, evc, and AMBA compliance System C SI & X Architecture Support 27% Wire reduction Encounter and RTL Compiler Reference Methodology Improved QoS Low Power 40% PWR & PSO savings Functional Verification Kit Reduced Risks Cortex-A8 Express Synthesizable QoS And TAT PFI Silicon Proof Point Silicon Validated low power flow Low Power Methodology Kit Faster deployment of low power flows
6 irm
7 ARM-Cadence Reference Methodology Scripted RTL to GDSII flow delivers Optimised PPA Reduced Turnaround Time Risk/Cost reduction Key elements Core hardening Generation of abstract models Available from ARM Jointly developed flows Qualified/released with cores Design kit gives complete outof-box experience Performance Max Attainable Performance ARM-Cadence Solution Proprietary Solutions Faster Time To Market Time
8 Cadence irms Available For All ARM Processors Processor Tier Encounter ARM Library (TSMC) ARM1176JZF-S IEM CPF Metro 130LP CORTEX-R4[F] Advantage 90G ARM11 MPCORE Advantage 90G CORTEX-A Advantage 90G, 65LP CORTEX-R Advantage 90G CORTEX-M Advantage 90G ARM1176JZ[F]-S Advantage 90G ARM926EJ-S Advantage 90G ARM1156J[F]-S SageX 130G ARM1136J[F]-S SageX 130G ARM968E-S SageX 130G ARM1026EJ-S SageX 130G ARM966E-S SageX 130G ARM946E-S SageX 130G ARM7TDMI-S SageX 130G ARM7EJ-S SageX 130G
9 ARM1176JZF-S IEM
10 What Consumers Care About Users want more features in their mobile devices MP3, Camera, Video, GPS... But also need long battery life Convenient form factor, affordable price Heart of all these devices - Microprocessor Battery technology is not evolving fast enough! Need to manage power consumption
11 Power Dissipation E t = ( CV 0 2 DD f + V I ) dt c Total Total Power Dissipation DD lkg t 0 V DD I leak dt Static Power Dissipation Dynamic Power Dissipation t 0 CV 2 DD f c dt Minimise I leak by: Reducing operating voltage Fewer leaking transistors I leak I switch Minimise I switch by: Reducing operating voltage Less switching cap Less switching activity
12 Improving Dynamic Energy Efficiency Dynamic Frequency Scaling (DFS) Reduce operating frequency if possible Reduces average power (but not task energy) Eliminates idle cycle Dynamic Voltage & Frequency Scaling (DVFS) Requires DFS Reduces voltage if frequency is reduced Reduces task energy Based on characterized frequency voltage pairs (lookup table)
13 How IEM Works? Batteries have finite amounts of energy stored in them Running fast and then idling wastes energy Voltage Reduce Voltage Reduce Voltage Reduce Voltage Energy Energy Saved Run Task Slow as as Possible Run Task in in Available Time Task 1 Idle Task 2 Task 3 Energy Time Only need to to run run just justfast enough to to meet the the application deadlines
14 IEM System Implementation
15 ARM1176JZ-S Power Management Two Complementary Techniques: ARM1176 Dormant Mode, allows Complete Power-off of Core (no leakage in core) Retain system state in Cache/TCM at low voltage Minimize energy loss due to leakage in standby modes. Note : Requirement of isolation cells to clamp the RAM inputs IEM compatible core and design flow Enables dynamic voltage and frequency scaling Tune Performance dynamically to current demand Substantial reduction of energy consumption, extended Battery Life.
16 ARM Artisan Library Support
17 ARM Power-Management Kit Power gates (MT-CMOS) Power control of voltage islands via switchable voltage rails using header (shown) or footer cells Level shifter and isolation cells Up and down shifting with optional enable signal Retention flip-flops Maintain FF state after power down for leakage reduction Back-bias support Reduce leakage current via well-biasing with special fill_tie cells Always on buffer Buffering of signals in powered-down areas VDD1 VDD1 VDD1 Global VSS Global VDD Note: Picture shows a conceptual implementation VDD2 VDD2 VDD2
18 Agenda ARM and Cadence Collaboration irm ARM1176JZF-S IEM ARM Artisan Library Support ARM1176JZF-S IEM implementation flow using Cadence Encounter Platform Conclusion
19 ARM and Cadence irm ARM-Cadence Reference Methodology ARM Artisan Metro Standard Cell ARM Artisan Power Management Kit Compiled Views for Fire&ICE, VoltageStorm and Celtic NDC Timing ECSM extensions RTL Compiler SOC Encounter Fire & Ice QX Celtic NDC VoltageStorm Conformal Low Power
20 ARM1176-IEM irm Features CPF based flow CPF file is used to describe the low power intent and to drive implementation and verification flow Automated RTL to GDS Multi Supply Voltage Implementation flow Multi Mode Multi Corner (MMMC) analysis and optimization Ensures design is optimized across complete voltage and frequency range Tri-lib based flow Provides accurate interpolation for DVFS and IR drop analysis ECSM extensions to.lib
21 Cadence Low-Power Solution Define power architecture early-on in the design flow Capture once using CPF; no re-entry or translation later on Entire design flow understands CPF and helps preserve the power-intent Verification: Comprehensive low-power simulation and formal verification Design: Power-aware synthesis, equivalence checking, and DFT Implementation: Automated power-aware RTL-to-GDS layout Management: Power plan and metrics
22 What is the Common Power Format? Single specification of power intent used throughout design, verification, and implementation ASCII File that captures: Design intent Power domain Logical: hierarchical modules as domain members Physical: power/ground nets and connectivity Analysis view: timing library sets for power domains Power Logic Level Shifter Logic Isolation Logic State-Retention logic Switch Logic & Control Signals Power modes Definitions Transition Expressions Technology information Level shifter cells Isolation cells State-retention cells Switch cells Always-on cells
23 ARM1176-IEM CPF: MSV setup create_power_nets -nets VDDRAM create_power_nets -nets VDDCORE \ -external_shutoff_condition {SWITCH_VCORE} create_power_nets -nets VDD create_power_domain -name VCORE \ -instances $VCORE_moduleInst_list \ -boundary_ports "$VCORE_pins" \ -shutoff_condition {SWITCH_VCORE} update_power_domain -name VCORE \ -internal_power_net VDDCORE create_global_connection -net VDDCORE -domain VCORE -pins VDD create_global_connection -net VSS -domain VCORE -pins VSS create_power_domain -name VRAM create_power_domain -name VSOC default create_isolation_rule -name rule_vcore2vram \ -from VCORE -to VRAM \ -isolation_output low \ -isolation_condition {!RAMCLAMP} update_isolation_rules -names rule_vcore2vram \ -location to -combine_level_shifting \ -cells {LVLLHEHX8M} create_level_shifter_rule -name rule_vram2vcore \ -from VRAM -to VCORE update_level_shifter_rules -names rule_vram2vcore \ -cells {LVLHLX8M} -location create_level_shifter_rule -name rule_vsoc2vcore create_isolation_rule -name rule_vcore2vsoc_low create_isolation_rule -name rule_vcore2vsoc_high
24 Multi Mode Multi Corner (MMMC) Process www Dynamic Voltage Frequency Scaling wwb Mode PM_highV VSOC 1.08V VCORE 1.08V VRAM 1.08V Frequency 250MHz Multi PVT Corners Temp bbw PM_medV 1.08V 0.90V 0.90V 166MHz PM_lowV 1.08V 0.72V 0.72V 90MHz VCORE_Dormant 1.08V Off 0.72V 250MHz Multiple Modes with multiple constraints (.sdc) bbb Voltage Analysis View Corner definition Power mode Library Set.lib (.ecsm* ext).cdb (SI) Operating Conditions (PVT) RC Corner -SPEF -QX tech -Cap Table.sdc
25 ARM1176-IEM CPF: Power modes Same power modes are used by both Logic Synthesis (RTLCompiler) and by Place & Route (SOCEncounter) Mode PM_highV PM_medV PM_lowV VCORE_Dormant Dynamic Voltage and Frequency Scaling VSOC 1.08V 1.08V 1.08V 1.08V VCORE 1.08V 0.90V 0.72V Off VRAM 1.08V 0.90V 0.72V 0.72V Target frequency 250MHz 166MHz 90MHz 250MHz create_nominal_condition -name highv -voltage 1.08 update_nominal_condition -name highv -library_set libs-worst-1.08v create_nominal_condition -name OFF -voltage 0 create_power_mode -name PM_highV -default \ -domain_conditions {VCORE@highV VRAM@highV VSOC@highV} \ update_power_mode -name PM_highV -sdc_files ARM1176JZFS.constraints_PM_highV.sdc create_power_mode -name VCORE_dormant \ -domain_conditions {VCORE@OFF VRAM@highV VSOC@highV}
26 ARM1176-IEM CPF: Corners & Analysis views Operating corners and analysis views are only used for physical implementation Analysis and physical optimization are working concurrently on active analysis views create_operating_corner -name WCORNER_1.08 \ -voltage temperature 125 -process 1 -library_set libs-worst-1.08v create_operating_corner -name WCORNER_0.72 \ -voltage temperature 125 -process 1 -library_set libs-worst-0.72v create_operating_corner -name BCORNER \ -voltage temperature "-40" -process 1 -library_set libs-best-1.32 create_analysis_view -name WCVIEW_1.08 \ -mode PM_highV \ -domain_corners {VCORE@WCORNER_1.08 VRAM@WCORNER_1.08 VSOC@WCORNER_1.08} create_analysis_view -name WCVIEW_0.72 \ -mode PM_lowV \ -domain_corners {VCORE@WCORNER_0.72 VRAM@WCORNER_0.72 VSOC@WCORNER_1.08} create_analysis_view -name BCVIEW_1.32 \ -mode PM_highV \ -domain_corners {VCORE@BCORNER VRAM@BCORNER VSOC@BCORNER}
27 Automated CPF-driven MSV flow Constraints CPF Netlist Use the CPF to drive synthesis and physical implementation MSV/power domain partition (power domains with assigned instances, toplevel IO pins and power ground connections) Setup MMMC environment (power modes, delay corners and analysis views ) Isolation rules and level_shifter rules to automatize the usage of shifter / isolation cells: definition, identification from RTL, insertion, placement and optimization Synthesize, place, optimize, and route based on power domains Domain-aware Clock Tree Synthesis Static/Dynamic Power Analysis SI & Static Timing Analysis Low Power Functional Verification Top-down MSV/MultiMode Single-pass Synthesis Floorplanning / Silicon Virtual Prototype Power Grid Synthesis Isolation/level shifter cells check and insertion Placement including SRPG/Level shifters/iso cells Power Routing Low Power Clock Tree Synthesis Domain-aware Post-CTS Optimization Domain Aware NanoRoute IRDrop-Aware Timing/SI Opt. Sign-off MSV/MMMC Infrastructure GDSII Timing/Power Optimization
28 Logic synthesis Lib1 0.72V Lib2 0.90V Lib3 1.08V RTL Chip CPF Read/constrain top Apply power constraints Synthesize Top Analyze timing/power Chip SDC Power Domains Shifters Isolation Power modes Leakage Dynamic Clock Gating Lib1 0.72V Top PSO VCORE B Lib2 0.90V Isolation C Isolation Lib3 1.08V VSOC VRAM Adjust / incremental update Top-down single-pass synthesis with power domain definition Identification of level shifters and isolation cells already instantiated in RTL Multi-mode synthesis to consider frequency and voltage scaling Implementation of separated scan chains, for VSOC and VCORE domains Leakage power optimization using High-Vt cells
29 Floorplan: Power Domains Each power domain has its own dedicated row structure automatically created depending on the associated cell libraries Hard block placement is scripted and easily customizable through relative floorplan commands Power structure is automatically built via tcl script. create_power_domain -name VCORE \ -instances $VCORE_moduleInst_list -boundary_ports "$VCORE_pins" \ -shutoff_condition {SWITCH_VCORE} create_power_domain -name VRAM \ -instances "$env(vram_moduleinst_list)" -boundary_ports "$VRAM_pins create_power_domain -name VSOC -default \ -boundary_ports "$VSOC_pins"
30 Floorplan: Power Structure VRAM Rings and stripes for: VDDRAM, VSS VCORE Rings and Stripes for: VDDCORE, VSS VSOC Rings and stripes for: VDD,VSS create_ground_nets -nets VSS create_power_nets -nets VDDRAM create_power_nets -nets VDDCORE -external_shutoff_condition {SWITCH_VCORE} create_power_nets -nets VDD
31 Placement Standard cells, level shifters (single and multi-height) and isolation cells automatically placed in a single pass verifypowerdomain command checks: nets crossing the boundaries (both level shifter cells and isolation cells) library binding placement of instances in a power domain IO pins assigned to the correct power domain
32 Level Shifters / Clamps: VCORE-VRAM Triple-row height LVLLHEH shifters Vertical connections of VDDI pins to VDDCORE power net automatically routed VRAM VSS VDDRAM Single-row height LVLHL shifters VDDCORE VSS create_isolation_rule -name rule_vcore2vram \ -from VCORE -to VRAM -isolation_output low \ -isolation_condition {!RAMCLAMP} update_isolation_rules -names rule_vcore2vram \ -location to -cells {LVLLHEHX8M} \ -combine_level_shifting create_level_shifter_rule -name rule_vram2vcore \ VCORE -from VRAM -to VCORE update_level_shifter_rules -names {rule_vram2vcore} \ -cells {LVLHLX8M} -location to
33 Clock Tree Synthesis & Routing CTS in SOC Encounter is power domain aware For all clocks crossing power domains, CTS assumes that level shifters are present (according to CPF rules) A single pass top-down clock tree is created by CTS CTS does the following: Establishes a single entry/exit point for each domain Selects buffers from appropriate libraries and places them within domain boundaries Balance skew through domains and for all active corners/views Both trialroute and nanoroute honour power domains in SOC Encounter
34 Cross-Domain Timing Optimization Optimization transparently considers level shifter / clamp placement and signal direction Parts of net should be don t touch Buffer needs to be inserted from the correct library and into the correct module Buffer location is timing driven Optimizes timing and design rules concurrently for all active corners/views Power Domain A Libraries A Power Domain A Libraries A Power Domain A (0.8V) Libraries A Power Domain B Libraries B Power Domain B Libraries B Power Domain B (1.0V) Libraries B 0.8V I/O Don t touch nets 0.8V I/O
35 Variable VDD Flow Assign non-pre-characterized VDD value as the operating voltage and run through timing optimization closure Using ECSM and tri-lib technology for better accuracy Requires a minimum of two library characterized for different voltages for good a accuracy in full range Supported by analysis and optimization Delay Calculator Process Temp SS, 125 o C 1.08V 0.90V 0.72V Dynamic Voltage and Frequency Scaling Mode VSOC VCORE VRAM Target frequency PM_highV 1.08V 1.08V 1.08V 250MHz PM_medV 1.08V 0.90V 0.90V 166MHz PM_triV 1.08V 1.00V 1.00V 200MHz VCORE_Dormant 1.08V Off 0.72V 250MHz
36 Library support for MMMC Library /Process ARM Metro libraries for TSMC CL013G process Available voltage corners WC: 0.72V, 0.9V, 1.08V BC: 0.88V, 1.1V, 1.32V Required views Timing models (.lib) characterized at available voltage corners, optionally with ECSM extensions for better accuracy Noise models (.cdb) characterized at available voltage corners
37 ECSM advanced timing models Delay sensitivity to Vdd increases nonlinearly at smaller geometries.lib and K-factors not accurate at low V dd and between characterization points need for more accurate cell models for IR-drop and MSV ECSM accurately models delay variations with V dd: Captures the waveform-dependent non-linear behavior of the receiver-pin capacitance Driver modeled as a current source: I/V curve for each slope, load combination ARM-Cadence RM deploys ECSM models for signoff STA within Encounter, leveraging detailed instance voltages output by power analysis. Delay (ps) nm Buffer, 1V nominal supply Non-linear increase in Delay due to V dd scaling 30% Linear Approximation Voltage (V dd ) SPICE ECSM-based K Factor
38 Formal Verification Functional equivalence check Structural checks (Conformal Low Power Solution) Missing level shifters and power connectivity Missing isolation and power connectivity Bad isolation cell and level shifter Correct cell placement in physical domain Isolation cell enable Enable VCORE A Vi Vo Y VRAM
39 Power and Rail analysis Placed & Routed Design Database Plots Derive Power-Pin Location CPF Mode Specification Power Libraries Report Power (Common Power Engine) Power-Switch ECO Static & Dynamic IR-drop Analysis Decap ECO Waveforms & IR drop Files Timing & Critical Path VDDCORE IR drop analysis Analysis
40 Conclusion Comprehensive Low Power support across RTL2GDS Leverages state of the art features, including DVFS and variable VDD flow Optimized and tested for use with latest Cadence tool releases Complete offering Processor IP Reference libraries Portable Reference Methodology Scripts for Cadence tools ARM and Cadence collaboration Streamlining rapid deployment of ARM processor products Accelerate time to market for the ARM Partner Available to ARM partners and Cadence customers
41 Thank You
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