ear Wide-Dynamic-Range BiCMOS Operational Transconductance Amplifier for High Frequency Applications

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1 ear Wide-Dynamic-Range BiCMOS Operational Transconductance Amplifier for High Frequency Applications Anchada Charoenrook and Mani Soma Department of Electrical Engineering University of Washington FT-10 Seattle, WA U.S.A Abstract This paper presents a very linear and wide dynamic range icmos operational transconductance amplifier for use in high performance, high frequency analog and mixed-signal applications. The design structure of the input stage together with the optimized use of BiCMOS technology provides the OTA with wide dynamic range and very low distortion properties. Comparisons between MOSFET, bipolar and BiCMOS configurations of the conversion stage are presented. The frequency response of the circuit is also analyzed in detail, including frequency compensation techniques. Simulation results using a generic BiCMOS technology [7] illustrate a THD of less than -68 db at Vin = k4 V at 50 MHz. 1. NTRODUCTON The increasing interest in high performance analog and mixed-signal processing drives the need for high speed Operational Transconductance Amplifiers (OTAs) [ 11. These applications often require very linear (7-10 bits) and wide dynamic range OTAs. A number of bipolar and CMOS OTAs have been proposed [2,3]. Each technology has its advantages and drawbacks. BiCMOS technology offers the possibility of designing and customizing the designs for high performance circuits by capitalizing on the best features of both technologies while minimizing their unfavorable features. More recently, a number of BiCMOS OTAs have been proposed. They are based on emitter degeneration of bipolar devices [4] or use the linear region in MOS- FETs as means to convert voltage to current [5]; Total Harmonic Distortion (THD) was reported to be 1% and 0.3% respectively. A design of a transconductor building block stage employing a BiCMOS complementary Darlington-connect pair (PMOS-npn) was also proposed [6]. This paper presents a low distortion wide-dynamic-range high speed BiCMOS OTA. Wide dynamic range is obtained by employing a resistor across the emitter of the differential pair. Unlike emitter degeneration schemes, the voltage across the resistor is. not in series with the input transistor, thus allowing a much wider input dynamic range. The use of a self-biased Darlington-connect (NMOS-npn) transistor as the input differential pair provides the circuit with very low distortion properties. This BiCMOS self-biased Darlington-connect employs a NMOS at its input giving the composite device near zero base current; conducts most current through the bipolar device, obtaining high g,; and uses a resistor to bias the MOSFET, reducing drain current modulation and decreasing device count in the circuit. Compensation techniques are used to enhance the frequency response of the OTA. 2. BASC OPERATON OF THE OTA The schematic diagram of the OTA is shown in Fig. 1. The input stage of the circuit consists of a BiCMOS self-biased Darlington-connect differential pair (ml, m2, Q, Q2, R2). MOSFET and bipolar transistors operate in the saturation and active regions respectively. The input differential volt- age (Vin+- V,;) is forced on resistor R which converts the input voltage into differential current i. Using this topology the voltage across the resistor is not in series with the input transistor, thus allowing a much wider input dynamic range without sacrificing linearity. Because the conversion is performed by the resistor, linearity region is only limited by the overhead voltage of the current source and current mirror. The incremental collector currents of the input pairs equal the current through resistor R. The second stage which consists of the current mirrors (Q3, Q4, Q5, Q6) replicate this current to the output stage of the OTA. At the output stage (Q7, Q8), the total current is subtracted by the biasing current from the current source (Q9, QlQ Q13, Q14) resulting in the incremental current leaving the OTA as Out+ and,,;. Thus the differential output current (out+ - Z,;) is proportional to the input voltage (Vin+ - Fi) by roughly / R. Low Early voltage of the transistors result in low output impedance. To improve the output impedance of the OTA, the output cascode stages are used, and current sources consisting of Q13 and 1214 are used to reduce biasing current of the output stage. The common mode feedback circuit consists of devices m3 to m6, Q12, Q13, and Q15. t adjusts the output current source to reduce common mode voltage output. When the output common mode voltage is higher than zero, current through Q15 increases reducing the output voltage; when output voltage is low the effect is complemen t ar y B /94/ 1994 EEE

2 Vcc 6 - ml to m6 W/L=8u/O.8u other bipolar area = 1 20 kohm -. vss -+- Figure 1: Schematic diagram of the OTA. 3. LNEAR DYNAMC RANGE The transconductance of the input stage is given by: vi,+ - v- = in where Q1+m, =,, iq1+i,, = i, Q2 'm2 = ' 1 and, iq2+im2 = -i. Q~, Q2, i~2, iq1 are the biasing collector currents of transistors Ql and Q2, and incremental collector currents of transistors Ql and Q2 respectively. ml, m2, imj, and im2 are the biasing drain currents of ml and m2, and the incremental currents of ml and m2 respectively, and the constant k = CO# ( W/ (2L) ). The second term on the right hand side of Eq. (1) is the error term due to bipolar's Vb, dependence on C. The third and fourth term are the errors due to square law dependence of d on Vgs. Both error terms decrease with increasing bias current. To obtain low Total Harmonic Distortion (THD) Zl is set high,, >> i. The BiCMOS composite device is biased such that the drain current of the MOSEET is about 5% of the total biasing current or more than the maximum base current of the bipolar transistor (Ql), so that bipolar npn transistor handles most of the current because it has a higher g, and lower noise. Resistor R2 serves the purpose of biasing the MOSFET. t is also used to provide local feedback, further reducing drain current modulation. Assuming the current through resistor R2 is constant, the MOSFET error term is attenuated by approximately 0. The input MOSEET provides the circuit with high input impedance and returns the bipolar device (Ql) base current to the collector of the composite device. This reduces the harmonic distortion introduced by p variation with collector current. As biasing current increases, this design configuration keeps the input linear dynamic range near constant and higher than that of MOSFET input pairs. BiCMOS configuration also attains lower harmonic distortion than that of either bipolar only or MOSFET only input pairs (Fig. 2 (a,h)). These benefits result from the characteristics of the devices. Thus changes in parameter processes may change the absolute value gained, but the BiCMOS configuration will still be superior, especially in applications where both dynamic range and THD are concurrently required. Bipolar and MOSFET devices have their virtues and flaws. A MOSFET implementation of the input pairs will provide a very high input impedance and near zero leakage gate current. However, at high biasing currents (in the order of milliamperes to obl.ain low THD),. the gate to source voltage (V,,) is high, rapidly decreasing the input dynamic range

3 ig. 2 (b)) and eventually saturating the current sources and e input capacitance will also increase pro- term only decreases as square root of increasing biasing current, generating higher THD than its bipolar counterpart. A bipolar implementation of the input pair has an error term which decreases logarithmically with biasing current providing very low THD at high biasing currents. However, it es a lower input impedance. Moreover, at very low biasing currents, the variation of p with its collector current introduces harmonic distortion into the differential current. Other high current effects in the bipolar device also ~ n the ~ rapid ~ decrease b of ~ THD ~ when the biasing current is increased. Hence THD decreases to a minimum and starts ~n~reas~ng biasing current increases (Fig. 2 (a)). Fig. 2 shows simulation results comparing THD between input stage ~mp~emen~ed using bipolar, MOSFET, and BiC- S d~~erential pair (parameters from [7]). Saber simulator was used to run the simulations. Saber s MOSFET model level 3 which includes short channel effects was eased. 4. AG ANALYSS A. nput stage The input stage consists of the input BiCMOS Darlingtonconnect differential pair, resistor R and the current sources. The input of this stage is Vi, and the output is il. From Fig. 1, assuming rol >> input impedance of the second stage which is close to /gm3 (at DC); rbl cc R2 and r,,, and g,, << gm ; the transfer function of the first stage can be written as: i, 1 (l+sccr1) 1 (+s/q) (2) where C, is the capacitance looking into the output node of current source l. B. Second stage The second stage is the current mirror which consists of transistors Q3 and Q5. The effect of this stage on the frequency response can be observed by deriving the collector current of transistor Q5(i5) from base current of Q3 and il: 1 1 For R, >> rb3 >> -, and rn5 >> rb5 >> -, the poles gm3 gm3 and zeros are approximately bounded as BiCMOS Biasing current (ma) C. Output stage The output stage consists of a common base transistor Q7. Referring to Fig. 1, and disregarding Cp7 we can derive the collector current of Q7 as: 1 - l7 -- i5 (1 +s/pg) (1 +s/p7) - Depending on the value of gm7, p4 and p7 may be real or a complex conjugate pole pair. At high biasing current (approximately l/gm7 <rb7i rc5 ), the poles are a Biasing current (ma) Figure 2: (a) nput stage THD at Vin f 4V and (b) nput dynamic range for various technologies. complex conjugate pair and are located at high frequencies CK7 + ccs5 (P6 P7>2~ c z7 cs5 (rc5 $- rb7) ). At low biasing cur- 12B.2.3

4 rent (approximately 1 /gm7 > rb7 + rc5 ), they are real and are located at lower frequencies. p6 and p7 are real and equal when l/gm7 E;: rb7 + rc5, and their magnitudes are derived as Considering all the stages together with Eqs. (2), (3), and (4), the transfer function of the OTA can be approximated as : where i =1 to 2 andj = 1 to 7. Referring to the analysis above, 22, p2 and p4 are located Zg,,/C,, which is at a high frequency close to ff Hence they are not the limitation in the frequency response. Depending on the process parameters, the biasing condition, and the implementation of current source 11 one of the following cases may be the limiting factor in the frequency response of the OTA. 1. p6 and p7 dominate at low frequencies. The values of the poles depend on the biasing current of the output stage. The biasing current of the output stage can be adjusted according to the derivation in section C in order to relocate the poles to higher frequencies. 2. p3 and p5 dominate at low frequencies. p3 and p5 are generated from the second stage. The absolute values of these poles are dictated by the process parameters and cannot be easily altered. f Z is at a higher frequency than p3 and p5, a compensating capacitor can be placed in parallel with current source 11 in order to lower 21 to compensate for either p3 or p5 whichever pole is at lower frequency. The exact value of the compensating capacitor must be determined by simulation. 3. z dominates at low frequencies. z is the zero resulted from the output impedance of current source Z, in parallel with R. R is set by the biasing current and the level of TRD required. For a constant biasing condition in the input stage, decreasing R will reduce THD. To compensate for z lower either p3 or p5 (whichever is at lower frequency). This is carried out by adding a compensating capacitance between the collector and emitter node of Q3 (Fig. 3 (a)) or between the collector and emitter node of Q5, decreasing p3 or p5 respectively. The value of the compensating capacitance and side effects on other higher frequency poles are determined through simulation. The process parameters used with the OTA in Fig. 1, resuit in z being the dominating element at 1.5 GHz; p3 close to 5 GHz and p5 clo:;e to 10 GHz; p6 and p7 > 27 GHz. Compensating capacitors (Ccom) (Fig.1) were added to reduce the effect of zl.the resulting frequency response of the output current has an excess phase of 2% at 200 MHz (Fig. 3 case <4>) and -3dB frequency at 9.5 GHz. For continuous-time filer application where the excess phase is critical [4], C CQ~ of 1 pf can be used to obtain an excess phase of less than 1% at 800 MHz (Fig. 3 case <2>). 5. SMULATON ~ U L ~ S Generic BiCMOS process parameters from [7] were used. The current sources zr 13, and 11 were implemented by simple current sources and a cascode current source respectively. Saber simulator was used to run the simulations. Saber s MOSFET model level 3 which includes short channel effects was used. Simulation results are as follows: 1. Linearity: THD less than 4*10-4 or -48 db at 50 MRz input voltage. 2. Dynamic range: Vin = f4 Volts. 6. CONCLUSONS This paper has presented an OTA design whose design structure and the optimized use of BiCMOS gives very linear and wide dynamic range properties. The paper also discussed the advantages of using BiCMOS technology compared to bipolar and MOSFET for this QTA. Frequency compensation techniques to enhance the frequency response were proposed. Simulation results of the OTA were illustrated. They conform with the analysis presented, Employing generic BiCMOS process parameters, shnulation of the OTA shows in THD of less than -68 d voltage of +4 Volts at 50 MHz. A ~ ~ Q ~ ~ e ~ ~ ~ e ~ t Partial financial support for this work has been provided by NSF Grant MP , SRC Contract 94-DJ-552, and the Washington Technology Center Contract for Mixed-signal Design and Test. eferences [l] V. Cornino, M. S. J. Steyaert, and G. C. Themes, 6A first-order current steering S gma-delta modulator, EEE J. Solid-state Circuits, Vol. 26, No. 3, March 1991, pp [23 A. Wysznski, <. Schaumann, S. Szczepanski, and P Van Hah, Design of a 2.7-GHz linear QTA and a 250-MHz elliptic filter in bipolar transistor-array technology, EEE Trans. Ci,: Syst., Vol. 40, NO., Jan 1993, pp [3] E. J. van der Zwan, E. A. M. Klumperink, and E. Seevinck, A CMOS OTA for high filters with programmable transfer function, EEE J. of Solid-,rtate Circuits, Vol. 26, No. 11, November pp [4] E Rezzi, V. Pisati, K. Castello, and R. Alini, Novel ineariza

5 tion circuit for BiCMOS transconductors used in high frequency pp OTA-C filters, Proc. ofeee SCAS, Vol. 2, 1993, pp [7] S. H.K. Embabi, A. Bellaouar, and M. 1. Elmasry, Digital BE C- [S R. Castello, E Montecchi, R. Alini, and A. Baschirotto, A MOS ntegrated Circuit Design, Kluwer Academic Publishers, very linear BiCMOS transconductor for high-frequency filter Norwell, Massachusetts, U.S.A, pp and application, Proc. of EEE SCAS, 1990, pp [6] S.D. Willingham, K. W. Martin, BiCMOS components for video-rate continuous-time filters, Proc. of EEE SCAS, 1992, , ,.. : : : Figure 3: Phase response (degree) <1> zero compensation, <2> C,,,,,=l pf, <3> Ccom=4 pf, <4> C,=6 pf, <5> C,,,=lO pf. Figure4: THD of the output current of the OTA B.2.5

Radivoje Đurić, 2015, Analogna Integrisana Kola 1

Radivoje Đurić, 2015, Analogna Integrisana Kola 1 OTA-output buffer 1 According to the types of loads, the driving capability of the output stages differs. For switched capacitor circuits which have high impedance capacitive loads, class A output stage