Active Electrode IC for EEG and Electrical Impedance Tomography with Continuous Monitoring of Contact Impedance

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1 PRE-PRINT VERSION. TO APPEAR IN IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS 1 Acive Elecrode IC for EEG and Elecrical Impedance Tomography wih Coninuous Monioring of Conac Impedance Marco Guermandi, Robero Cardu, Eleonora Franchi Scarselli, Member, IEEE, and Robero Guerrieri, Member, IEEE Absrac The IC presened inegraes he fron-end for EEG and Elecrical Impedance Tomography (EIT) acquisiion on he elecrode, ogeher wih elecrode-skin conac impedance monioring and EIT curren generaion, so as o improve signal qualiy and inegraion of he wo echniques for brain imaging applicaions. The elecrode size is less han 2 cm 2 and only 4 wires connec he elecrode o he back-end. The readou circui is based on a Differenial Difference Amplifier and performs single-ended amplificaion and frequency division muliplexing of he hree signals ha are sen o he back-end on a single wire which also provides power supply. Since he sysem s CMRR is a funcion of each elecrode s gain accuracy, an analysis is performed on how his is influenced by mismaches in passive and acive componens. The circui is fabricaed in 0.35 µm CMOS process and occupies 4 mm 2, he readou circui consumes 360 µw, he inpu referred noise for bipolar EEG signal acquisiion is 0.56 µv RMS beween 0.5 and 100 Hz and almos halves if only EEG signal is acquired. I. INTRODUCTION Neuroimaging is a discipline which deals wih he abiliy o image he srucure and/or funcionaliy of he cenral nervous sysem (CNS). Among he echniques currenly used o provide funcional maps of CNS aciviy in clinical pracice or a research level we may menion Posiron Emission Tomography (PET), Funcional Magneic Resonance Imaging (fmri) [1], Elecro- and Magneo-Encephalography (EEG and MEG) [2] and Diffuse Opical Tomography (DOT, also known as NIRS) [3]. The firs wo echniques provide he highes level of spaial accuracy a he price of raher low emporal resoluion (one scan every few seconds). Moreover, he expensive and voluminous hardware limis use of hem o hospial seings while paien discomfor hampers several possible applicaions, for example in sleep research or epilepic focus localizaion which require long-erm monioring. By conras, he oher echniques rade spaial accuracy for compacness, movabiliy and ease of use. In paricular, he localizaion of EEG signal sources is a fairly well esablished mehod This work has been creaed in he scope of he CSI projec. The CSI projec has received funding from he ENIAC Join Underaking under gran agreemen n and from he naional programs/funding auhoriies of Ausria, Hungary, Ialy and he Neherlands. M. Guermandi, E. Franchi Scarselli and R. Guerrieri are wih he Advanced Research Cener on Elecronic Sysems (ARCES), Universiy of Bologna, Bologna, Ialy ( mguermandi@arces.unibo.i, eleonora.franchi@unibo.i, robero.guerrieri@unibo.i). R. Cardu was wih he Advanced Research Cener on Elecronic Sysems (ARCES), Universiy of Bologna, Bologna, Ialy. He is now wih ST Microelecronics, Agrae Brianza, Ialy ( robero.cardu@s.com). c 2014 IEEE. Personal use of his maerial is permied. Permission from IEEE mus be obained for all oher uses, in any curren or fuure media, including reprining/republishing his maerial for adverising or promoional purposes, creaing new collecive works, for resale or redisribuion o servers or liss, or reuse of any copyrighed componen of his work in oher works. of providing funcional maps of brain aciviy [2] and one which guaranees good levels of porabiliy and comfor for he paien. I is rue ha EEG source localizaion suffers from a lower spaial resoluion han fmri and PET; however images can be acquired a a much higher sampling rae, allowing analysis of phenomena occurring a ime inervals of fracions of seconds. A diagnosic sysem based on EEG source localizaion could herefore be ideal for seings such as docors surgeries, he home or ambulances, provided an improvemen in spaial accuracy can be achieved. Since EEG source localizaion relies on he abiliy o reconsruc curren dipole locaions inside he paien s head volume by measuring he volages generaed on is surface, a high densiy sysem is required so as o opimize he localizaion accuracy [4]. EEG source localizaion algorihms rely heavily on he availabiliy of an accurae, paien-specific head model able o describe he elecrical behavior of he domain [5]. To his end, if one could obain srucural informaion, say, from a one-off MRI scan, ha would significanly increase he reconsrucion qualiy. However his would sill no provide direc informaion abou he conduciviy of he various issues or regions which are in pracice commonly guessed by simply assigning a single, ime-invarian conduciviy value o each of he few issues ino which he head volume is usually segmened. To overcome hese limiaions, i has been proposed ha local, ime-dependen conduciviy informaion be provided by Elecrical Impedance Tomography (EIT) [6][7] a relaively new imaging echnique which allows one o esimae he conduciviy disribuion inside a body by injecing small AC currens a frequencies ranging from a few KHz o a few MHz on he surface and measuring he resuling volage on he same surface. Applicaions range from lung monioring [8] o personalized monioring sysems [9]. Alhough his is no he designed arge applicaion for he ASIC presened, EIT is allegedly able o direcly image brain aciviy by measuring conduciviy variaions in cerebral regions due, for example, o modificaions in blood perfusion, akin o he BOLD signal deeced by fmri [10]. Recenly, ASICs have been specifically designed for EIT measuremens [8][11] bu no for being direcly inegraed on he elecrode. A common source of EEG signal qualiy degradaion is he conac impedance which exiss a he inerface beween he elecrode meal surface and he paien s skin. A high value of conac impedance leads o a poenial divider effec a he inpu of he remoe amplifier which causes a reducion in CMRR; i also increases he noise generaed a he mealskin inerface and augmens he effec of inerference coupling hrough capaciive effecs o he cables, or arifacs due o cable movemen, microphony and he piezoelecric effec [12].

2 PRE-PRINT VERSION. TO APPEAR IN IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS This can be paricularly roublesome when performing an EEG on an epilepic paien since arifacs can be incorrecly inerpreed as seizures. Conac impedance is minimized in clinical EEG proocols by removing superficial skin layers by abrasion and insering a conducive gel or pase in-beween he wo surfaces. Exensive skin preparaion is no suiable for high densiy sysems and ou-of-hospial seings in view of he long preparaion ime, infecion risks and significan level of raining required by he person placing he elecrodes [13]. This paper presens an IC enabling one o inegrae he 2 EEG, EIT and ESI was presened in [16]. As compared o ha, he presen soluion improves performance by reducing power consumpion by a facor of almos hree, whils sill achieving lower noise. This is obained hanks o a differen archiecure in he readou circui which is now based on a single Differenial Difference Amplifier (DDA) raher han hree operaional amplifiers. Moreover, he digial inerface is exended so ha an EIT curren waveform is obained by direc synhesis, soring he 8-bi waveform samples in an onchip memory, which gives a much larger degree of freedom in choosing EIT curren waveforms han wih square wave alone. To our knowledge, his work and [16] are he firs and only aemps o inegrae EEG, EIT and ESI on an acive-elecrode. An overview of he acive-elecrodes and of he full sysem in which hey are inegraed is presened in Secion II; Secion III presens he inegraed circui and he single blocks composing i; while Secion IV shows measuremen resuls, boh from an elecrical characerizaion sand-poin and from some simple funcional esing in acquisiion of EEG, EIT and conac impedance. Conclusions are drawn in Secion V. II. A N EEG SYSTEM BASED ON ACTIVE - ECTRODES Fig. 1. On he op, he es sysem for he acive-elecrode characerizaion. On he boom, picures of he op and boom side of he elecrode before cable soldering and sealing wih resin. In order o undersand he design requiremens for he acive-elecrodes, he es sysem developed for elecrode characerizaion is inroduced in Fig. 1. Each acive-elecrode can be configured a any ime beween i) EEG/ESI readou, ii) EIT poenial and EEG/ESI readou and iii) EIT curren injecion. A. Acive-elecrode specificaions and characerisics fron-end for EEG and EIT acquisiion on he elecrode, ogeher wih elecrode-skin conac impedance monioring (ESI) and EIT curren generaion. The main purpose is o provide a sysem which enables he user o gaher conduciviy informaion on he head issues from EIT measuremens, so as o improve EEG source localizaion. The IC is designed o acquire EEG and EIT signals (plus he elecrode conac impedance) a he same ime so as o have he bes possible inegraion beween he wo echniques. This overcomes he common limiaions associaed wih using wo separae sysems for EEG and EIT. I direcly performs signal precondiioning on he elecrode, much like acive-elecrodes repored in he lieraure [14][15] which improve EEG signal exracion qualiy by placing a high inpu impedance, low oupu impedance and low noise amplifier direcly on he elecrode, so as o be less prone o issues originaing from conac impedance. The acive-elecrode is also designed o down-conver he EIT oupu volage o a lower frequency, so as o relax back-end bandwidh specificaions, and synhesize EIT inpu curren. Anoher design feaure is he abiliy o coninuously monior ESI, which can provide informaion on he signal qualiy and a possible need o replace or reposiion an elecrode [16][17]. The acive-elecrode area is small enough o be compaible wih high-densiy inegraion; moreover, since EEG, EIT and ESI signals share he same oupu line, he wire number is minimized and only one acquisiion channel is required by each elecrode. A differen implemenaion of his acive-elecrode able o joinly exrac Specificaions for EEG signal qualiy are derived from he Inernaional Federaion of Clinical Neurophysiology (IFCN) s sandards which are commonly adoped in clinical pracice [18]. Preamplifier inpu impedances should be higher han 100 MΩ, he Common Mode Rejecion Raio (CMRR) of he sysem mus be a leas 110 db and addiional noise inroduced in he recording should be less han 0.5 µv roo-mean-square a any frequency from 0.5 o 100 Hz including Hz. Unlike EEG, EIT is currenly no included in sandard clinical pracice and is only being used in research seings, so no widely acceped sandard exiss o define he minimum requiremens in erms of signal qualiy. Concerning maximum noise value, he choice was o adop he same level as for EEG signals. The maximum insananeous value of EIT injeced curren was deliberaely limied o 127 µa. This value is well wihin he limis prescribed by IEC echnical sandards for medical elecrical equipmen since injeced curren frequency is limied o values higher han 16 KHz [19]. Common mode rejecion of an EIT sysem is no required o remove inerference coupling from he mains as happens wih EEG signal acquisiion, bu mainly o preven he measuremen from being affeced by he common mode signal inroduced by he volage drop which may be caused by unmached EIT currens flowing o ground [20]. In general, values in he order of 60 o 70 db are commonly found in sysems repored in he lieraure [21] and are herefore used as he specificaion. Common injecion frequencies for EIT range from a few KHz o MHz [6][21]. In his sysem, he maximum

3 PRE-PRINT VERSION. TO APPEAR IN IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS 3 injecion frequency is limied o 256 KHz, since working a higher frequency generally requires exensive and coninuous calibraion o compensae for differen behavior among he full se of elecrodes. This is unrealisic in a sysem which is designed o be easy o use and se up. In order o suppor high-densiy sysem inegraion, he elecrode PCB (see he picures in Fig. 1) occupies less han 2 cm 2 and places he IC on he op side ogeher wih a few exernal componens; soldered ono he boom side are he wires connecing he elecrode o he back-end. Boh sides are hen covered wih resin in order o seal he elecronics. The PCB has a 5 mm diameer hole whose walls are gold-plaed; his is used for direc conac wih he paien s skin, achieved by placing he PCB on he scalp and filling he hole wih conducive gel. This elecrode size allows for a high-densiy sysem wih up o 300 channels approx. for an average-size head. For such a high number of channels, cable lighness and compacness are of major imporance; hence, he number of signals needed o connec each elecrode o he back-end was minimized o 4, namely he oupu signal (OUT), ground and wo digial programming signals (CK, DATA). The elecrode is conneced o he back-end by means of a 1 m four-core cable erminaing in a four-pole ouch-proof connecor. A dedicaed power line is no foreseen; he power supply for he analog par is provided by he oupu line iself, which is DC biased by a programmable exernal curren source whose value can be increased when he elecrode is acing as an EIT curren source in order o provide his addiional curren only when requesed. The oupu line is shared among EEG, EIT and ESI signals by placing hem a differen frequency bands. I should be noed ha none of he hree signals is ransferred a baseband. The firs reason for his is ha in his way mos noise and inerference which can couple o he ground and oupu signal hrough he cables (e.g Hz nework inerference) do no affec he readou volages. Moreover, every signal is locaed above he flicker noise corner frequency of he circuis on he elecrode and a he back-end, somewha as is done in sandard chopper amplifiers [15], where he bes rade-off beween noise and power consumpion can be obained. A hird reason relaes o he gain accuracy and CMRR and will become clear in Sec. II-B. Each elecrode performs single-ended amplificaion. This is desirable since i avoids sending back he reference signal o each elecrode, which would lead o an increased number of wires. The difference beween each signal and he reference one is performed a he back-end. The main drawback of his soluion is he limi i poses on he CMRR of he sysem, which is limied by he mismach beween he single-ended gains of he wo elecrodes ICs, as discussed in Sec.II-B. The final down-conversion o baseband (wih quadraure signals for ESI and EIT) and separaion of he hree signals is no performed unil afer analog-o-digial-conversion, so as o relax noise level specificaions a he back-end as well. B. Common Mode Rejecion Raio analysis for single-ended amplificaion Referring o Fig. 2, le us consider wo acive-elecrodes based on a non-invering inegraed amplifier in which, o V CM V d /2 V d /2 V 1 V 2 C 1 C 1 C 2 C 2 R R IC1 V o1 V IC2 o2 V d OUT Fig. 2. Sample circui for compuing CMRR reducion due o mismaches in he gain of he amplifiers of wo acive-elecrodes (G 1 = 1 + C 1 /C 2 and G 2 = 1 + C 1 /C 2 ). obain he highes achievable gain accuracy and avoid complex and expensive rimming procedures, he gain value is fixed by a capaciance raio (G = 1 + C 1 /C 2 ). Resisor R is insered only for DC biasing of he invering node and is effec may be considered negligible a he frequency in quesion. The difference of he wo oupu signals will be: V dout = G 1 + G 2 V d +(G 1 G 2 ) V CM =G D V d +G CM V CM 2 (1) which gives a CMRR of CMRR = G D G CM = G 1 + G 2 2 (G 1 G 2 ) hence limied by he mismach beween gains G 1 and G 2 of he wo amplifiers. The main sources of gain mismach are he limied gain of he OpAmp and he mismach in acive and passive componens wihin he same IC [22]. We now focus on mismaches on capaciors, while oher causes will be discussed in Sec. III-B once he acive elemen opology is inroduced. A simple model for inegraed capaciors describes he sandard deviaion σ of he raio beween he capaciance mismach C and is desired value C as ( ) C σ A c = ɛ c (3) C W L C where ɛ c = A c C a is a process-dependen parameer (i can be roughly esimaed o be in he range of for he process used) and C a he capaciance per uni area. The wors case scenario for he mismach beween he gain of wo differen ICs G 1 and G 2 will be: (2) G 1 = 1 + C1 C1 C 2+ C 2 G 2 = 1 + C1+ C1 C 2 C 2 (4) where C 1 and C 2 are he absolue value of he maximum deviaion which is expeced on capaciance values C 1 and C 2. Common mode and differenial gain will herefore be given by: G CM = 2 C2 C1+C1 C2 C2 2 C2 2 G D = 1 + C2C1+ C2 C1 C2 2 C2 2 (5)

4 PRE-PRINT VERSION. TO APPEAR IN IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS 4 ECTRODE IN EIT ESI READOUT M1 M2 V REF 512x10 MEM DIGITAL INTERFACE & CTRL I IC PCB OUT AVDD CK DATA DVDD IN EEG ESI EIT feit V 1 EIT 1 KHz f EIT 1 KHz V 1 IN V 2 2 KHz OUT READOUT OUT EIT EEG ESI ESI 1 KHz 2 KHz 1uA 65uA V 2 EEG ESI ESI 2 KHz Fig. 3. On he lef, scheme of he acive-elecrode s IC and PCB. On he righ, frequency plan for muliplexing he hree signals on he same oupu line. The CMRR will be: CMRR = C1C2+ C1 C2+C2 2 C2 2 2 (C 2 C 1+C 1 C 2) C 2C 1+C (C 2 C 1+C 1 C 2) having assumed ha C 1,2 >> C 1,2. Now, subsiuing C 1 = (G 1) C 2 and considering a ±3σ deviaion for he capaciance values which, from (3), gives C 2 = 3ɛ c C2 and C 1 = 3ɛ c (G 1) C2, one ges CMRR = C 2 6ɛ c G = C T 6ɛ c G 1+ (G 1) G G 1+ (G 1) where, since capaciance size is generally limied by area occupaion consrains, he CMRR is expressed as a funcion of he oal capaciance C T = C 1 + C 2 = G C 2. From (7), one can observe how he CMRR is no only affeced by process-dependen parameer ɛ c and he sizing of capaciances C T, bu also decreases as he differenial gain increases. For he sandard CMOS 0.35µm process used in his design, a reasonable area occupaion in he order of 0.5 mm 2 for he passive componens yields a oal capaciance value of abou 200 pf. Limiing he differenial gain o a value of 10, he maximum achievable CMRR is compued from (7) o be abou 70 db. One addiional reason for limiing he differenial gain is ha he addiion of he EIT signal on each elecrode easily leads o high ampliude signals up o some ens of mv on he elecrodes near hose injecing currens. Moreover, i should be poined ou ha single-ended amplificaion is prone o reducion in CMRR performance due o non-linear behavior which migh arise for large oupu swings. IFCN sandards prescribe a CMRR of a leas 110 db for he acquisiion of an EEG signal. Driven Righ Leg (DRL) loops are commonly used in EEG sysems [12][23] in order o increase he CMRR by 30 o 40 db and can be implemened o saisfy he specificaion. I should be poined ou ha, since he DRL loop bandwidh needs o be limied o a few hundred Hz so as o guaranee sabiliy, i does no increase he CMRR a EIT frequencies. When using capaciive passives o se he gain of he amplifier, one should bear in mind ha an addiional resisive pah needs o be added in parallel in order o se he DC volage of inernal nodes (resisor R in Fig. 2). In high-cmrr differenial amplifiers for neural recording applicaions [15][16][24] i is (6) (7) common o subsiue sandard resisors by so-called MOSbipolar pseudoresisor elemens which, for small volages across he device, can achieve an incremenal resisance in excess of Ω. This value would no be high enough o guaranee he required gain accuracy and CMRR a he lowes limi of he sandard EEG band (0.5 Hz), while i is sufficien in he frequency bands where EEG signals are up-convered and EIT signals down-convered prior o amplificaion. A. Archiecure III. THE ACTIVE-ECTRODE IC The main blocks composing he acive-elecrode s IC are shown in Fig. 3 while able III-A summarizes some main characerisics of IC programming in he differen working modaliies. A curren limiing resisor is placed on he inpu signal pah o guaranee paien safey. For he same reason, bu in order o allow a higher AC curren value for EIT injecion, he EIT curren source is conneced o he elecrode hrough a de-coupling capacior. The inpu sage of he readou secion consiss of wo inpu mixers. In normal operaion, he mixers run a f EIT - 1 KHz and 2 KHz for respecively downconvering he EIT signal around 1 KHz and up-convering he EEG signal. The wo signals are hen subraced by a differenial amplifier based on a DDA. If only he EEG signal is required, he mixers are driven in couner-phase by 1 KHz square wave. Since he EEG signal already drops below sysem noise level a frequencies higher han a few hundred Hz and EIT is a slowly modulaed signal relaed o eiher he head srucure or he meabolism, here is no risk of he wo signals overlapping in normal condiions. High-frequency conen in EEG signals migh be associaed wih large arifacs due o elecrode movemen which can lead o overlapping. However, i should be noed ha EIT is by iself very sensiive o his sor of arifac [6] which should in any case be minimized. The digial porion of he IC is mainly comprised of an inpu inerface which acquires programming daa from he back-end, some regisers for soring configuraion bis and a 512x10 bi Sequenial Access Memory (SAM), which sores he samples for direc synhesis of he EIT curren waveform (8 bi digial word) plus digial signals M1 and M2 which conrol he mixers for inpu signal down- and up-conversion. The memory can be read a a frequency ranging from 2 KHz (if only he EEG signal is acquired and he highes frequency signals required are M1 and M2 which are 1 KHz square wave) o 512 KHz

5 PRE-PRINT VERSION. TO APPEAR IN IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS 5 Config f CK f M1 f M2 f EIT (inj. curren) I AV DD OUT Specrum EEG EEG Readou 2 KHz 1 KHz 1 KHz µa ESI ESI EEG+EIT Readou 32 o 512 KHz f EIT - 1 KHz 2 KHz µa ESI EIT Injecion 32 o 512 KHz KHz o f CK /2 380 µa TABLE I SUMMARY OF IC S MAIN CHARACTERISTICS FOR DIFFERENT CONFIGURATIONS 1 KHz EIT 1 KHz EEG 2 KHz ESI (memory cycled every 1 ms). In order o minimize coupling of digial noise o he analog circuis, digial power is separaed from he analog power supply and is derived from recificaion of he DATA signal by means of a low-hreshold (30 mv) Shoky diode and a 1 nf capaciance. An inernal bandgap reference volage provides he required reference currens. Two differen bias currens are foreseen; a 1 µa curren which is used as he reference curren for he analog readou circui and a higher accuracy 65 µa branch which is urned on only when he elecrode is acing as an EIT curren source. Elecrode-Skin conac impedance monioring is performed I I 1 2 V 1 2 M1 M2 I 1 I 2 I 3 pulse from he readou circui. This happens for one fourh of he ime due o he 50% duy-cycle of M1 and M2 and does no require modificaion in he readou circui behavior. Neverheless, since he elecrode-skin conac impedance has a significan reacive componen a 250 Hz, he differenial signal V 1 2 generaed by he curren injecion is sill upconvered o around 2 KHz by M2, ogeher wih he baseband EEG signal. Higher-order harmonics of he differenial signal are markedly aenuaed before being up-convered in heir urn. The shape of he injeced curren is chosen for wo reasons. The firs is o minimize he effec of curren injecion on he readou of EIT and EEG signals. The second is ha, since a he injecion frequency he issue s elecrical behavior is generally resisive raher han reacive [26], he porion of he volage drop associaed wih issue impedance is no upconvered. This is especially imporan when simulaneously scanning a high number of elecrodes since, even hough issue impedance is generally a leas wo orders of magniude lower han conac impedance, he aggregae effec of muliple injecions on every elecrode could easily affec he conac impedance measuremen. Z Rs I 1 Rp Cp Vhcp I 2 I 4 V ms Fig. 4. Working principle, circui model and iming of elecrode-skin conac impedance measuremen. Curren sources are only urned on when he inpu is disconneced from he DDA by he inpu mixers. a he same ime as he EEG/EIT readou and simulaneously on all elecrodes. The monioring is based on injecing a very small AC es curren beween adjacen elecrodes and measuring he differenial volage a he injecion frequency across he wo elecrodes (see Fig. 4). This will be given by he sum of he wo conac impedances plus he conribuion of issue impedance. The defaul value of he injecion frequency is chosen o be 250 Hz, which is close o he EEG frequency range in order o have a good esimae for is low frequency value wihou overlapping he EEG signal. Tes curren is injeced in small pulses of 1 µa wih a very low duy-cycle and only when boh signals conrolling he inpu mixers (M1 and M2) are se o zero, so ha he elecrode is disconneced B. Readou secion circui design The readou secion is based on a DDA (see Fig. 5), which was firs inroduced in [27]. I is basically an exension of a sandard operaional amplifier wih wo differenial inpus. Using his block o design an insrumenaion amplifier allows boh inpus o show a high-impedance, wihou he need for eiher wo addiional buffers a he inpus (such as in [16]) or hree-opamp srucures. In wha follows, since we are ineresed in having a good closed loop gain accuracy o mach CMRR specificaions (see (2)), we will perform a gain variaion analysis due o parasiic capaciances and process mismaches. Characerizaion of he block in erms of noise, DC gain and frequency behavior can be readily derived from ha of he OpAmp opology on which i is based, so i will no be carried ou here. Going on o consider parasiic capaciances and assuming an infinie gain for he DDA, he raio beween oupu and inpu differenial volage for he AC coupled differenial amplifier shown in Fig. 5(b) will be: v o v 1 v 2 = [ 1 + C 1 + α (C 1 + C 2 ) + C in C 2 ] C 0 C 0 (1 + α) + C in (8)

6 PRE-PRINT VERSION. TO APPEAR IN IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS 6 V pf V V V p1 m1 p2 Vm2 Vo V 2 V1 C 0 C0 V m1 V p2 α C +C 0 in C 2 Vo V pf 80 pf DDA 20 pf V o C 1 α (C +C )+C 1 2 in DC loop (a) (b) (c) Fig. 5. (a) DDA symbol and (b) differenial amplifier based on DDA. Capaciance C 0 is added o cancel parasiic effecs a DDA inpu nodes. (c) Implemenaion of he differenial amplifier in he acive-elecrode s IC. where α is he raio beween he parasiic capaciance associaed wih he op-plae of each capacior and he capaciance iself, while C in is he inpu capaciance of he DDA. Neglecing non-idealiies (α = 0, C in = 0), he equaion reduces v o v 1 v 2 o = 1 + C1 C 2 which is he same as for a non-invering configuraion of a sandard operaional amplifier. From (8), i can easily be seen ha he deviaion of gain from he expeced value due o parasiic effecs is canceled when C 0 = C 1 +C 2. Based on (7), which is sill valid even if he OpAmp is subsiued by a DDA, he gain of he differenial amplifier has been limied o 5, wih capaciance values of C 1 = 80 pf, C 2 = 20 pf and C 0 = 100 pf, argeing a CMRR of a leas 70 db. This leads o a conversion gain from he elecrode o he IC oupu of 10/π. This value is high enough o significanly relax he rade off beween noise and power in he following sages in he back-end. We can consider he overall noise in EEG acquisiion o be due o he sum of ha of wo acive-elecrodes (v n,ae ) plus ha of he differenial amplifier in he back-end (v n,be, see Fig. 2 v 2 n,ae + (π/10 v n,be) 2. The overall 1), namely v n = noise budge is 0.5µV RMS ; if we allow he differenial amplifier o have an inpu-referred noise of up o 0.5µV RMS, he inpu-referred noise level for each of he acive-elecrodes can be compued o be 0.34µV RMS. If we assume a conservaive value of 10 for he noise efficiency facor (NEF, [24]) of he differenial amplifier in he back-end, we can expec is curren consumpion o be approximaely 27 µa. As will be made clearer laer in he paper, his value is less han one-fourh of he curren consumpion of a single acive-elecrode. Fig. 5(c) shows he acual implemenaion of he differenial 3/10 1uA 2000/0.5 Vm2 2000/0.5 Vm1 500/50 600/100 V x V y 2000/0.5 Vp1 500/50 600/100 60/ /0.5 Vp2 15/ /1 V ou v x gm (v v ) 1 m1 x gm (v v ) 3 m2 y 1:1+γ v y gm (v v ) gm (v v ) 2 p1 x 4 p2 y Fig. 7. Small signal model of DDA firs sage. γ represens he mismach beween curren mirror inpu and oupu currens. plifier, mismach in he ransconducances of he differenial couples in he proposed circui is an issue since i can aler gain accuracy (as will be demonsraed in wha follows), degrading he CMRR as discussed in Sec. II. The oupu volage of he DDA-based differenial amplifier is: v o = A v1 v p1 + A v2 v m1 + A v3 v p2 + A v4 v o C 2 C 1 + C 2 (9) where A vi is he DDA open-loop DC gain from each of he four inpus o he oupu. The closed loop DC gain from each of he hree inpus o he oupu will be: amplifier where MOS pseudo-resisors are added for DC biasing of he inpu nodes. Since he inpu sage of he DDA is based on p-channel MOS differenial pairs, he DC gain was fixed o 2 by means of a DC loop wih a low-power (4 µa curren consumpion) acive elemen, so ha he oupu DC volage will be wice ha of he inpu. Fixing he paien s common mode o 1.5 V, he DC value of he elecrode oupu will be 3 V; his guaranees ha he differenial couples of he DDA will operae correcly. The complee DDA is depiced in Fig. 6. The firs sage is composed of wo differenial couples, whose oupu currens are summed on he oupu node and are followed by a common source sage. A hird sage, a common drain, is needed o shif he oupu volage since i is also used as V DD of he analog circuis and of he DDA iself. Unlike wha happens in an OpAmp-based differenial ami o Fig. 6. Schemaic and ransisor sizing of he DDA. Power supply volage is fixed by he oupu iself, which is DC biased by an exernal curren source. A CL,i = vo v i vj=0,j i = = Avi A v4 A vi (C 1+C 2) C 1+C 2 C 2A v4 (C 1+C 2) (10) C 2 C 1 +C 2 A v4

7 PRE-PRINT VERSION. TO APPEAR IN IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS 7 for v i,j = v p1, v m1, v p2. Linearizing he DDA firs sage (see Fig. 7), neglecing oupu conducances and assuming each ransconducance o have a differen value due o mismach, he ransconducances from each inpu o he oupu curren will be: Gm 1 = io v p1 vm1=v m2=v p2=0 Gm 2 = i o v m1 vp1=v m2=v p2=0 Gm 3 = io v p2 vm1=v p1=v m2=0 = gm1gm2(2+γ) gm 1+gm 2 = gm1gm2(2+γ) gm 1+gm 2 = gm3gm4(2+γ) gm 3+gm 4 i Gm 4 = o v m2 = vm1=v gm3gm4(2+γ) gm 3+gm 4 p1=v p2=0 (11) where γ models he curren mirror mismach. Now, assuming ha he DDA oupu volage is given by v o = i o ( R o ) where R o represens he produc of he oupu resisance a he firs sage and he gain of he following sages, i is A vi = G mi R o. Combining his wih (11) and subsiuing in (10), one ges: A CL,1 = vo = v p1 vm1=v p2=0 C 1+C 2 C 2 C 1 +C 2 A v4 A CL,2 = vo v m1 vp1=v p2=0 = C1+C2 C 2 C 1 +C 2 A v4 A CL,3 = vo v p2 vm1=v p1=0 = (gm1gm2)(gm3+gm4) (gm 1+gm 2)(gm 3gm 4) (gm1gm2)(gm3+gm4) (gm 1+gm 2)(gm 3gm 4) C1+C2 C 2 C 1 +C 2 A v4 (12) As defined in (2), he CMRR is relaed o a mismach beween he gains of differen ICs. From (12), one can observe how gain accuracy is no influenced, a firs order, by mismaches in he curren mirror. On he oher hand, since here can be a significan spread in A v4 among differen ICs due o process variaions in MOS parameers, A v4 accuracy can no be high enough o guaranee a good mach in A CL,i beween differen elecrodes. Hence, he only way o guaranee a high CMRR for he sysem is o have a high open loop gain A v,4 so ha C1+C2 A v4 << C2, jus as would happen for an OpAmp based amplifier. To his end, he gain-bandwidh produc of he DDA was fixed o 7 MHz, in order o guaranee a closed loop gain accuracy of more han 70 db in he signal bandwidh. I should also be poined ou how, while he gain A CL,3 from he inpu sharing he differenial couple wih he feedback volage (v p2, conneced o v 1 ) is no affeced by mismaches in he acive elemens, he oher wo gains (A CL,1 from inpu v p1 and A CL,2 from inpu v m1 which is conneced o v 2 ) are. In he design under consideraion (see Fig.5), his means ha while one channel (i.e. v 1, whose gain is A CL,3 ) has a CMRR which is, a firs order, limied only by passive componen mismaches, he oher channel s CMRR (i.e. v 2, whose gain is A CL,2 ) also degrades hrough mismaches in he acive elemens. Since he EIT signal differs from he EEG in ha is CMRR is no increased by he DRL loop as discussed in Sec. II, he EIT signal is amplified hrough he firs channel which ensures he bes performance. Assuming a maximum ransconducance deviaion of ± g m from he average value g m, a lile algebra enables he maximum and minimum values of A CL,1,2 o be compued respecively as: C 1+C 2 (gm gm) C 2 max(a CL,1,2 ) = (gm+ gm) min(a CL,1,2 ) = (gm gm) (gm+ gm) C 1+C 2 C 2 (13) which, when combined, provide he maximum variaion in closed loop gain: A CL,1,2 = 4gm gm A CL,1,2 gm 2 gm 2 4 gm gm (14) Following his resul, careful design wen ino coherenly sizing he curren sources and differenial couple MOS ransisors in order o provide he required accuracy. Final uning was based on MoneCarlo simulaion and careful layouing was carried ou on differenial pairs, curren sources and capaciances so as o minimize mismaches. Simulaions show how he chosen componen sizing leads o an accuracy which is limied by he mismaches in curren sources and capaciors, hence mainly by he chip area which is available. C. EIT and ESI curren sources 127 posiive and 127 negaive curren sources like he one depiced in Fig. 8(a) are grouped in 7 blocks of 64, 32, 16, 8, 4, 2 and 1 source respecively, each conrolled by one of he 7 UP and 7 DOWN signals coming from he digial secion of he IC. An 8-bi binary word is sored in he inernal memory and conains 512 samples of oupu curren. The oupu curren lies beween -127 and +127 µa, and is conrolled in seps of 1 µa. Since he memory can be read a a frequency up o 512 KHz, he maximum represenable frequency conen is 256 KHz (wihou considering higher order harmonics). The EIT signal is down-convered in he inpu mixer by muliplicaion by a square wave a frequency f M1, where f M1 is a submuliple of he memory clock. The synhesized curren is normally chosen o be a digiized sinusoidal wave a f EIT = f M1 + 1 KHz. More complex curren waveforms can be used o simulaneously apply muliple curren paerns adoping frequencydivision or code-division muliplexing [25]. The reference curren is fixed o 65 µa, which is equal o 65 imes he curren generaed by he single curren source. This reference curren and he sizing of curren source ransisors were chosen so as o guaranee ha he maximum absolue error in he generaed curren was below 1 µa. In order o have a highspeed urn on and off of each curren source, he drain volage of he ransisors was kep equal o he average volage of he curren source oupu. In his way he parasiic capaciance on he drain node, which has a high value due o large ransisor sizing for curren accuracy and low flicker noise, is always kep approx. a he oupu volage. This is achieved by he feedback loop in Fig. 8(a), which is based on a lowpower operaion amplifier (4µA bias curren) and an off-chip capacior. The oupu node of he curren source is AC coupled o he elecrode by means of a 100 nf off-chip capacior. This is done o preven DC curren from flowing hrough he paien whenever he clock signal is sopped due o, for example, cable inerrupion or a failure in he back-end driving circui. Curren consumpion of he block responsible for EIT curren injecion is 260 µa, which is required only when he IC is

8 PRE-PRINT VERSION. TO APPEAR IN IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS 8 65 ua UP 7.5/23 1 ua UP CURRENT SOURCE OUTPUT ECTRODE Conrol signal 1 KHz pulses from memory 250 Hz pulses 7.5/23 65 ua DOWN DOWN OFF CHIP CAPACITORS Q Q Q D Q D Q D Q 1uA ECTRODE 4.5/38 1 ua 1uA 250 Hz pulses 4.5/38 (a) (b) Fig. 8. (a) EIT curren sources. Bias curren is derived from a high accuracy reference curren. (b) Diagram of ESI conrol logic and curren sources. The inpu signal is he LSB of he EIT curren source conrol word (ESI is only preformed when he elecrode is programmed for EEG/EIT readou, no for EIT injecion). Since memory is looped every 1 ms, he sequenial circui reduces he pulse frequency by a facor of 4 o produce a 250 Hz signal. effecively programmed o deliver curren o he elecrode. For ESI measuremen, he injeced curren waveform is deermined from one bi of he digial word sored in he memory. Since he memory is cycled every 1 ms during normal operaion wih a simulaneous EEG/EIT signal readou, in order o be able o injec ESI curren a lower frequencies alernae posiive and negaive pulses are generaed once every four pulses deeced on he inpu signal by he digial circui depiced in Fig. 8(b). The curren source is a replica of one branch used for EIT. D. Digial secion DAY LINE CK DATA WE DAY SET 512 x 10 SAM ADDRESS GENERATOR MEM DATA MEM CTRL 2 bi MUX DATA WORD ADDITIONAL PROG BITS 0 0 ADDRESS CURRENT SOURCES CONTROL LOGIC 10 bi REGISTERS M1 M2 UP<1:8> DOWN<1:8> } TO MIXERS } ESI CONTROL TO EIT CURRENT SOURCES Fig. 9. Digial porion of he IC. This comprises a programmable delay line for he clock signal and a serial inerface for wriing programming words on four 10-bi regisers. The sequenial access memory conains samples of EIT curren waveform for direc synhesis and inpu mixer conrol signals M1 and M2. The digial secion of he IC is depiced in Fig. 9. The core is he 512x10 bi SAM which is sequenially addressed in boh reading and wriing phases. During normal operaion, words sored in memory are read sequenially o deermine he insananeous value of he EIT injeced curren and he value of signals M1 and M2 which drive he inpu mixer of he readou circui. The ime insan a which curren sources and mixers swich can be modified by acing on he programmable delay line, which is provided in order o compensae for he differen iming a which clock edges occur on differen elecrodes due o variabiliy in line driver capabiliy and load (i.e. cable capaciance). Depending on process corners, power supply and emperaure, he seps by which he delay can be modified are comprised beween approximaely 500 ps and 1 ns, for an overall delay which lies beween 16 and 32 ns. An inpu inerface is designed o sore he elecrode programming daa on four 10-bi regisers. Daa are wrien by means of one serial daa signal and one clock signal. The digial inerface firs convers he serial daa sream ino a parallel 14-bi word. The inpu shif-regiser coninuously samples he daa signal; o idenify ha a new word is ready o be wrien on one of he four inernal regisers, he firs and las bis of he shif regiser need o be equal o zero. The regiser on which o wrie he new word is deermined by wo address bis, while he remaining en bis provide he word o be wrien. The firs regiser allows one o provide he programmable delay in he clock signal. The second regiser conains he daa word o be wrien in he memory during wrie phases, while he hird and fourh conain he configuraion bis for memory read/wrie operaions and addiional configuraion bis. Complee wriing of he SAM requires less han 35 ms. A. Elecrical characerizaion IV. IC MEASUREMENTS The IC is fabricaed in 0.35 µm sandard CMOS echnology, 3.3 V supply volage. The die (see Fig. 10) is 2x2 mm 2 in size and is encapsulaed in a 5 by 5 mm 2 QFN plasic package. Performance values in erms of inpu referred noise are given in Fig. 11 for simulaneous acquisiion of EEG and EIT signals. Since each elecrode performs single-ended amplificaion, in order o evaluae noise a he inpu of he backend ADC (see Fig. 1), he es seup is composed of an inpu DC signal conneced o wo ICs whose oupus are subraced by an insrumenaion amplifier for medical applicaions. The flicker noise corner frequency is around 200 Hz, so ha EEG and EIT signals are boh effecively placed in regions of he specrum where hermal noise dominaes. The upper-lef graph of Fig. 11 shows noise specral densiy, wih M2 running a 2 KHz for EEG signal up-conversion. The inpu referred noise is 0.56 µv RMS for he EEG signal inegraed beween 0.5

9 PRE-PRINT VERSION. TO APPEAR IN IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS 9 Fig. 10. Die phoograph. The IC area is 4 mm 2. Inpu referred noise [V/sqr(Hz)] 1µ 100n EEG Band (0-100 Hz) 10n µ 100n KHz 10n µ 100n KHz 10n µ 100n KHz 10n Frequency [Hz] Fig. 11. Inpu referred noise for he acquisiion of EEG (upper-lef graph) and EIT signals (remaining hree graphs, for differen injecion frequencies), once down-convered o base-band. CMRR [db] CMRR [db] Inpu Frequency [Hz] EIT Signal 80 w/o CK delay comp. 70 w/ CK delay comp EEG Signal 20 16K 32K 64K 128K 256K Injecion Frequency [KHz] Fig. 12. Common Mode Rejecion Raio for he readou of EEG and EIT signals. For EIT, CMRR degrades as frequency increases. Calibraion of clock delay line parially compensaes he effec, improving he CMRR value. and 100 Hz. The oher hree graphs show he equivalen inpu noise for EIT signal a differen injecion frequencies; i can be seen ha he noise level is slighly higher han for EEG. If only one signal ype is required (eiher EEG or EIT), M1 and M2 are driven in couner-phase, doubling he oupu signal and herefore approximaely halving he inpu referred noise level o 0.28 µv RMS for EEG signal acquisiion. CMRR measured performances are presened in Fig. 12 by measuring he oupu volage mismach of wo aciveelecrodes wih he same sinusoidal inpu signal of 50 mv peak-o-peak ampliude. This is a reasonable value for Hz common mode signals once reducion of hem due o DRL implemenaion is aken ino accoun [23]. The CMRR is characerized for every combinaion of elecrodes among a se of 8; resuls are presened for he wors case. The EEG channel is characerized by a slighly lower CMRR han he expeced 70 db, being abou 64 db a Hz. A very low frequency, he CMRR degrades due o he presence of pseudo-resisors in parallel wih he capaciances which se he amplifier gain. As expeced from wha was said in Sec. III-B, he EIT channel is characerized by a beer CMRR a low frequency (68 db for a 16 KHz inpu signal). This value degrades wih increasing frequency down o less han 40 db a 256 KHz. This is mainly due o he ime delay beween clock signals reaching differen elecrodes. Afer calibraion is performed by programming he delay line in he digial secion, CMRR is resored o 60 db a 64 KHz and increased o 50 db a 256 KHz. A comparison beween performances of he IC presened and oher acive-elecrode s ICs repored in he lieraure is presened in Table II hough for EEG signal readou only, since only [16] performs join EEG-EIT signal readou and curren injecion. One should noice how he noise efficiency facor (NEF, [24]) is in-line wih ha repored in [15] (which however is no able o measure EIT or ESI) and almos one hird of ha in [16], due o he use of one DDA insead of muliple OpAmps. By conras, he NEF value is quie high when compared o low-power differenial insrumenaion amplifiers such as [24] due o he decision no o ake he reference signal o every elecrode, as well as he need o be able o acquire EEG and high frequency EIT simulaneously. The CMRR for his work is similar o ha of [16] and higher han ha of he oher acive-elecrode soluion [15] in he absence of feedback echniques. However his value is high enough o be increased by DRL o similar or higher levels [12][23]. [24] [15] [16] This Work Curren [µa] Z 50Hz [Ω] - 10 G >100 M >100 M CMRR [db] (+30) Noise [µv rms] (Band) ( (0.5- (0.5- ( Hz) -100 Hz) -100 Hz) -100 Hz) NEF Acive-elecrode No Yes Yes Yes TABLE II COMPARISON OF EEG READOUT PERFORMANCES AS COMPARED TO PREVIOUS WORK REPORTED IN THE LITERATURE. IN BRACKETS IN [15], THE CMRR IMPROVEMENT DUE TO FEEDBACK TECHNIQUES.

10 PRE-PRINT VERSION. TO APPEAR IN IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS 10 EIT characerizaion is shown in Fig. 13(a) by injecing a 64 KHz curren wih variable ampliude ino a resisive load R LOAD of eiher 150 Ω or 1050 Ω, wih R = 500 Ω (see Fig. 13(d)). A second IC down-convers he volage across he resisor esing lineariy and frequency behavior of boh curren injecion and signal condiioning sages. Deviaions from expeced values were confined below 0.5% in every condiion esed. Fig. 13(b) shows a similar es, considering a variable conac impedance R. Even when increasing o values significanly higher han sandard conac impedance value a EIT frequencies, he injeced curren is only slighly modified. The mismach in currens injeced by wo differen ICs is measured in Fig. 13(c) as a funcion of ampliude, wih an injecion frequency of 64 KHz. The mismach is confined below 1% and 1 µa. ESI measuremen accuracy is repored in Fig. 14. The es is 250 Hz [KΩ] Measured Theoreical Error Tes Impedance Number Fig. 14. ESI characerizaion by measuremen of 25 known es impedances like he one in Fig. 4, wih R s=1 KΩ, 30 KΩ < R p < 120 KΩ, 10 nf < C p < 90 nf [28]. For common values of he hree parameers (R s 1 KΩ, R p 50 KΩ, C p 30 nf for he series of wo Ag/AgCl elecrodes wihou skin abrasion, corresponding o es impedance number 8) he error is lower han 10% Error [%] Fig. 15. The EEG signal is acquired in he righ occipial posiion O 2, wih reference on Fp z. Alpha waves in he 8-13 Hz range are visible when he subjec has his eyes closed in he firs half of recording (ligher ones correspond o higher power specral densiy in he shor ime Fourier ransform graph). is lower han 10%. Fig. 13. Tesing of EIT curren generaion and volage down-conversion. IC1 (and IC3 where needed) generaes he high frequency curren, IC2 downconvers he volage produced on a es resisor. (a) shows he lineariy of boh operaion for increasing curren ampliude wih wo differen R LOAD and R = 500Ω. (b) shows how upon increasing R o values significanly higher han sandard conac impedance a EIT frequencies, injeced curren is no modified significanly. (c) shows he mismach beween wo opposie currens injeced on he same node. The es seup is depiced in (d)-lef for (a) and (b), and (d)-righ for (c). performed by injecing he curren on known impedances. As expeced and discussed in Sec. III-A, he error in he compued impedance increases when he load is mainly resisive (hough always remaining lower han 20%) while, for more common values of he parameers (R s, R p and C p in Fig. 4), he error B. Funcional characerizaion Fig. 15 shows he funcionaliy in he acquisiion of EEG signals. One EEG channel is shown, acquired in he occipial region of he righ hemisphere; alpha waves in he 8-13 Hz range are visible when he subjec has his eyes closed in he firs half of recording. Fig. 16 shows a simple es for simulaneous EEG and ESI measuremen. During EEG acquisiion in he resing sae, he elecrode cable is inenionally pulled so ha he conac impedance increases, as aesed by measuremen. Due o worsening qualiy of he conac impedance, he EEG signal acquired on he elecrode decreases significanly owards he end of he recording. EIT is esed by using he resisive phanom depiced in Fig. 17(a). A resisive nework wih six differen resisor values represens he scalp, skull and gray-whie maer layers; wo resisors in he ouermos layers have differen values o simulae variaions in layer hickness. A 127 µa, 64 KHz curren is injeced beween he hird and ninh elecrodes while 7 elecrodes readou he oupu volage. A 2 KΩ resisor is insered in series wih he elecrode inpu in order o simulae

11 PRE-PRINT VERSION. TO APPEAR IN IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS 11 (a) R.O. R.O. R.O. INJ 3/2R 1 R.O. R.O. 3/2R 3 REF R.O. R 1 R 3 R 5 INJ R 2 R 4 R 6 GREY WHITE MATTER SKULL SKIN Fig. 16. The EEG signal acquired in O 2, wih reference on Fp z. Conac impedance is measured beween O 1 and O 2 and increases during measuremen since he elecrode cable is being pulled, worsening conac qualiy. A sharp increase is visible close o he end of he recording. The EEG signal is of good qualiy a he beginning of he recording, while a he end, he bad conac qualiy gives rise o low frequency oscillaions which make he signal qualiy unaccepable. he conac impedance. Reconsrucion is performed hrough a simple Newon-Raphson non-linear solver. Fig. 17(b) shows he relaive errors in he reconsrucion of resisor values, which are confined below 10%. In a second sep, R 6 is increased by 10% and EIT signal acquisiion is performed again. The difference beween he wo reconsrucion soluions is compued and normalized o each resisor value, in order o esimae he relaive variaion in resisances. Fig. 17(c) shows he deviaion wih respec o he expeced soluion (10% for he inner layer, 0 for he ohers), normalized o each resisor value. For differenial reconsrucion, he error is confined below 4%. Addiionally, an EIT real impedance map reconsrucion is performed in a wo-dimensional es phanom of known properies where a 35 mm diameer objec wih 0.7 S/m conduciviy is placed inside a ank filled wih 1 S/m saline soluion. A 128 µa pp curren a 16 KHz is injeced beween opposie elecrodes, while 10 differen elecrodes read ou volages a a frame rae of 10 Hz. Accuracy of reconsrucion depends no only on he acive-elecrode properies bu on densiy and posiion as well and on he EIT inverse problem solver. Since opimizaion of his lies ouside he scope of his work, we adoped a simple one-sep Gauss-Newon solver wih Tikhonov regularizaion [6]. I can be seen ha he sysem correcly idenifies areas where resisiviy increases. V. CONCLUSIONS Neuroimaging echniques can be roughly divided ino wo groups; he firs one (comprising fmri and PET) is characerized by high spaial resoluion, low emporal resoluion and bulky and expensive hardware. This hampers boh applicabiliy ouside hospial seings and possible applicaions. By conras, EEG source localizaion is characerized by high porabiliy, low cos and he abiliy o reconsruc rapidly varying signals. Unforunaely EEG based imaging suffers from low spaial resoluion, which can be improved by using high densiy sysems and improving he knowledge of he elecrical characerisics of he head issues, which can be provided by EIT. The IC presened here allows one o inegrae EEG and EIT echniques on he same acive-elecrode of a high densiy (b) (c) R R 1 2 R 3 R 4 R 5 R 6 ABSOLUTE IMPEDANCE RECONSTRUCTION R R 1 2 R 3 R 4 R 5 R 6 RATIVE IMPEDANCE RECONSTRUCTION % Ω (390 Ω ) % Ω (180 Ω ) % Ω (2200 Ω ) % Ω (390 Ω ) % Ω (100 Ω ) 363 Ω(390 Ω) 7% 1.9% (0%) 1.9% 2.7% (0%) 2.7% 1.1% (0%) 1.1% 1% (0%) 1% 3.6% (0%) 3.6% 7.3% (10%) 2.7% Fig. 17. (a) EIT is validaed on a es phanom based on a resisor mesh (R 1 =390 Ω, R 2 =180 Ω, R 3 =2200 Ω, R 4 =390 Ω, R 5 =100 Ω, R 6 =390 Ω). Two elecrodes are used for curren injecion (INJ ), 6 plus he reference one for volage readou(r.o. and REF respecively). The six reconsruced resisance value are shown in (b), showing he expeced values (in brackes) and relaive error. In (c), reconsruced variaions are shown wih respec o he previous soluion, when increasing R 6 by 10% of is value. Fig. 18. Impedance map reconsrucion of an 18 cm diameer cylindrical ank, 1 cm high, filled wih a 1 S/m saline soluion and a moving objec wih 0.7 S/m conduciviy. Dark ones correcly idenify regions where resisiviy increases. sysem, each elecrode being able o be programmed a any ime beween EIT curren injecion and EEG/EIT volage readou. During volage readou, he elecrode can also be used o coninuously monior he meal-skin conac impedance in order o evaluae signal qualiy and he possible need o reposiion an elecrode. Wih respec o he soluion presened in [16], performance in erms of power consumpion and noise has been significanly improved wih similar CMRR. The noise level for EEG signal acquisiion inegraed on he 0.5 o 100 Hz bandwidh is 0.56 µv rms when acquired a he same ime as EIT, while i is halved when only EEG is acquired. Curren consumpion of he readou porion of he IC is 120 µa, wih a noise efficiency facor for sandalone EEG signal acquisiion

12 PRE-PRINT VERSION. TO APPEAR IN IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS 12 of 12.5, which is in line wih ha repored in he lieraure for EEG-only acive-elecrodes [15]. REFERENCES [1] C. J. Price, A review and synhesis of he firs 20 years of PET and fmri sudies of heard speech, spoken language and reading, NeuroImage, vol. 62, no. 2, pp , Aug [2] C. M. Michel e al., EEG source imaging, Clin. Neuroph., vol. 115, no. 10, pp , Oc [3] A. Cuso e al., Anaomical alas-guided diffuse opical omography of brain acivaion, NeuroImage, vol. 49, no. 1, pp , Jan [4] G. Lanz e al., Epilepic source localizaion wih high densiy EEG: how many elecrodes are needed?, Clin. Neuroph., vol. 114, no. 1, pp , Jan [5] M. Dannhauer e al., Modeling of he human skull in EEG source analysis, Hum. Brain Map., vol. 32, no. 9, pp , Sep [6] R. H. Bayford, Bioimpedance Tomography (Elecrical Impedance Tomography), Ann. Rev. of Biom. Eng., vol. 8, pp , Aug [7] T. De Marco e al., EIT Forward Problem Parallel Simulaion Environmen wih Anisoropic Tissue and Realisic Elecrode Models, IEEE Trans. on Biom. Eng., vol. 59, no. 5, pp , May [8] I. F. Trianis e al., A muli-frequency bioimpedance measuremen ASIC for elecrical impedance omography, Proc. of ESSCIRC 2011, pp , Sep [9] J. Ferreira, F. Seoane, K. Lindecranz, AD5933-based elecrical bioimpedance specromeer. Towards exile-enabled applicaions,proc. of EMBC 2011, pp , Aug Sep [10] T. Tidswell e al., Three-Dimensional Elecrical Impedance Tomography of Human Brain Aciviy, NeuroImage, vol. 13, no. 2, pp , Feb [11] L. Consaninou e al., High-Power CMOS Curren Driver Wih Accurae Transconducance for Elecrical Impedance Tomography, IEEE Trans. on Biom. Circ. and Sys., pre-prin, doi: /TB- CAS [12] A. C. MeingVanRijn, A. Paper, C. A. Grimbergen, High qualiy recording of bioelecric evens. Par 1: Inerference reducion, heory and pracice, Med. & Biol. Eng. & Compu., no. 28, pp , Sep [13] T. C. Ferree e al., Scalp elecrode impedance, infecion risk, and EEG daa qualiy, Clin. Neuroph., vol. 112, no. 3, pp , Mar [14] A. C. MeingVanRijn e al., Low-cos acive elecrode improves he resoluion in biopoenial recordings, in Proc. of EMBC 1996, [15] J. Xu e al., A 160µW 8-Channel Acive Elecrode Sysem for EEG Monioring, IEEE Trans. on Biom. Circ. and Sys., vol. 5, no. 6, pp , Dec [16] M. Guermandi e al., Acive Elecrode IC combining EEG, Elecrical Impedance Tomography, Coninuous Conac Impedance Measuremen and Power Supply on a Single Wire, in Proc. of ESSCIRC 2011, pp , Sep [17] S. Mira e al., A 700 µw 8-Channel EEG/Conac-impedance Acquisiion Sysem for Dry-elecrodes, in Proc. of Symp. on VLSI Circuis, pp , June [18] M. R. Nuwer e al., IFCN sandards for digial recording of clinical EEG, Elecr. and clin. Neuroph., vol. 106, no. 3, pp , Mar [19] IEC , Medical elecrical equipmen - Par 1: General requiremens for basic safey and essenial performance, 3 rd ediion. [20] A. McEwan e al., A review of errors in muli-frequency EIT insrumenaion, Phys. Meas., vol. 28, no. 7, pp , July [21] M. Goharian e al., A DSP Based Muli-Frequency 3D Elecrical Impedance Tomography Sysem, Ann. of Biom. Eng., vol. 36, no. 9, pp , Sep [22] J. Szynowski, CMRR analysis of insrumenaion amplifiers, Elecr. Le., vol. 19, no. 14, pp , July [23] B. B. Winer, J. G. Webser, Driven-Righ-Leg Circui Design, IEEE Trans. on Biom. Eng., vol. 30, no. 1, pp , Jan [24] R. R. Harrison and C. Charles, A low-power low-noise CMOS amplifier for neural recording applicaions, IEEE J. Solid Sae Circ., vol. 38, no. 6, pp , June [25] A. McEwan e al., Code-Division-Muliplexed Elecrical Impedance Tomography Specroscopy, IEEE Trans. on Biom. Circuis and Sysems, vol.3, no.5, pp , Oc [26] C. Gabriel, S. Gabriel and E. Corhou, The dielecric properies of biological issues: I. Lieraure survey, Phys. in Med. and Biol., vol. 41, no. 11, pp , Nov [27] E. Sackinger, W. Guggenbhul, A Versaile Building Block: The CMOS Differenial Difference Amplifier, IEEE J. of Solid Sae Circ., vol. sc-22, no. 2, pp , April [28] Y. M. Chi, Dry-Conac and Nonconac Biopoenial Elecrodes: Mehodological Review, IEEE Rev. in Biom. Eng., vol. 3, pp , Marco Guermandi received he M.Sc. and Ph.D. degrees from he Universiy of Bologna, Bologna, Ialy, in 2005 and 2009, respecively. Since 2009, he has been wih he Advanced Research Cener on Elecronic Sysems E. De Casro, Universiy of Bologna. His curren research ineress include he design of high-performance applicaion specified inegraed circuis for biomedical applicaions and he developmen of biomedical insrumenaion for neural imaging from bioelecrical daa, boh from hardware and algorihm sandpoin. Robero Cardu was born in Cagliari, Ialy, in He aended he Universiy of Bologna, Bologna, Ialy, receiving his M.Sc and Ph.D degrees in 2008 and 2012, respecively. His research aciviy has been mainly focused on he design of inegraed circuis for biomedical applicaions. Specifically, his main ineres has been on he analog fron end for elecroencephalography (EEG) and elecrical impedance omography (EIT) signal acquisiion. Since 2012 he has been working as an analog IC designer for power managemen applicaions a STMicroelecronics in Milan, Ialy. He is currenly focused on he developmen of innovaive soluions o maximize efficiency in swiched power supplies applicaions. Eleonora Franchi Scarselli (M 98) received he M.S. degree in elecrical engineering and he Ph.D. degree in elecrical engineering and compuer science from he Universiy of Bologna, Bologna, Ialy, in From 1994 o 2004, she was a Research Assisan wih he Faculy of Engineering, Universiy of Bologna, where she has been an Associae Professor since 2005 and she currenly eaches design of digial inegraed circuis. She is wih he Advanced Research Cener on Elecronic Sysems (ARCES) a he same Universiy where she has been and is presenly involved in research aciviies concerning design of circuis and sysem for RF and sensor applicaions, for enabling wireless 3-D communicaion and for biomedical applicaions.

13 PRE-PRINT VERSION. TO APPEAR IN IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS 13 Robero Guerrieri received he Dr.Eng. and Ph.D. degree from he Universiy of Bologna, Ialy, in 1980 and 1986 respecively. Afer working a he Deparmen of Elecrical Engineering and Compuer Sciences of he Universiy of California a Berkeley as Visiing Researcher and a he MIT as visiing scienis, he joined he Universiy of Bologna where he is Full Professor and eaches design of inegraed sysems. His research ineress are in various aspecs of inegraed circui modeling and design, including digial sysems and biomeric sensors, and applicaions of microelecronics o bioechnology. His work on VLSI design has been cied by widely read magazines, such as he Nikkei and Elecronic Design and documened in more han 90 scienific papers. He is Direcor of he join laboraory beween ST Microelecronics and he Universiy of Bologna. In his role, he is involved in he developmen of new microprocessors, compuaional sysems and packaging echnologies for advanced silicon circuis. He has founded wo sar-up companies in he field of biomedical devices for paien monioring in cancer herapy.