SONET / SDH. Block Diagram. COutput Output XTAL HPLL. Figure 1 - Block Diagram
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1 PX7 Dual Frequency HPLL XO PX7 Features Features Description Applications The PX7 is a dual frequency crystal oscillator, XO, based upon ectron s HPLL high performance phase locked loop frequency multiplier ASIC, that combines key digital synthesis techniques with I s proven core analog technology blocks. A standard low frequency crystal provides the reference to the fractionaln synthesizer so that virtually any frequency between 0MHz and 00 MHz can be factory programmed allowing quick turn manufacturing. Industry Standard Package,.0 x 7.0 x.8 mm HPLL High Performance PLL ASIC Typical Jitter 00 fsrms ( khz to 0 MHz) Two Output Frequencies from 0 MHz to 00 MHz Spurious Suppression, 70 dbc Typical. or 3.3 Supply oltage LCMOS, LPECL or LDS Output Configurations Output Enable Compliant to EC RoHS Directive Applications PLL circuits for clock smoothing and frequency translation Description Standard 4 Gigabit Fibre Channel 0 Gigabit Fibre Channel 0GbE LAN / WAN Synchronous Ethernet OC9 Block Diagram SONET / SDH DD COutput Output INCITS 300 INCITS IEEE 80.3ae ITUT G.8 ITUT G.709 GR3CORE Issue4 XTAL LCMOS LPECL LDS HPLL Figure Block Diagram Gnd Page of 9 ectron International 7 Lowell Road, Hudson, NH 030 Tel: 88ECTRON
2 PX7 Dual Frequency HPLL XO Performance Specifications oltage Current Electrical Performance Parameter Test Conditions Symbol Min Typ Max Units 3.3 Option. Option LCMOS LDS LPECL Supply DD.97. I DD Operating Temperature, 3 T OP C Output Enable () IH 0.7 x DD IL 0. Frequency Select () IH 0.7 x DD Nominal Frequency IL 0. LPECL/LDS LCMOS Frequency f N 0 0 Temperature Stability, T A = 40 to +8 C f STAB ±0 ppm Outputs LPECL Output midlevel O DD.4 DD. swing (diff) OD..9 PP LDS Output midlevel O.4..8 swing (diff) OD m PP LCMOS Output OH 0.9 x DD DD Rise/Fall Time (0/80%), Symmetry,3 LPECL/LDS LCMOS with C L = pf LPECL: DD.3 (diff) LDS:. (diff) LCMOS: DD / 00 0 OL 0. x DD t R/ t f 30. SYM 4 0 % Spurious Suppression 70 dbc Jitter (Performance Option N) khz to 0 MHz фj 000 fsrms Jitter (Performance Option A) khz to 0 MHz фj 00 fsrms ma MHz ps ns ] ] 3] 4] ] ] See Standard Frequencies and Ordering Information (Pg 8). Parameters are tested with production test circuit (See Figure for LCMOS, Figure 3 for LPECL and Figure 4 for LDS). Parameters are tested at ambient temperature with test limits guardbanded for specified operating temperature. Measured as the maximum deviation from the best straightline fit, per MIL030. Parameters are described with waveform diagram below (Figure ). Not tested in production, guaranteed by design, verified at qualification. Page of 9 ectron International 7 Lowell Road, Hudson, NH 030 Tel: 88ECTRON
3 PX7 Dual Frequency HPLL XO Test Circuits & Output Waveform nf nf NC 39 Scope Scope 0k k 0k MD MD Figure LCMOS Production Test Circuit Figure 3 LPECL Production Test Circuit t R t F nf Scope 80% s 0% 0k 0k On Time MD Period Figure 4 LDS Production Test Circuit Figure Waveform Diagram Absolute Maximum Ratings Parameter Symbol Ratings Unit Power Supply DD 0 to 3.8 Input Current I IN 00 ma Output Current I OUT ma Output Enable 0 to DD Storage Temperature T STR to C Soldering Temperature / Duration T PEAK / t P 0 / 40 C / sec Page 3 of 9 ectron International 7 Lowell Road, Hudson, NH 030 Tel: 88ECTRON
4 PX7 Dual Frequency HPLL XO LPECL Application Diagrams nf nf Figure Single Resistor Termination Scheme Resistor values are typically 0 to 40 ohms for 3.3 operation and 8 to 0 ohms for. operation. Figure 7 Pull Up Pull Down Termination Resistor values are typically for 3.3 operation For. operation, the resistor to ground is ohms and the resistor to supply is 40 ohms There are numerous application notes on terminating and interfacing LPECL logic and the two most common methods are a single resistor to ground, Figure, and a pullup/pulldown scheme as shown in Figure 7. An AC coupling capacitor is optional, depending on the application and the input logic requirements of the next stage. One of the most important considerations is terminating the Output and Complementary Outputs equally. An unused output should not be left unterminated, and if one of the two outputs is left open it will result in excessive jitter on both. PC board layout must take this and 0 ohm impedance matching into account. Load matching and power supply noise are the main contributors to jitter related problems. LDS Application Diagrams nf nf Receiver Receiver Figure 8 LDS to LDS, internal 00Ω Figure 9 LDS to LDS, External 00Ω and AC block ing caps Some LDS structures have an internal 00 ohm resistor on the input and do not need additional components. One of the most important considerations is terminating the Output and Complementary Outputs equally. An unused output should not be left unterminated, and if one of the two outputs is left open it will result in excessive jitter on both. PC board layout must take this and 0 ohm impedance matching into account. Load matching and power supply noise are the main contributors to jitter related problems. Page 4 of 9 ectron International 7 Lowell Road, Hudson, NH 030 Tel: 88ECTRON
5 PX7 Dual Frequency HPLL XO Typical Characteristics Figure 0 Typical Phase Noise/Jitter Performance INTEGER Mode Page of 9 ectron International 7 Lowell Road, Hudson, NH 030 Tel: 88ECTRON
6 PX7 Dual Frequency HPLL XO Reliability I qualification includes aging at various extreme temperatures, shock and vibration, temperature cycling, and IR reflow simulation. The PX7 family is capable of meeting the following qualification tests: Parameter Environmental Compliance Conditions Mechanical Shock MILSTD883, Method 00 Mechanical ibration MILSTD883, Method 007 Solderability MILSTD883, Method 003 Gross and Fine Leak MILSTD883, Method 04 Resistance to Solvents MILSTD883, Method 0 Moisture Sensitivity Level Handling Precautions IPC/JEDEC JSTD00, MSL Although ESD protection circuitry has been designed into the PX7 proper precautions should be taken when handling and mounting. I employs a human body model (HBM) and a chargeddevice model (CDM) for ESD susceptibility testing and design protection evaluation. ESD Ratings Model Minimum Conditions Human Body Model 000 MILSTD883, Method 30 Charged Device Model 900 JEDEC, JESDC0 Machine Model 00 JEDEC, JESDAA Reflow Profile (IPC/JEDEC JSTD00) Parameter Symbol alue PreHeat Time t S 0 sec Min, 80 sec Max Ramp Up R UP 3 C/sec Max Time Above 7 C t L 0 sec Min, 0 sec Max Time To Peak Temperature T AMBP 480 sec Max Time at 0 C t P 0 sec Min, 40 sec Max Ramp Down R DN C/sec Max The device has been qualified to meet the JEDEC standard for PbFree assembly. The temperatures and time intervals listed are based on the PbFree small body requirements. The temperatures refer to the topside of the package, measured on the package body surface. The PX7 device is hermetically sealed so an aqueous wash is not an issue. Terminal Plating: Electrolytic Ni >.9µm Electrolytic Au > 0.7µm Page of 9 ectron International 7 Lowell Road, Hudson, NH 030 Tel: 88ECTRON
7 PX7 Dual Frequency HPLL XO Outline & Marking Diagram Suggested Pad Layout PX7 YWW CCCCCCC D XX/XX 9g9h Y = Year WW = Week C = Option Codes XX/XX = Frequency/Frequency (See Ordering Info) inch [mm] Pinout LCMOS Output Option Pin # Symbol Function Frequency Select 0 = F = F Output Enable 3 GND Electrical and Lid Ground 4 f O Output Frequency NC No Connection DD Supply oltage 7,8 NC Factory Use Only 9 NC/GND No Connect or Ground, Frequency Select is internally pulled to DD with a 30 kω resistor., Output Enable is internally pulled to DD with a 30 kω resistor. If option C is selected, must be pulled low by the user with a LCMOS logic device or a 3 kω resistor to ground. Pinout LPECL, LDS Output Options Pin # Symbol Function Frequency Select 0 = F = F Output Enable 3 GND Electrical and Lid Ground 4 f O Output Frequency Cf O Complementary Output Frequency DD Supply oltage Output Enable Option Symbol Function Result A C H (3 DD /4) to DD L Gnd to 0. OD H (3 DD /4) to DD OD L Gnd to 0. OD = Outputs Disabled = Outputs Enabled Tape & Reel (EIA48A) Tape Dimensions (mm) Reel Dimensions (mm) Dimension W F Do Po P A B C D N W W # Per Tolerance Typ Typ Typ Typ Typ Typ Min Typ Min Min Typ Max Reel PX Page 7 of 9 ectron International 7 Lowell Road, Hudson, NH 030 Tel: 88ECTRON
8 PX7 Dual Frequency HPLL XO Standard Frequency Table Standard Factory Configurable Frequencies (MHz) EE HH K ND P T DD HD K NP PD TB DX HJ KA NA P TK D JF K N P TA DZ KK KH NM P TE DB J K NG PA TH DK KM K NH PG TF DH KP LH N PN TJ ED LM K N P TU E KT K NE RJ, TM E JB KG N PE E K K N PK Recent Adds: EF JC KJ NF PF NX E JZ KL NL PB W EG KX K NR.00 PC C EB LF KN NC.48 P EH JW KR N R EJ J KU NT 9.38 R E JE LJ.748 NJ R EK JG KW NK R E JM LK NB RT E LG KE NN 7.0 TX EC JK L PT 7.7 R E JY L RX RA E J L P R F J LA PU T.8000 F J L P R F JD L PP R F KD L3 3.0 PW R F LL LC PX R F J LB PY RW FB JP L RB F JU L RC TY F JL LD RD TG F JX LN RY TC HE JR L RF H KY M RU T HF J M RR TW H J MA RE T H J M PM T H LE.0000 M RK T H JJ M TL HC JN M PH TT H JT.383 M P HB JH M PJ T HG J.87 M P T H JA N RH TN H KB N PL T HK KC N PR T H KF NU RG TD Page 8 of 9 ectron International 7 Lowell Road, Hudson, NH 030 Tel: 88ECTRON
9 PX7 Dual Frequency HPLL XO Ordering Information PX 7 H D E H C N A F/F Product Family PX: Dual Frequency XO Package 7: x 7 x.8 mm Supply E: 3.3 H:. Output A: LCMOS C: LPECL D: LDS Operating Temperature E: 40 C to 8 C J: 0 C to 70 C T: 0 C to 70 C F, F (See Standard Frequency Table Performance Option (Future) N: N/A A: 00 fsrms typical Jitter Future N: N/A Enable/Disable A: Enable High C: Enable Low Stability E: ±0 ppm G: ±30 ppm H: ± 3 ppm K: ± 0 ppm S: ± 00 ppm Example: PX7EAJGAANJ9/K (HPLL, Dual Frequency XO, 3.3, LCMOS, 0 to 70 C, ±30ppm, EN=H, F=. MHz, F=77.7 MHz) For Additional Information, Please Contact USA: ectron International 7 Lowell Road Hudson, NH 030 Tel: Fax: Europe: ectron International Landstrasse, D7494 Neckarbischofsheim, Germany Tel: +49 (0) Fax: +49 (0) Asia: 8 Yin Cheng Road(C), nd Floor One Lu Jia Zui Pudong, Shanghai 000, China Tel: Fax: Disclaimer ectron International reserves the right to make changes to the product(s) and or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information. Page 9 of 9 ectron International 7 Lowell Road, Hudson, NH 030 Tel: 88ECTRON
SONET / SDH. Block Diagram. COutput Output XTAL HPLL. OE or NC. Figure 1 - Block Diagram
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