MN6474A. D/A Converter for Digital Audio Equipment. For Audio Equipment. Overview. Pin Assignment. Features. Applications

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1 For Audio Equipment D/A Converter for Digital Audio Equipment Overview The is a CMOS digital-to-analog converter with a built-in 6-bit digital filter for pulse code modulation (PCM) digital audio equipment. It uses noise shaping technology to convert a digital signal into a PWM signal. It contains a 4-fold oversampling digital filter that permits simplification of the low pass filter after the D/A converter, thus greatly reducing the power consumption of the entire D/A conversion system. The chip provides both regular and inverted phase outputs for both channels. The chip contributes to cost and size reductions for CD players and other digital audio equipment. Features Built-in 4-fold oversampling digital filter (ripple of only ± db within the supported band and attenuation of 62.7 db within the cutoff band) Internal resolution of bits Two's complement input (I 2 S input code also supported) Built-in overflow limiter No zero cross distortion Sample-and-hold circuit is unnecessary Output pin for detecting zero input Single 5V power supply Pin Assignment LRPOL LRCLK BCLK SRDATA DV SS3 DV DD 34FS PD MDATA MCLK FS ZFLGB NSUB DV SS2 DV DD2 X X2 DV SS DV DD AV DD MLD RSTB IE TP TP2 TEST TEST2 AV DD4 (TOP VIEW) QFP0-P-44A OUTR() AV SS AV SS2 OUTR() AV DD2 AV DD3 OUTL() AV SS3 AV SS4 OUTL() Applications CD players and other digital audio equipment

2 For Audio Equipment Block Diagram Timing Generator LRPOL LRCLK BCLK SRDATA IE S/P Converter FIR FIR 2 Microcomputer Interface Noise Shaping Logics PWM Logics (R) PWM Logics (L) Analog Block (R) Analog Block (L) 2 4 OUTR() OUTR() OUTL() OUTL() PD MDATA MCLK MLD 40 4 TEST2 TEST TP2 TP ZFLGB 34FS 92FS X X2

3 For Audio Equipment Pin Descriptions Pin No. Symbol Function Description MLD Microcomputer command load input ("L" level to load) 2 RSTB Reset pin (active "L"). Always pull this pin low after applying the power. 3 IE Input format selection pin. "H" level; I 2 S format "L" level; signal processing LSI format. 4 TP Digital filter test output pin. Leave this pin open. 5 TP2 Digital filter test output pin 2. Leave this pin open. 6 TEST Digital filter test input pin. Keep this pin at "L" level. 7 TEST2 Digital filter test input pin 2. Keep this pin at "L" level. No connection Leave these pins open. 9 No connection Leave these pins open. 0 AV DD4 Power supply pin 4 for analog circuits. (5V) OUTL() Left channel inverted phase PWM output pin. 2 AV SS4 Ground pin 4 for analog circuits. 3 AV SS3 Ground pin 3 for analog circuits. 4 OUTL() Left channel normal phase PWM output pin. 5 AV DD3 Power supply pin 3 for analog circuits. (5V) 6 No connection Leave this pin open. 7 AV DD2 Power supply pin 2 for analog circuits. (5V) OUTR() Right channel through phase PWM output pin. 9 AV SS2 Ground pin 2 for analog circuits. 20 AV SS Ground pin for analog circuits. 2 OUTR() Right channel inverted phase PWM output pin. 22 AV DD Power supply pin for analog circuits. (5V) 23 DV DD Power supply pin for digital circuits. (5V) (Power supply for oscillator circuit) 24 DV SS Ground pin for digital circuits. (Ground for oscillator circuit) 25 X2 Crystal oscillator pin. 26 X Crystal oscillator pin. (External clock input pin) 27 No connection Leave this pin open. 2 DV DD2 Power supply pin 2 for analog circuits. (5V) 29 DV SS2 Ground pin 2 for digital circuits. 30 NSUB Connect to D-V DD. (Silicon substrate potential fixing pin) 3 ZFLGB Output pin for detecting zero input FS 92f s (=9.26 MHz)output pin. Max. load capacity: 30 pf. LRPOL LRCLK polarity selection pin. "H" level; selects the left channel "L" level; the right channel. 34 LRCLK LRCLK pin. When the LRPOL pin is at "H" level, "H" level in this pin indicates left channel data input; "L" level indicates right channel data input. When the LRPOL pin is at "L" level, "L" level in this pin indicates left channel data input; "H" level input indicates right channel data input. 35 BCLK Serial input bit clock 36 SRDATA Serial input data (digital) input pin. 37 DV SS3 Ground pin 3 for digital circuits.

4 For Audio Equipment Pin Descriptions (continued) Pin No. Symbol Function Description 3 DV DD Power supply pin for digital circuits. (Silicon substrate potential fixing pin.) (5V) 39 34FS 34f s (=.432 MHz) output pin. Max. load capacitance: 30 pf. 40 PD Power down pin. (active "H") 4 MDATA Microcomputer command data input pin. MCLK Clock input pin for microcomputer command. Conversion Characteristics DV DD =5.0V, DV SS =0V, AV DD =5.0V, AV SS =0V, f=.6mhz, Ta=25 C Parameter Symbol Test Conditions min typ max Unit Analog characteristics Signal-to-noise ratio S/N EIAJ (khz) db Dynamic range D.R. EIAJ (khz) 90 9 db Total harmonic distortion THDN EIAJ (khz) % Crosstalk EIAJ (khz) 90 9 db Output level * khz F.S..4.7 V rms Note*: These analog characteristics are for circuits equivalent to the suggested application circuit.

5 For Audio Equipment Application Circuit Example 7th order L.P.F(HAF 0079) DV SS DV DD AV DD AV SS 5 E 5 C4 47µF th order L.P.F(HAF 0079) R3 0W R4 0W *C5 0µF 24 5pF R2 4.7kW C C3 5pF.6 MHz *C 00µF R 0W R7 kw R5 kw R kw R6 kw C5 47µF R32 470W *C6 0.56µF C pF R9 220W N C0 C3 22µF 22µF C22 C 22µF C2 22µF R34 470kW 0µF C24 R7 R9 AV DD DV DD DV SS X2 X DV DD2 DV SS2 NSUB ZFLGB 92f s AV SS OUTR() AV SS2 OUTR() AV DD2 AV DD3 AV SS3 OUTL() AV SS4 OUTL() LRPOL LRCLK BCLK SRDATA DV SS3 DV DD 34FS PD MDATA MCLK AV DD4 0 9 TEST2 7 TEST 6 TP2 5 TP 4 IE 3 RSTB 2 MLD R32 470W 470W R R23 C2 C29 C3 C32 0µF N N C 0µF R27 0W C34 0pF C35 0pF R2 0W R ch L ch R3 kw C6 R24 C7 IC4 R0 C7 R26 C2 IC2 0µF R 00µF R29 00kW R30 00kW R25 C pF R4 kw R2 C C 0µF R35 470kW N C32 R20 220W C20 C23 C9 0µF C25 R R5 kw R2 *C9 0.56µF IC3 IC S2 S3 S S4 S5 S6 C2 V DD V SS R6 kw R22 *C,C5,C6 and C9 are attached to the rear of the P base. IC to 4 AN655 PD(S3) RSTB(S) IE(S4) Signal processing LSI format Reset "L" I 2 S format Power down mode "H"

6 For Audio Equipment Package Dmensions (Unit: mm) QFP0-P-44A.7± ± (0.65) 4.0±0.2.7±0.4 0 (.92) ±0. 2.2± max (2.35) 0.5 SEATING PLANE 0.±0. (.5±0.2) 0 to 0

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