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1 6-line EMI filter and ESD protection for audio interface Features 4-line EMI filter and ESD protection for internal and external (headset) microphone 2-line EMI filter and ESD protection for headset speaker Benefits EMI (I/O) low-pass filter High efficiency EMI filter Very low PCB space consumption: 4.6 mm 2 Very thin package: 0.65 mm High efficiency in ESD suppression High reliability offered by monolithic integration High reduction of parasitic elements through integration and wafer level packaging Complies with following standards IEC level 4 external pins 15 kv (air discharge) 8 kv (contact discharge) IEC level 1 internal pins 2 kv (air discharge) 2 kv (contact discharge) Applications ESD protection and EMI/RFI filtering for the audio bottom connector interface, where EMI filtering in ESD sensitive equipment is required: Mobile phones and communication systems Wireless modules Description The is a highly integrated device designed to suppress EMI/RFI noise in all systems subjected to electromagnetic interference. The flip chip packaging means the package size is equal to the die size. This filter includes ESD protection circuitry, which prevents damage to the application when it is subjected to ESD surges up to 15 kv. Figure 1. Flip chip package, 20 bumps Pin configuration A B C MIC1P MIC2N MIC2P SPK_R SPK_L MIC1N BIAS1 MIC1P int Int MIC2N int HOOK BIAS2 SPK_L int D MIC1N int BIAS3 MIC2P int SPK_R int PHG Silicon side February 2008 Rev 1 1/14

2 Characteristics 1 Characteristics Figure 2. Circuit schematic Table 1. Symbol V pp MIC2_P-ext MIC2_N-ext -ext MIC1_P-ext MIC1_N-ext SPK_R-ext SPK_L-ext -ext R10 C5 R11 C6 R1 R2 R3 R4 R6 R7 R8 R9 Absolute ratings (limiting values) R12 R13 C1 C2 C3 C4 C1 to C4 = 1.3 nf typical Parameter IEC air discharge on external lines IEC contact discharge on external lines IEC air discharge on internal lines IEC contact discharge on internal lines HOOK BIAS2 MIC2_P-int MIC2_N-int -int BIAS1 MIC1_P-int MIC1_N-int BIAS3 SPK_R-int PHG (Phantom Ground) SPK_L-int Test conditions Min Max Unit P SPK Continuous power dissipation per channel SPK_L, SPK_R T amb = 85 C 180 mw I SPK Continuous current per channel SPK_L, SPK_R T amb = 85 C 135 ma P total Total continuous power dissipation T amb = 85 C 285 mw T op Operating temperature range C T stg Storage temperature range C T j Junction temperature 125 C Table 2. Symbol V BR Electrical characteristics - definitions (T amb = 25 C) Parameters Breakdown voltage I IPP kv I RM Leakage V RM V RM V CL Stand-off voltage Clamping voltage VCL VBR VRM IR IRM IRM IR VRM VBR VCL V R d Dynamic impedance I PP Peak pulse current IPP C line Input capacitance per line 2/14

3 Characteristics Table 3. Electrical characteristics - values (T amb = -40 C to 85 C unless otherwise specified) Symbol Parameter Test conditions Min Typ Max Unit V BR I RM Diode reverse breakdown voltage Leakage current through clamping diodes I R = 1 ma T amb = 25 C V R = 3 V DC per line T amb = 25 C 14.0 V 0.5 µa C1-C4 (1) Capacitance on MIC lines V = 0 V, F = 1 MHz, 1.3 nf C5-C6 (1) Channel Capacitance SPK_L, SPK_R V OSC = 30 mv T amb = 25 C 60 pf R1 (2) Hook Pull up resistance 47 kω R2 (2) External Microphone Pull up resistance 2.2 kω R3,R4, R7, R8 (2) Microphone Serial Resistance 100 Ω R6, R9 (2) Internal Microphone Pull up and 1 kω Pull down resistance R10, R11 (3) SPK Serial Resistance 10 Ω R12, R13 (2) SPK PHG Resistance 15 kω MICx channel THD Distortion 1. Capacitor tolerance ±30% 2. Resistor tolerances ±10% 3. Resistor tolerances ±20% 4. See Figure 20 and Figure 21 V dc = V, (4) F = 20 Hz - 20 khz, R gen = 600 Ω, V out = 1.5 V PP R load = 200 kω, T amb = 25 C Balanced (or differential mode) -75 (A) 3/14

4 Characteristics 1.1 RF filtering The low signal level on the analog inputs and the pulsed transmitter in the phone are a combination that requires efficient RF-filtering. RF-rectification must be avoided. Therefore, the stop band attenuation is optimized for the frequency bands MHz. Table 4. Stop band performance MHz Channel Test conditions Attenuation Min Typ Max Unit MIC1_x to MIC1_x-int R source = 50 Ω, R load = 1 kω 25 MIC2_x to MIC2_x-int R source = 50 Ω, R load = 1 kω 25 MIC1_P to BIAS1 R source = 50 Ω, R load = 1 kω 25 MIC2_P to BIAS2 R source = 50 Ω, R load = 1 kω 25 SPK_x to SPK_x-int R source = 50 Ω, R load = 1 kω 25 Table 5. Channel Stop band performance MHz 1.2 Attenuation characteristics Figure Test conditions Attenuation Min Typ Max Unit MIC1_x to MIC1_x-int R source = 50 Ω, R load = 1 kω 20 MIC2_x to MIC2_x-int R source = 50 Ω, R load = 1 kω 20 MIC1_P to BIAS1 R source = 50 Ω, R load = 1 kω 20 MIC2_P to BIAS2 R source = 50 Ω, R load = 1 kω 20 MIC1_P and MIC1_N lines (50 Ω / 50 Ω) Figure 4. MIC1_P and MIC1_N lines (50 Ω / 1 KΩ simulation) k 1M 10M 100M 1G MIC1_P line MIC1_N line R source = 50 Ω / R load = 50 Ω MIC1_P line MIC1_N line R source = 50 Ω / R load = 1 KΩ -50 4/14

5 Characteristics Figure 5. MIC2_P and MIC2_N lines (50 Ω / 50 Ω) Figure 6. MIC2_P and MIC2_N lines (50 Ω / 1 KΩ simulation) Figure Figure MIC2_P line MIC2_N line SPK_L and SPK_R lines (50 Ω / 50 Ω) 300.0k 1.0M 3.0M 10.0M 30.0M 100.0M 300.0M 1.0G 3.0G f/hz SPK_R line SPK_L line MIC1_P and BIAS1 lines (50 Ω / 50 Ω) k 1M 10M 100M 1G R source = 50 Ω / R load = 50 Ω MIC2_P line MIC2_N line R source = 50 Ω / R load = 1 KΩ Figure Figure 10. SPK_L and SPK_R lines (50 Ω / 1 KΩ simulation) 300.0k 1.0M 3.0M 10.0M 30.0M 100.0M 300.0M 1.0G 3.0G f/hz SPK_R Sim SPK_L line Sim line MIC1_P and BIAS1 lines (50 Ω / 1 KΩ simulation) Mic1P/BIAS1 50 R source = 50 Ω/ R load = 50 Ω R source = 50 Ω / R load = 1 kω Mic1P/BIAS1 1k 5/14

6 Characteristics Figure 11. MIC2_P and BIAS2 lines (50 Ω / 50 Ω) Figure 12. MIC2_P and BIAS2 lines (50 Ω / 1 KΩ simulation) Mic2P/BIAS2 50 R source = 50 Ω/ R load = 50 Ω 1.3 ESD characteristics Figure 13. ESD response to IEC (15 kv air discharge) on input V in and output V out Mic1 line vi = 20 V/d vo = 5 V/d 100 ns/d Figure 15. ESD response to IEC (15 kv air discharge) on input V in and output V out Mic2 line Mic2P/BIAS2 1k R source = 50 Ω / R load = 1 kω Figure 14. ESD response to IEC (-15 kv air discharge) on input V in and output V out Mic1 line vi = 20 V/d vo = 5 V/d 100 ns/d Figure 16. ESD response to IEC (-15 kv air discharge) on input V in and output V out Mic2 line vi = 20 V/d vi = 20 V/d vo = 5 V/d 100 ns/d vo = 5 V/d 100 ns/d 6/14

7 Characteristics 1.4 Filter characteristics Figure 17. Analog crosstalk MIC2_P and MIC1_N lines (50 Ω / 50 Ω) Figure 18. Analog crosstalk SPK_R and MIC2_N lines (50 Ω / 50 Ω) MIC2_N/MIC1_P 1.5 Total harmonic distortion characteristics Figure 19. THDN () Total harmonic distortion and noise Figure 20. with only cables and environmental circuit versus frequency, V BIAS = 0 V VGEN: 1.5 Vp-p 20 Hz < F < 20 khz RGEN: 600 Ω RLOAD: 200 kω A-Weighting filter Bandwidth: 40 khz TAMB = 25 C k k 10 k F (Hz) THDN () SPK_R/MIC2_N Variation of total harmonic distortion and noise in microphone lines versus frequency, balanced (or differential) mode, V BIAS = 0 V VGEN: 1.5 Vp-p V MAX = 0V 20 Hz < F < 20 khz RGEN: 600 Ω RLOAD: 200 kω A-Weighting filter Bandwidth: 40 khz TAMB = 25 C k k 10 k F (Hz) 7/14

8 Characteristics Figure 21. Variation of total harmonic distortion and noise in microphone lines versus frequency, balanced (or differential) mode, V BIAS = 2.4 V Figure 22. Variation of total harmonic distortion and noise in microphone lines versus frequency, unbalanced (or single-ended) mode THDN () THDN () Figure 23. Figure 24. VGEN: 1.5 Vp-p V MAX = 2.4 V 20 Hz < F < 20 khz RGEN: 600 Ω RLOAD: 200 kω A-Weighting filter Bandwidth: 40 khz TAMB = 25 C 1.5 V PP F (Hz) k k 10 k Test setup for measurement of distortion on MIC channels Internal UPV setup schematic 300 Ω 120 pf UPV Rohde & Schwarz audio analyzer MIC1N MIC1N VGEN: 1.5 Vp-p 20 Hz < F < 20 khz RGEN: 600 Ω RLOAD: 100 kω A-Weighting filter Bandwidth: 40 khz TAMB = 25 C XLR connectors MIC1Nint MIC1P MIC1Nint MIC1Pint 120 pf F (Hz) k k 10 k 100 kω To balanced Input amplifier 1.5 V PP 120 pf 120 pf 100 kω 300 Ω MIC1P MIC1Pint To balanced Input amplifier 8/14

9 Application schematics 2 Application schematics Figure 25. Basic configuration scheme Figure 26. MIC2_P MIC2_N MIC1_P MIC1_N SPK_R SPK_L Stereo line in MIC2_P MIC2_N MIC1_P MIC1_N R10 C5 R11 C6 R1 R2 R3 R4 R6 R7 R8 R9 R1 R2 R3 R4 R6 R7 R12 R13 C1 C2 C3 C4 HOOK BIAS2 MIC2_P-int MIC2_N-int -int BIAS1 MIC1_P-int MIC1_N-int BIAS3 SPK_R-int PHG (Phantom Ground) SPK_L-int HOOK BIAS2 MIC2_P-int MIC2_N-int -int BIAS1 MIC1_P-int MIC1_N-int R8 R9 C1 C2 C3 C4 BIAS3 SPK_R R10 SPK_R-int C5 R12 PHG (Phantom Ground) SPK_L R11 C6 R13 SPK_L-int 9/14

10 Application schematics Figure 27. Stereo microphone / line in Figure 28. MIC2_P MIC2_N MIC1_P MIC1_N SPK_R SPK_L R10 C5 R11 C6 R1 R2 R3 R4 R6 R7 R8 R9 HOOK BIAS2 MIC2_P-int MIC2_N-int -int BIAS1 MIC1_P-int MIC1_N-int BIAS3 SPK_R-int SPK_L-int External balanced microphone / stereo line in MIC2_P MIC2_N MIC1_P MIC1_N SPK_R R1 R2 R3 R4 R6 R7 R12 R13 C1 C2 C3 C4 PHG (Phantom Ground) HOOK BIAS2 MIC2_P-int MIC2_N-int -int BIAS1 MIC1_P-int MIC1_N-int R10 R8 R9 C1 C2 C3 C4 BIAS3 SPK_R-int C5 R12 PHG (Phantom Ground) SPK_L R11 C6 R13 SPK_L-int 10/14

11 Ordering information scheme 3 Ordering information scheme Figure 29. Ordering information scheme EMIF yy - xxx zz Fx 4 Package information In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at Figure 30. EMI Filter Number of lines Information 3 letters = application 2 digits = version Package F = Flip-Chip x = 2: Lead free, pitch = 500 µm, bump = 315 µm Flip chip dimensions 500 µm ± µm ± µm ± mm ± 50 µm 650 µm ± mm ± 50 µm 11/14

12 1.75 ± ± ± 0.3 E xxz yww 2.56 E xxz yww E xxz yww Package information Figure 31. Marking Figure 32. Footprint recommendation Dot, ST logo xx = marking z = manufacturing location yww = datecode (y = year ww = week) E x y x w z w Copper pad Diameter: 250µm recommended, 300 µm max Solder stencil opening: 330 µm Solder mask opening recommendation: 340 µm min for 315 µm copper pad diameter Note: Figure 33. Flip chip tape and reel specification 0.73 ± 0.05 All dimensions in mm Dot identifying Pin A1 location 2.0 ± 0.05 More packing information is available in the application notes: AN1235: Flip chip: Package description and recommendations for use AN1751: "EMI Filters: Recommendations and measurements" ST 4.0 ± ST 4 ± 0.1 User direction of unreeling Ø 1.55 ± 0.05 ST 12/14

13 Ordering information 5 Ordering information Table 6. Ordering information Ordering code Marking Package Weight Base qty Delivery mode HP Flip chip 6.45 mg Tape and reel 6 Revision history Table 7. Document revision history Date Revision Changes 18-Feb First issue 13/14

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