Ultra Small, Low Power Consumption Voltage Detector
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1 Ultra Small, Low Power Consumption Voltage Detector FEATURES Accuracy ± 2% at V DF 1.5 V or ±0.03 V Low Power Consumption at 0.6 μa typical at V DF = 2.7 V, V IN = 2.97 V Detect Voltage Range 0.7 V 5.0 V in 0.1 V increments Operating Voltage Range 0.7 V 6.0 V Detect Voltage Temperature Drift ±100 ppm/ 0 C Output Configuration CMOS (Version C) or N- channel Open Drain (N Version) Operating Ambient Temperature C Packages : USP-3 and SSOT-24 EU RoHS Compliant, Pb Free APPLICATIONS Microprocessor reset circuitry Memory battery back-up circuits Power-on reset circuits Power failure detection System battery life and charge voltage monitors DESCRIPTION The are highly precise, low power consumption, CMOS voltage detectors, manufactured using laser trimming technology. With low power consumption and high accuracy, the series is suitable for precision mobile equipment. The in ultra small packages are ideally suited for high-density PC boards. The is available in both CMOS and N- channel open drain output configurations Detector is available in USP-3 and SSOT-24 packages. TYPICAL APPLICATION CIRCUIT TYPICAL PERFORMANCE CHARACTERISTIC Pull-up Resistor R PL used with N-channel output configuaration only Supply Current vs. Input Voltage x272xx PS PRELIMINARY 1
2 ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATINGS UNITS Input Voltage V IN 0.3 ~ +7.0 V Output Current I OUT 10 ma Output Voltage Power Dissipation 2) CMOS Output V OUT 0.3 ~ V IN V N-channel Open Drain 0.3 ~ +7.0 V USP-3 P D 120 SSOT Operating Temperature Range T OPR 40 ~ + 85 Storage Temperature Range T STG 55 ~ +125 All voltages are in respect to V SS ELECTRICAL OPERATING CHARACTERISTICS NOTE: mw 0 C 0 C Ta = 25 0 C PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT CIRCUIT Operating Voltage V IN V DF(T) = V 1) V Detect Voltage V DF V DF(T) = V E-1 2) V Hysteresis Width V HYS V DF(T) = V V DF x V DF x V DF x V Supply Current1 I SS1 V IN = V DF(T) x 1.1 E - 2 2) µa Supply Current2 I SS2 V IN = V DF(T) x 0.9 E - 3 2) µa Output Current I OUTN I OUTP 3) V IN = 0.7 V V OUT = 0.5 V V OUT = 0.3 V V OUT = 0.1 V V IN = 1.0 V V OUT = 0.1 V, 1.0 V < V DF(T) 2.0 V V IN = 2.0 V V OUT = 0.1 V, 2.0 V < V DF(T) 3.0 V V IN = 3.0 V V OUT = 0.1 V, 3.0 V < V DF(T) 4.0 V V IN = 4.0 V V OUT = 0.1 V, 4.0 V < V DF(T) 1, V IN = 6.0 V V OUT = 5.5 V Leakage Current I LEAK Version C V IN = V DF(T) x 0.9, V OUT = 0 V Version N V IN = 6.0 V, V OUT = 6.0 V µa Detect Voltage Temperature C T OPR 85 0 C ± 100 ppm/ 0 C Characteristics Detect Delay Time 4) t DF V IN = 6.0 V 0.7 V, from V IN = V DF to V OUT = 0.5 V µs Release Delay Time 5) t DR V IN = 0.7 V 6.0 V, from V IN = V DR to V OUT = V DR 6) ma µs 1) V DF(T) is a nominal detect voltage 2) Please refer to the table named Detect Voltage Accuracy and Supply Current Specifications 3) C version only 4) Delay time from the moment, when V IN = V DF to the moment, when V OUT = 0.5 V, at V IN falling from 6.0 V to 0.7 V 5) Delay time from the moment, when V IN = V DR to the moment, when V OUT = V DR 6) Release voltage (V DR = V DF + V HYS) PS PRELIMINARY 2
3 ELECTRICAL OPERATING CHARACTERISTICS (CONTINUED) Detect Voltage Accuracy and Supply Current Specification SYMBOL E-1 E-2 E-3 NOMINAL DETECT VOLTAGE DETECT VOLTAGE V DF (V) SUPPLY CURRENT1 I SS1 (μa) SUPPLY CURRENT2 I SS2 (μa) V DF(T) MIN. MAX. TYP. MAX. TYP. MAX PS PRELIMINARY 3
4 PIN CONFIGURATION PIN ASSIGNMENT USP-3 (BOTTOM VIEW) SSOT-24 (TOP VIEW) PIN NUMBER USP-3 SSOT-24 PIN NAME FUNCTIONS 1 4 V IN Power Input 2 3 V OUT Output Voltage (Detect LOW ) 3 2 V SS Ground 1 NC No Connection BLOCK DIAGRAM C N Diodes inside the circuits are ESD protection diodes and parasitic diodes. BASIC OPERATION Operation of the in a typical application circuit is exlained by the timing diagram shown below. Note: To simplfy explanation, an operation time of the circuit is not included. PS PRELIMINARY 4
5 When input voltage V IN is higher than detect voltage V DF, output voltage V OUT is equal input voltage V IN. (Output of the N version with N-channel open drain is in high impedance state.) When input voltage V IN falls below detect voltage V DF, output voltage V OUT becomes equal to the ground voltage V SS level. When input voltage V IN falls below minimum operating voltage V MIN, output becomes unstable. In this condition, V OUT is equal pull-up voltage, which is V IN in typical application. When input voltage V IN rises above the minimum operating voltage V MIN, output keeps the ground voltage level V SS, until V IN becomes equal or higher than a release voltage V DR. When the input voltage V IN rises above the release voltage V DR, output voltage V OUT becomes equal to the input voltage V IN. (Output of the N version with N-channel open drain is in high impedance state.) The difference between V DR and V DF represents the hysteresis width. TYPICAL APPLICATION CIRCUIT C LAYOUT AND USE CONSIDERATIONS N 1. The IC may malfunction if absolute maximum ratings are exceeded. 2. To stabilize the IC's operations, please, ensure that V IN rise and fall times are more than several μs/v. 3. N version with N-channel open drain configuration is recommended, when a resistive divider is used to set V IN voltage (see figure below). Voltage drop at resistor R IN caused by supply and load currents, changes level of detect and release voltages. Those errors are not constant because of the fluctuation of currents. In addition, oscillation may occur if voltage drop caused by load or transient current exceeds hysteresis V HYS = V DR - V DF. In such cases, please ensure that R IN is less than 10 kω and that C is more than 0.1 μf. N Recommended Pull-up Resistors Value INPUT VOLTAGE RANGE 0.7V~6.0V 0.8V~6.0V 1.0V~6.0V PULL-UP RESISTANCE 220kΩ 100kΩ 33kΩ PS PRELIMINARY 5
6 TEST CIRCUITS Circuit Circuit Circuit Circuit Pull-up Resistor R PL = 100 kω is used for N version only PS PRELIMINARY 6
7 TYPICAL PERFORMANCE CHARACTERISTICS (1) Supply Current vs. Input Voltage x102xx x502xx (2) Output Voltage vs. Input Voltage C202xx Ta = 25 0 C N202xx V PULL_UP = 6.0 V, RPULL_UP = 100 kω (3) Detect Voltage, Release Voltage vs. Ambient Temperature x102xx x202xx PS PRELIMINARY 7
8 TYPICAL PERFORMANCE CHARACTERISTICS (Continued) (4) Output Current (N-channel transistor) vs Input Voltage (5) Output Current (P-channel transistor) vs. Input Voltage x502xx VOUT = 0.5 V IXD512C102xx VOUT = VIN V x502xx VOUT = 0.3 V IXD512C102xx VOUT = VIN V x502xx VOUT = 0.1 V IXD512C102xx VOUT = VIN V PS PRELIMINARY 8
9 ORDERING INFORMATION - DESIGNATOR DESCRIPTION SYMBOL DESCRIPTION NOTE: C CMOS output Output Configuration N N-channel open drain output Detect Voltage (V DF) Detect Voltage Range: 1.0 V~5.0 V, e.g. 1.2 V - = 1, = 2 Detect Threshold Accuracy 2 ±2% - (*) Packages (Order Unit) HR HR-G NR NR-G USP-3 (3000/Reel) USP-3 (1000/Reel) SSOT-24 (3000/Reel) SSOT-24 (3000/Reel) The -G suffix denotes Halogen and Antimony free as well as being fully RoHS compliant. PS PRELIMINARY 9
10 PACKAGE DRAWING AND DIMENSIONS USP-3, Units: mm SSOT-24, Units: mm USP-3 Reference Pattern Layout, Units: mm USP-3 Reference Metal Mask Design PS PRELIMINARY 10
11 MARKING SSOT-24 Represents output configuration and detect voltage range MARK OUTPUT CONFIGURATION OUTPUT VOLTAGE PRODUCT SERIES K 1.0V~2.9V C CMOS L 3.0V~5.0V M 1.0V~2.9V N N-channel open drain N 3.0V~5.0V Represents detect voltage SSOT-24 (Top View) MARK DETECT VOLTAGE (V) MARK DETECT VOLTAGE (V) F H K L M N P R S T A U B V C X D Y E Z Represents production lot number 01 to 09, 10, 11,, 99, 0A,, 0Z, 1A, repeated.(g, I, J, O, Q, W excluded) USP-3 Represents product series MARK PRODUCT SERIES 0 xxxxxx Represents output configuration and integer number of the detect voltage MARK DETECT VOLTAGE (V) OUTPUT CONFIGURATION MARK DETECT VOLTAGE (V) OUTPUT CONFIGURATION A 1.x F 1.x B 2.x H 2.x C 3.x CMOS Output K 3.x D 4.4 L 4.4 E 5.x M 5.x Represents decimal point of the detect voltage MARK DETECT VOLTAGE (V) PRODUCT SERIES 3 x.3 xx3xxx 0 x.0 xx0xxx Represents production lot number USP-3 (Top View) 01 to 09, 10, 11,, 99, 0A,, 0Z, 1A, repeated.(g, I, J, O, Q, W excluded) N-channel open drain PS PRELIMINARY 11
12 Customer Support To share comments, get your technical questions answered, or report issues you may be experiencing with our products, please visit Zilog s Technical Support page at To learn more about this product, find additional documentation, or to discover other fac-ets about Zilog product offerings, please visit the Zilog Knowledge Base at zilog.com/kb or consider participating in the Zilog Forum at This publication is subject to replacement by a later edition. To determine whether a later edition exists, please visit the Zilog website at Warning: DO NOT USE THIS PRODUCT IN LIFE SUPPORT SYSTEMS. LIFE SUPPORT POLICY ZILOG S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF ZILOG CORPORATION. As used herein Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness. Document Disclaimer 2015 Zilog, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZILOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZILOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. The information contained within this document has been verified according to the general principles of electrical and mechanical engineering. PS PRELIMINARY 12
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