Dual, 16 MHz, Rail-to-Rail FET Input Amplifier AD823

Transcription

1 FEATURES Single-supply operation Output swings rail-to-rail Input voltage range extends below ground Single-supply capability from 3 V to 36 V High load drive Capacitive load drive of 5 pf, G = + Output current of 5 ma,.5 V from supplies Excellent ac performance on.6 ma/amplifier 3 db bandwidth of 6 MHz, G = + 35 ns settling time to.% ( V step) Slew rate of V/µs Good dc performance 8 µv maximum input offset voltage µv/ C offset voltage drift 5 pa maximum input bias current Low distortion: 8 dbc worst khz Low noise: 6 nv/ khz No phase inversion with inputs to the supply rails APPLICATIONS Battery-powered precision instrumentation Photodiode preamps Active filters -bit to 6-bit data acquisition systems Medical instrumentation GENERAL DESCRIPTION The is a dual precision, 6 MHz, JFET input op amp that can operate from a single supply of 3. V to 36 V or from dual supplies of ±.5 V to ±8 V. It has true single-supply capability with an input voltage range extending below ground in single-supply mode. Output voltage swing extends to within 5 mv of each rail for IOUT µa, providing outstanding output dynamic range. An offset voltage of 8 µv maximum, an offset voltage drift of µv/ C, input bias currents below 5 pa, and low input voltage noise provide dc precision with source impedances up to a Gigaohm. It provides 6 MHz, 3 db bandwidth, 8 db khz, and a V/µs slew rate with a low supply current of.6 ma per amplifier. The drives up to 5 pf of direct capacitive load as a follower and provides an output current of 5 ma,.5 V from the supply rails. This allows the amplifier to handle a wide range of load conditions. 3V GND OUTPUT (db) Dual, 6 MHz, Rail-to-Rail FET Input Amplifier k CONNECTION DIAGRAM OUT 8 +V S IN +IN V S OUT IN +IN Figure. 8-Lead PDIP and SOIC 5mV µs Figure. Output Swing, +VS = +3 V, G = + G = + k k M FREQUENCY (Hz) Figure 3. Small Signal Bandwidth, G = + 9- R L = kω C L = 5pF +V S = +3V G = + This combination of ac and dc performance, plus the outstanding load drive capability, results in an exceptionally versatile amplifier for applications such as A/D drivers, high speed active filters, and other low voltage, high dynamic range systems. The is available over the industrial temperature range of 4 C to +85 C and is offered in both 8-lead PDIP and 8-lead SOIC packages. M Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 96, Norwood, MA 6-96, U.S.A. Tel: Fax: Analog Devices, Inc. All rights reserved.

2 * PRODUCT PAGE QUICK LINKS Last Content Update: /8/7 COMPARABLE PARTS View a parametric search of comparable parts. EVALUATION KITS Universal Evaluation Board for Dual High Speed Operational Amplifiers DOCUMENTATION Application Notes AN-8: JFET-Input Amps are Unrivaled for Speed and Accuracy AN-53: Find Op Amp Noise with Spreadsheet AN-57: Careful Design Tames High Speed Op Amps AN-4: Replacing Output Clamping Op Amps with Input Clamping Amps AN-47: Fast Rail-to-Rail Operational Amplifiers Ease Design Constraints in Low Voltage High Speed Systems AN-58: Biasing and Decoupling Op Amps in Single Supply Applications AN-649: Using the Analog Devices Active Filter Design Tool : Dual, 6 MHz, Rail-to-Rail FET Input Amplifier Data Sheet User Guides UG-8: Universal Evaluation Board for Dual High Speed Op Amps in SOIC Packages TOOLS AND SIMULATIONS Analog Filter Wizard Analog Photodiode Wizard Power Dissipation vs Die Temp VRMS/dBm/dBu/dBV calculators SPICE Macro Model A SPICE Macro Model REFERENCE MATERIALS Product Selection Guide High Speed Amplifiers Selection Table Tutorials MT-3: Ideal Voltage Feedback (VFB) Op Amp MT-33: Voltage Feedback Op Amp Gain and Bandwidth MT-47: Op Amp Noise MT-48: Op Amp Noise Relationships: /f Noise, RMS Noise, and Equivalent Noise Bandwidth MT-49: Op Amp Total Output Noise Calculations for Single-Pole System MT-5: Op Amp Total Output Noise Calculations for Second-Order System MT-5: Op Amp Noise Figure: Don't Be Misled MT-53: Op Amp Distortion: HD, THD, THD + N, IMD, SFDR, MTPR MT-56: High Speed Voltage Feedback Op Amps MT-58: Effects of Feedback Capacitance on VFB and CFB Op Amps MT-6: Choosing Between Voltage Feedback and Current Feedback Op Amps DESIGN RESOURCES Material Declaration PCN-PDN Information Quality And Reliability Symbols and Footprints DISCUSSIONS View all EngineerZone Discussions. SAMPLE AND BUY Visit the product page to see pricing options. TECHNICAL SUPPORT Submit a technical question or find your regional support number. DOCUMENT FEEDBACK Submit feedback for this data sheet. This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified.

3 TABLE OF CONTENTS Features... Applications... General Description... Connection Diagram... Revision History... Specifications... 3 Absolute Maximum Ratings... 6 Thermal Resistance... 6 ESD Caution... 6 Typical Performance Characteristics...7 Theory of Operation... 3 Output Impedance... 4 Application Notes... 5 Input Characteristics... 5 Output Characteristics... 5 Outline Dimensions... 8 Ordering Guide... 9 REVISION HISTORY / Rev. D to Rev. E Changes to Theory of Operation Section... 3 Changes to Ordering Guide / Rev. C to Rev. D Changes to Figure Changes to Figure / Rev. B to Rev. C Changes to Table /7 Rev. A to Rev. B Updated Format... Universal Changes to DC Performance... 5 Updated Outline Dimensions... 8 Changes to Ordering Guide /4 Rev. to Rev. A Changes to Specifications... Changes to Ordering Guide... 7 Updated Outline Dimensions /95 Revision : Initial Version Rev. E Page of

4 SPECIFICATIONS At TA = 5 C, +VS = +5 V, R L = kω to.5 V, unless otherwise noted. Table. Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE 3 db Bandwidth, VO. V p-p G = + 6 MHz Full Power Response VO = V p-p 3.5 MHz Slew Rate G =, VO = 4 V Step 4 V/µs Settling Time to.% G =, VO = V Step 3 ns to.% G =, VO = V Step 35 ns NOISE/DISTORTION PERFORMANCE Input Voltage Noise f = khz 6 nv/ Hz Input Current Noise f = khz fa/ Hz Harmonic Distortion RL = 6 Ω to.5 V, VO = V p-p, f = khz 8 dbc Crosstalk f = khz RL = 5 kω 5 db f = MHz RL = 5 kω 63 db DC PERFORMANCE Initial Offset..8 mv Maximum Offset Over temperature.3. mv Offset Drift µv/ C Input Bias Current VCM = V to 4 V 3 5 pa at TMAX VCM = V to 4 V.5 5 na Input Offset Current pa at TMAX.5 na Open-Loop Gain VO =. V to 4 V, RL = kω 45 V/mV TMIN to TMAX V/mV INPUT CHARACTERISTICS Input Common-Mode Voltage Range. to +3. to +3.8 V Input Resistance 3 Ω Input Capacitance.8 pf Common-Mode Rejection Ratio VCM = V to 3 V 6 76 db OUTPUT CHARACTERISTICS Output Voltage Swing IL = ± µa.5 to V IL = ± ma.8 to 4.9 V IL = ± ma.5 to 4.75 V Output Current VOUT =.5 V to 4.5 V 6 ma Short-Circuit Current Sourcing to.5 V 4 ma Sinking to.5 V 3 ma Capacitive Load Drive G = + 5 pf POWER SUPPLY Operating Range 3 36 V Quiescent Current TMIN to TMAX, total ma Power Supply Rejection Ratio VS = 5 V to 5 V, TMIN to TMAX 7 8 db Rev. E Page 3 of

5 At TA = 5 C, +VS = +3.3 V, RL = kω to.65 V, unless otherwise noted. Table. Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE 3 db Bandwidth, VO. V p-p G = + 5 MHz Full Power Response VO = V p-p 3. MHz Slew Rate G =, VO = V Step 3 V/µs Settling Time to.% G =, VO = V Step 5 ns to.% G =, VO = V Step 3 ns NOISE/DISTORTION PERFORMANCE Input Voltage Noise f = khz 6 nv/ Hz Input Current Noise f = khz fa/ Hz Harmonic Distortion RL = Ω, VO = V p-p, f = khz 93 dbc Crosstalk f = khz RL = 5 kω 5 db f = MHz RL = 5 kω 63 db DC PERFORMANCE Initial Offset..5 mv Maximum Offset Over temperature.5.5 mv Offset Drift µv/ C Input Bias Current VCM = V to V 3 5 pa at TMAX VCM = V to V.5 5 na Input Offset Current pa at TMAX.5 na Open-Loop Gain VO =. V to V, RL = kω 5 3 V/mV TMIN to TMAX V/mV INPUT CHARACTERISTICS Input Common-Mode Voltage Range. to +. to +.8 V Input Resistance 3 Ω Input Capacitance.8 pf Common-Mode Rejection Ratio VCM = V to V 54 7 db OUTPUT CHARACTERISTICS Output Voltage Swing IL = ± µa.5 to 3.75 V IL = ± ma.8 to 3. V IL = ± ma.5 to 3.5 V Output Current VOUT =.5 V to.5 V 5 ma Short-Circuit Current Sourcing to.5 V 4 ma Sinking to.5 V 3 ma Capacitive Load Drive G = + 5 pf POWER SUPPLY Operating Range 3 36 V Quiescent Current TMIN to TMAX, total ma Power Supply Rejection Ratio VS = 3.3 V to 5 V, TMIN to TMAX 7 8 db Rev. E Page 4 of

6 At TA = 5 C, VS = ±5 V, RL = kω to V, unless otherwise noted. Table 3. Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE 3 db Bandwidth, VO. V p-p G = + 6 MHz Full Power Response VO = V p-p 4 MHz Slew Rate G =, VO = V Step 7 5 V/µs Settling Time to.% G =, VO = V Step 55 ns to.% G =, VO = V Step 65 ns NOISE/DISTORTION PERFORMANCE Input Voltage Noise f = khz 6 nv/ Hz Input Current Noise f = khz fa/ Hz Harmonic Distortion RL = 6 Ω, VO = V p-p, f = khz 9 dbc Crosstalk f = khz RL= 5 kω 5 db f = MHz RL= 5 kω 63 db DC PERFORMANCE Initial Offset mv Maximum Offset Over temperature. 7 mv Offset Drift µv/ C Input Bias Current VCM = V 5 3 pa VCM = V 6 pa at TMAX VCM = V.5 5 na Input Offset Current pa at TMAX.5 na Open-Loop Gain VO = + V to V, RL = kω 3 6 V/mV TMIN to TMAX 3 V/mV INPUT CHARACTERISTICS Input Common-Mode Voltage Range 5. to to +3.8 V Input Resistance 3 Ω Input Capacitance.8 pf Common-Mode Rejection Ratio VCM = 5 V to +3 V 66 8 db OUTPUT CHARACTERISTICS Output Voltage Swing IL = ± µa 4.95 to V IL = ± ma 4.9 to +4.9 V IL = ± ma 4.75 to V Output Current VOUT = 4.5 V to +4.5 V 7 ma Short-Circuit Current Sourcing to V 8 ma Sinking to V 6 ma Capacitive Load Drive G = + 5 pf POWER SUPPLY Operating Range 3 36 V Quiescent Current TMIN to TMAX, total ma Power Supply Rejection Ratio VS = 5 V to 5 V, TMIN to TMAX 7 8 db Rev. E Page 5 of

7 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter Rating Supply Voltage 36 V Internal Power Dissipation PDIP (N).3 W SOIC (R).9 W Input Voltage (Common Mode) ±VS Differential Input Voltage ±VS Output Short-Circuit Duration See Figure 4 Storage Temperature Range N, R 65 C to +5 C Operating Temperature Range 4 C to +85 C Lead Temperature Range 3 C (Soldering, sec) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE θja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Specification is for device in free air. Table 5. Thermal Resistance Package Type θja Unit 8-Lead PDIP 9 C/W 8-Lead SOIC 6 C/W MAXIMUM POWER DISSIPATION (W) LEAD PDIP 8-LEAD SOIC T J = 5 C AMBIENT TEMPERATURE ( C) Figure 4. Maximum Power Dissipation vs. Temperature 9-4 ESD CAUTION Rev. E Page 6 of

8 TYPICAL PERFORMANCE CHARACTERISTICS UNITS σ = 4µV UNITS σ =.4pA UNITS 4 3 UNITS INPUT OFFSET VOLTAGE (µv) Figure 5. Typical Distribution of Input Offset Voltage INPUT BIAS CURRENT (pa) Figure 8. Typical Distribution of Input Bias Current 9-8 UNITS C TO +5 C 3 UNITS INPUT BIAS CURRENT (pa) V CM = V INPUT OFFSET VOLTAGE DRIFT (µv/ C) Figure 6. Typical Distribution of Input Offset Voltage Drift TEMPERATURE ( C) Figure 9. Input Bias Current vs. Temperature VS = +5V V S = ±5V INPUT BIAS CURRENT (pa) 3 INPUT BIAS CURRENT (pa) COMMON-MODE VOLTAGE (V) Figure 7. Input Bias Current vs. Common-Mode Voltage COMMON-MODE VOLTAGE (V) Figure. Input Bias Current vs. Common-Mode Voltage 9- Rev. E Page 7 of

9 V S = ±.5V R L = kω 93 OPEN-LOOP GAIN (db) OPEN-LOOP GAIN (db) k k k 5k LOAD RESISTANCE (Ω) Figure. Open-Loop Gain vs. Load Resistance TEMPERATURE ( C) Figure 4. Open-Loop Gain vs. Temperature 9-4 OPEN-LOOP GAIN (k V ) V R L = kω R L = kω R L = Ω OPEN-LOOP GAIN (db) GAIN R L = kω C L = pf PHASE PHASE MARGIN (Degrees) OUTPUT VOLTAGE (V) Figure. Open-Loop Gain vs. Output Voltage, VS = ±.5 V 9- k k k M M M FREQUENCY (Hz) Figure 5. Open-Loop Gain and Phase Margin vs. Frequency THD (db) V S = +3V V OUT = V p-p R L = Ω V S = ±5V V OUT = V p-p R L = 6Ω V S = ±.5V V OUT = V p-p R L = kω V OUT = V p-p R L = 5kΩ k k k FREQUENCY (Hz) ALL OTHERS +V S = +3V V OUT = V p-p R L = 5kΩ Figure 3. Total Harmonic Distortion vs. Frequency M 9-3 INPUT VOLTAGE NOISE (nv/ Hz) 3 3 k k k M FREQUENCY (Hz) Figure 6. Input Voltage Noise vs. Frequency 9-6 Rev. E Page 8 of

10 CLOSED-LOOP GAIN (db) C +7 C 55 C C L = pf R L = kω G = + CMRR (db) V S = ±5V FREQUENCY (MHz) 9-7 k k k M M FREQUENCY (Hz) 9- Figure 7. Closed-Loop Gain vs. Frequency Figure. Common-Mode Rejection Ratio vs. Frequency GAIN = + OUTPUT RESISTANCE (Ω). OUTPUT SATURATION VOLTAGE (V). V OL 5 C V S V OH 5 C. k k k M M FREQUENCY (Hz) Figure 8. Output Resistance vs. Frequency, +VS = +5 V, Gain = LOAD CURRENT (ma) Figure. Output Saturation Voltage vs. Load Current 9- OUTPUT STEP SIZE FROM V TO V SHOWN (V) V S = ±5V C L = pf %.%.% %.%.% SETTLING TIME (ns) 9-9 QUIESCENT CURRENT (ma) C +5 C 55 C 5 5 SUPPLY VOLTAGE (±V) 9- Figure 9. Output Step Size vs. Settling Time (Inverter) Figure. Quiescent Current vs. Supply Voltage Rev. E Page 9 of

11 POWER SUPPLY REJECTION (db) PSRR +PSRR SERIES RESISTANCE (Ω) Ф M = V IN Ф M = 45 R S C L k k k M M FREQUENCY (Hz) Figure 3. Power Supply Rejection vs. Frequency CAPACITOR (pf ) Figure 6. Series Resistance vs. Capacitive Load R L = kω G = OUTPUT VOLTAGE (V p-p) V S = ±5V CROSSTALK (db) k +V S = +3V k M M FREQUENCY (Hz) k k k M FREQUENCY (Hz) M 9-7 Figure 4. Large Signal Frequency Response Figure 7. Crosstalk vs. Frequency V IN =.9V p-p +V S = +3V G = V IN = V p-p V S = ±5V G = + 5mV µs 5V µs kω +5V V IN =.9V p-p kω 5Ω 3V kω V OUT 5pF 9-5 khz, V p-p 5V 64Ω 5pF 9-8 Figure 5. Output Swing, +VS = +3 V, G = Figure 8. Output Swing, VS = ±5 V, G = + Rev. E Page of

12 5V R L = 3Ω C L = 5pF R F = R G = kω G = 3V R L = kω C L = 5pF +V S = +3V G = + GND GND 5mV µs 9-9 5mV µs 9-3 Figure 9. Output Swing, +VS = +5 V, G = Figure 3. Output Swing, +VS = +3 V, G = + V IN = mv STEP +V S = +3V G = + 5V R L = kω C L = 5pF G = +.55V.45V 5mV 5ns Figure 3. Pulse Response, +VS = +3 V, G = GND 5mV ns Figure 33. Pulse Response, +VS = +5 V, G = V R L = kω C L = 5pF G = + R L = kω C L = 47pF G = + GND 5mV ns Figure 3. Pulse Response, +VS = +5 V, G = mV ns Figure 34. Pulse Response, +VS = +5 V, G = +, CL = 47 pf 9-34 Rev. E Page of

13 R L = kω C L = 5pF V S = ±5V G = + +V V 5V 5ns Figure 35. Pulse Response, VS = ±5 V, G = Rev. E Page of

14 THEORY OF OPERATION The is fabricated on the Analog Devices, Inc. proprietary complementary bipolar (CB) process that enables the construction of PNP and NPN transistors with similar ft s in the 6 MHz to 8 MHz region. In addition, the process also features N-Channel JFETs that are used in the input stage of the. These process features allow the construction of high frequency, low distortion op amps with picoamp input currents. This design uses a differential output input stage to maximize bandwidth and headroom (see Figure 36). The smaller signal swings required on the SP/SN outputs reduce the effect of the nonlinear currents due to junction capacitances and improve the distortion performance. With this design, harmonic distortion of better than 9 khz into 6 Ω with VOUT = 4 V p-p on a single 5 V supply is achieved. The complementary common emitter design of the output stage provides excellent load drive without the need for emitter followers, thereby improving the output range of the device considerably with respect to conventional op amps. The can drive ma with the outputs within.6 V of the supply rails. The also offers outstanding precision for a high speed op amp. Input offset voltages of mv maximum and offset drift of µv/ C are achieved through the use of the Analog Devices advanced thin film trimming techniques. A nested integrator topology is used in the (see Figure 37). The output stage can be modeled as an ideal op amp with a single-pole response and a unity-gain frequency set by transconductance gm and Capacitor C. R is the output impedance of the input stage; gm is the input transconductance. C and C5 provide Miller compensation for the overall op amp. The unity-gain frequency occurs at gm/c5. Solving the node equations for this circuit yields V OUT Vi = A ( sr[ C( A + ) ] + ) s + g m C where: A = gmgm RR (open-loop gain of op amp). A = gm R (open-loop gain of output stage). The first pole in the denominator is the dominant pole of the amplifier and occurs at ~8 Hz. This equals the input stage output impedance R multiplied by the Miller-multiplied value of C. The second pole occurs at the unity-gain bandwidth of the output stage, which is 3 MHz. This type of architecture allows more open-loop gain and output drive to be obtained than a standard -stage architecture would allow. V CC R4 R37 V BE +.3V V I5 Q43 Q55 I6 Q44 A = Q57 A = 9 V INP J J6 Q7 Q6 Q46 Q58 R44 Q49 R8 Q8 C Q Q54 V OUT V INN SP SN Q6 Q6 V CC C Q48 V B Q53 Q35 V EE I C6 R33 I R43 I3 Q56 Q5 I4 Q59 A = Q7 A = Figure 36. Simplified Schematic Rev. E Page 3 of

15 OUTPUT IMPEDANCE The low frequency open-loop output impedance of the commonemitter output stage used in this design is approximately 3 kω. Although this is significantly higher than a typical emitter follower output stage, when it is connected with feedback, the output impedance is reduced by the open-loop gain of the op amp. With 9 db of open-loop gain, the output impedance is reduced to <. Ω. At higher frequencies, the output impedance rises as the open-loop gain of the op amp drops; however, the output also becomes capacitive due to the integrator capacitors C and C. This prevents the output impedance from ever becoming excessively high (see Figure 8), which can cause stability problems when driving capacitive loads. In fact, the has excellent cap-load drive capability for a high frequency op amp. Figure 34 shows the connected as a follower while driving 47 pf direct capacitive load. Under these conditions, the phase margin is approximately. If greater phase margin is desired, a small resistor can be used in series with the output to decouple the effect of the load capacitance from the op amp (see Figure 6). In addition, running the part at higher gains also improves the capacitive load drive capability of the op amp. g m VI g m VI C SN R V OUT SP C R C5 R g m Figure 37. Small Signal Schematic 9-37 Rev. E Page 4 of

16 APPLICATION NOTES INPUT CHARACTERISTICS In the, N-Channel JFETs are used to provide a low offset, low noise, high impedance input stage. Minimum input commonmode voltage extends from. V below VS to V < +VS. Driving the input voltage closer to the positive rail causes a loss of amplifier bandwidth and increased common-mode voltage error. The does not exhibit phase reversal for input voltages up to and including +VS. Figure 38 shows the response of an voltage follower to a V to 5 V (+VS) square wave input. The input and output are superimposed. The output polarity tracks the input polarity up to +VS, with no phase reversal. The reduced bandwidth above a 4 V input causes the rounding of the output wave form. For input voltages greater than +VS, a resistor in series with the s noninverting input prevents phase reversal, at the expense of greater input voltage noise. This is illustrated in Figure GND % +V S GND V µs V Figure 38. Input Response: RP =, VIN = to +VS 9 % V IN V V R P 5V µs Figure 39. Input Response: VIN = to +VS + mv, VOUT = to +VS, RP = 49.9 kω V OUT Because the input stage uses N-Channel JFETs, input current during normal operation is negative; the current flows out from the input terminals. If the input voltage is driven more positive than +VS.4 V, the input current reverses direction as internal device junctions become forward biased. This is illustrated in Figure 7. A current limiting resistor should be used in series with the input of the if there is a possibility of the input voltage exceeding the positive supply by more than 3 mv, or if an input voltage is applied to the when ±VS =. The amplifier becomes damaged if left in that condition for more than seconds. A kω resistor allows the amplifier to withstand up to V of continuous overvoltage and increases the input voltage noise by a negligible amount. Input voltages less than VS are a completely different story. The amplifier can safely withstand input voltages V below VS as long as the total voltage from the positive supply to the input terminal is less than 36 V. In addition, the input stage typically maintains picoamp level input currents across that input voltage range. The is designed for 6 nv/ Hz wideband input voltage noise and maintains low noise performance to low frequencies (see Figure 6). This noise performance, along with the s low input current and current noise, means that the contributes negligible noise for applications with source resistances greater than kω and signal bandwidths greater than khz. OUTPUT CHARACTERISTICS The s unique bipolar rail-to-rail output stage swings within 5 mv of the supplies with no external resistive load. The s approximate output saturation resistance is 5 Ω sourcing and sinking. This can be used to estimate the output saturation voltage when driving heavier current loads. For instance, when driving 5 ma, the saturation voltage to the rails is approximately 5 mv. If the s output is driven hard against the output saturation voltage, it recovers within 5 ns of the input returning to the amplifier s linear operating region. A/D Driver The rail-to-rail output of the makes it useful as an A/D driver in a single-supply system. Because it is a dual op amp, it can be used to drive both the analog input of the A/D as well as its reference input. The high impedance FET input of the is well suited for minimal loading of high output impedance devices. Rev. E Page 5 of

17 Figure 4 shows a schematic of an being used to drive both the input and reference input of an AD67, a -bit, 3-MSPS, single-supply ADC. One amplifier is configured as a unity-gain follower to drive the analog input of the AD67, which is configured to accept an input voltage that ranges from V to.5 V. The other amplifier is configured as a gain of to drive the reference input from a.5 V reference. Although the AD67 has its own internal reference, there are systems that require greater accuracy than the internal reference provides. On the other hand, if the AD67 internal reference is used, the second amplifier can be used to buffer the reference voltage for driving other circuitry while minimally loading the reference source. +5VA +5VD The distortion analysis is important for systems requiring good frequency domain performance. Other systems may require good time domain performance. The noise and settling time performance of the provides the necessary information for its applicability for these systems. 5dB/DIV V IN =.5V p-p G = + FI = 49kHz V IN V REF (.5V) kω VA 8 4.µF 7 kω µf.µf.µf µf CLOCK 49.9Ω µf V CC REFOUT AIN AIN REFIN REFCOM NCOMP NCOMP ACOM 6 REF 8 9 COM 9 8 +V DD AD67 DCOM µF OTR BIT (MSB) BIT BIT3 BIT4 BIT5 BIT6 Figure 4. Driving Input and Reference of the AD67, a -Bit, 3-MSPS ADC +5VD BIT7 BIT8 BIT9 BIT BIT BIT (LSB) The circuit was tested with a 5 khz sine wave input that was heavily low-pass filtered (6 db) to minimize the harmonic content at the input to the. The digital output of the AD67 was analyzed by performing a fast Fourier transform (FFT). During the testing, it was observed that at 5 khz, the output of the cannot go below ~35 mv (operating with negative supply at ground) without seriously degrading the second harmonic distortion. Another test was performed with a Ω pull-down resistor to ground that allowed the output to go as low as mv without seriously affecting the second harmonic distortion. There was, however, a slight increase in the third harmonic term with the resistor added, but it was still less than the second harmonic. Figure 4 is an FFT plot of the results of driving the AD67 with the with no pull-down resistor. The input amplitude was.5 V p-p and the lower voltage excursion was 35 mv. The input frequency was 49 khz, which was chosen to spread the location of the harmonics. 9-4 Figure 4. FFT of AD67 Output Driven by 3 V, Single-Supply Stereo Headphone Driver The exhibits good current drive and total harmonic distortion plus noise (THD+N) performance, even at 3 V single supplies. At khz, THD+N equals 6 db (.79%) for a 3 mv p-p output signal. This is comparable to other singlesupply op amps that consume more power and cannot run on 3 V power supplies. In Figure 4, each channel s input signal is coupled via a μf Mylar capacitor. Resistor dividers set the dc voltage at the noninverting inputs so that the output voltage is midway between the power supplies (+.5 V). The gain is.5. Each half of the can then be used to drive a headphone channel. A 5 Hz high-pass filter is realized by the 5 μf capacitors and the headphones that can be modeled as 3 Ω load resistors to ground. This ensures that all signals in the audio frequency range ( Hz to khz) are delivered to the headphones. CHANNEL CHANNEL 95.3kΩ µf MYLAR 95.3kΩ µf MYLAR 3V 95.3kΩ 3 8 / 47.5kΩ kω kω 4.99kΩ 4.99kΩ.µF 5µF HEADPHONES 3Ω IMPEDANCE 6 / 5µF 47.5kΩ µf Figure 4. 3 V Single-Supply Stereo Headphone Driver L R Rev. E Page 6 of

18 Second-Order Low-Pass Filter Figure 43 depicts the configured as a second-order Butterworth low-pass filter. With the values as shown, the corner frequency equals khz. Component selection is shown in the following equations: R = R = User Selected (Typical Values: kω to kω). 44 C farads π f R. 77 C π f R V IN R kω cutoff C 8pF cutoff C 56pF R kω +5V C3.µF / C4.µF 5V Figure 43. Second-Order Low-Pass Filter 5pF V OUT A plot of the filter is shown in Figure 44; better than 5 db of high frequency rejection is provided. HIGH FREQUENCY REJECTION (db) k V DB V OUT k k M M M FREQUENCY (Hz) Figure 44. Frequency Response of Filter Single-Supply Half-Wave and Full-Wave Rectifiers An configured as a unity-gain follower and operated with a single supply can be used as a simple half-wave rectifier. The inputs maintain picoamp level input currents even when driven well below the minus supply. The rectifier puts that behavior to good use, maintaining an input impedance of over Ω for input voltages from within V of the positive supply to V below the negative supply. The full-wave and half-wave rectifier shown in Figure 45 operates as follows: when VIN is above ground, R is bootstrapped through the unity-gain follower A and the loop of Amplifier A. This forces the inputs of A to be equal, thus no current flows through R or R, and the circuit output tracks the input. When VIN is below ground, the output of A is forced to ground. The noninverting input of Amplifier A sees the ground level output of A; therefore, A operates as a unitygain inverter. The output at Node C is then a full-wave rectified version of the input. Node B is a buffered half-wave rectified version of the input. Input voltage supply to ±8 V can be rectified, depending on the voltage supply used. A V IN A 9 B 3 +V S 8 R kω.µf A / R kω 7 A / Figure 45. Full-Wave and Half-Wave Rectifier V µs C FULL-WAVE RECTIFIED OUTPUT B HALF-WAVE RECTIFIED OUTPUT 9-44 C % V Figure 46. Single-Supply Half-Wave and Full-Wave Rectifier 9-46 Rev. E Page 7 of

19 OUTLINE DIMENSIONS.4 (.6).365 (9.7).355 (9.). (5.33) MAX.5 (3.8).3 (3.3).5 (.9). (.56).8 (.46).4 (.36) 8. (.54) BSC 5.8 (7.).5 (6.35) 4.4 (6.).5 (.38) MIN SEATING PLANE.5 (.3) MIN.6 (.5) MAX.5 (.38) GAUGE PLANE.35 (8.6).3 (7.87).3 (7.6).43 (.9) MAX.95 (4.95).3 (3.3).5 (.9).4 (.36). (.5).8 (.).7 (.78).6 (.5).45 (.4) COMPLIANT TO JEDEC STANDARDS MS- CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. Figure Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N-8) Dimensions shown in inches and (millimeters) 766-A 5. (.968) 4.8 (.89) 4. (.574) 3.8 (.497) (.44) 5.8 (.84).5 (.98). (.4) COPLANARITY. SEATING PLANE.7 (.5) BSC.75 (.688).35 (.53).5 (.).3 (.) 8.5 (.98).7 (.67).5 (.96).5 (.99).7 (.5).4 (.57) 45 COMPLIANT TO JEDEC STANDARDS MS--AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 47-A Rev. E Page 8 of

20 ORDERING GUIDE Model Temperature Range Package Description Package Option ANZ 4 C to +85 C 8-Lead PDIP N-8 AR 4 C to +85 C 8-Lead SOIC_N R-8 AR-REEL 4 C to +85 C 8-Lead SOIC_N, 3 Tape and Reel R-8 AR-REEL7 4 C to +85 C 8-Lead SOIC_N, 7 Tape and Reel R-8 ARZ 4 C to +85 C 8-Lead SOIC_N R-8 ARZ-RL 4 C to +85 C 8-Lead SOIC_N, 3 Tape and Reel R-8 ARZ-R7 4 C to +85 C 8-Lead SOIC_N, 7 Tape and Reel R-8 AR-EBZ Evaluation Board Z = RoHS Compliant Part. Rev. E Page 9 of

21 NOTES 995 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D9--/(E) Rev. E Page of