1 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: FUNDAMENTAL THEORY AND APPLICATIONS, VOL. 45, NO. 1, JANUARY input signal is v(t) =1+0:5sin(!t)  J. Valsa and J. Vlach, SWANN A program for analysis of switched analog nonliner networks, Int. J. Circuit Theory and Applications, vol. 23, no. 4, pp , July Aug with f =101=[100 p 2] Hz, the switching frequency is f s = 100 Hz. The choice of values is such that the network will need a long time for the transients to die out. Fig. 3 shows the transient response of v(t) during the first 20 periods of the input signal, starting from zero initial condition. If we apply the steady-state algorithm, only six iterations are needed to get the error below : Fig. 4 shows the dc and the harmonic content of the output. Example 3 is the input circuit of a self-biasing amplitude modulator. It has two input signals e 1(t) = 5 sin(! 1t) e 2(t) = 5 sin(! 2t) with f 1 = p 24 Hz and f 2 = 500 Hz. The original circuit is in Fig. 5(a), its equivalent in Fig. 5(b). The input port of the transistor is modeled as an internally controlled switch (ideal diode), in series with an internal dc voltage source E =0:7V. The nonlinear admittance g represents the diode conductance. For v = v(t) it is defined by g(v) =0:005(v +0:1v 2 ): Computation of the steady-state response via transient analysis is very expensive, because the capacitor is large and makes the time constant of the circuit much larger than the period of the lowest input frequency. Fig. 6 shows the transient of the voltage v(t): When we apply the steady-state algorithm, the convergence, shown in Fig. 7, is fast and the steady state is reached within six iterations. Fig. 8 shows the response of the network in steady state and Fig. 9 is the dc and the harmonic content of the output in steady state. VII. CONCLUSION The paper presented a simple algorithm to calculate the quasiperiodic steady state of switched networks. Conditions for its convergence were derived. Acceleration to the steady state is based on extrapolation and thus avoids the need to calculate derivatives and Jacobians. Illustrative examples show application of the algorithm. REFERENCES  K. S. Kundert, J. K. White, and A. Sangiovanni-Vincentelli, Steady State Methods for Simulating Analog and Microwave Circuits. Norwell, MA: Kluwer Academic,  L. Zhu and J. Vlach, Analysis and steady state of nonlinear networks with ideal switches, IEEE Trans. Circuits Syst. I, vol. 42, pp , Apr  L. O. Chua and A. Ushida, Algorithms for computing almost periodic steady state response of nonlinear systems to multiple input frequencies, IEEE Trans. Circuits Syst., vol. CAS-28, pp , Oct  K. S. Kundert, J. White, and A. Sangiovanni-Vincentelli, A mixed frequency-time approach for distortion analysis of switching filter circuits, IEEE J. Solid-State Circuits, vol. 24, pp , Apr  K. S. Kundert, G. B. Sorkin, and A. Sangiovanni-Vincentelli, Applying harmonic balance to almost-periodic circuits, IEEE Trans. Circuits Syst., vol. CAS-36, no. 2, pp , Feb  S. Skelboe, Computation of the periodic steady-state response of nonlinear networks by extrapolation methods, IEEE Trans. Circuits Syst., vol. CAS-27, pp , Mar , Conditions for quadratic convergence of quick periodic steadystate methods, IEEE Trans. Circuits Syst., vol. CAS-29, pp , Apr An Offset Compensated and High-Gain CMOS Current-Feedback Op-Amp Ali Assi, Mohamad Sawan, and Jieyan Zhu Abstract This brief describes a new CMOS current-feedback operational amplifier (CFOA) with an on-chip continuous-time current-mode input offset voltage compensation circuit. The proposed compensation method is based on a combination of two techniques: the error integration and the current feedback. In addition, this method is irrespective of process and temperature parameters because of its fully symmetrical architecture. HSPICE simulations of the designed CMOS CFOA layout show that the input offset voltage could be reduced to less than 1 mv, and a gain of around 112 db and a power consumption of less than 3 mw are achievable. Index Terms CMOS analog design, current-feedback op-amp, current-mode technique, offset compensation. I. INTRODUCTION The current-feedback operational amplifier (CFOA), also called the transimpedance amplifier, has been described in , , , and . The most important features of CFOA s are wide-band and high slew-rate. CFOA s use a single-stage amplifier architecture; therefore, no compensation capacitance is needed. This type of operational amplifier has found wide use in high-frequency applications since the end of the 1980 s . CFOA s rely on the availability of complementary transistors , i.e., very similar NPN transistor and PNP transistor in bipolar or metal oxide semiconductor field effect transistor (Channel N MOSFET) and metal oxide semiconductor field effect transistor Channel P MOSFET in CMOS technology. The offset voltage of CFOA depends heavily upon the difference of V BE s or V T s. This ranges from a few millivolts to as high as 40 mv in most bipolar junction transistor (BJT) CFOA s, as reported in  and . To date, most of the research on CFOA s are focusing on bipolar technology. In addition to the consideration of high frequency, another important reason is that the 1V T between Channel N MOSFET and Channel P MOSFET is much bigger than that of V BE s of BJT s. The 1V T could be more than 100 mv even in a modern silicon fabrication process. To overcome input offset voltage in CFOA s, two architectures have been investigated. The most popular one is to insert a diodeconnected transistor in series with each emitter follower in  and . This technique does degrade the CFOA s bandwidth because of an increase of the impedance at its negative input (V n ). The other technique is to scale I PNP and I NPN  with a proper choice of Manuscript received May 9, 1995; revised November 15, This work was supported by the Canadian Microelectronics Corporation (CMC) and the Natural Sciences and Engineering Research Council of Canada. This paper was recommended by Associate Editor A. Rodriquez-Vazquez. The authors are with the Department of Electrical and Computer Engineering, École Polytechnique de Montréal, Montréal, PQ, Canada H3C 3A7 ( Publisher Item Identifier S (98)01616-X /98$ IEEE
2 86 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: FUNDAMENTAL THEORY AND APPLICATIONS, VOL. 45, NO. 1, JANUARY 1998 (a) (b) Fig. 1. (c) CFOA. (a) Typical architecture. (b) Closed-loop macromodel. (c) CMOS implementation. the emitter areas. This last method is not suitable in CMOS CFOA design because of much more dispersion of parameters in the CMOS process than that in bipolar. In this brief, a new CMOS CFOA with an on-chip current-mode input offset voltage compensation circuit is proposed. The proposed compensation method is based on a combination of two techniques frequently exploited by analog designers in different applications. These techniques are the error integration and the current feedback. However, the compensation method described in this brief is also suitable for BJT CFOA s. In Section II, CFOA s are briefly reviewed. Section III describes the proposed offset compensation method operating on continuoustime current mode. In Section IV, simulation results of the offset compensated CMOS CFOA are presented and discussed. Finally, Section V presents a conclusion. Fig. 2. Block diagram of the CFOA with the compensation circuitry. II. PRINCIPLE OF CFOA S The detailed analysis of CFOA s dc and ac performance has been described in  and . However, a brief description of a CFOA will be given in this section. In Fig. 1(a), V p and V n are noninverting inputs of CFOA, respectively. The input stage B1 is a unity-gain buffer forcing V n to follow V p. Under an ideal condition, i.e., a fully symmetrical input buffer, one can have V n = V p. An imbalance at the inputs will cause an imbalance current I n at V n. The current I n is then reflected at the common node Vo, 0 designated In, 0 by current mirror (CM). The output voltage signal, V O, is obtained by a second unity-gain buffer B2. Amplification is produced by a transimpedance stage. Generally, the transimpedance gain Z is very high, therefore, a tiny current I n is needed to obtain a large output voltage magnitude. The C p at node V 0 o is a layout parasitic equivalent capacitance. A simplified macromodel of the CFOA architecture configured in closed-loop op-amp is shown in Fig. 1(b). The output resistance of the input stage buffer R inv is included since it has a significant effect on the bandwidth of the CFOA. The current that flows out from the inverting terminal i n is transferred to the gain node, which is represented by R z and C z, via CM that has a current gain K. The
3 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: FUNDAMENTAL THEORY AND APPLICATIONS, VOL. 45, NO. 1, JANUARY (a) (b) Fig. 3. (c) Compensation circuit. (a) Block diagram of the VC VIC. (b) Schematic of half VC VIC. (c) Schematic of the CIM. voltage at the gain node is transferred to the output in the usual way by a voltage buffer with voltage gain A. The transfer function is given by v o v p = 1+ R 2 R 1 1+j!C z R inv 1+ and the pole frequency is also given by f03db = AK R 2 R 1 +R 2 AK 2C z R inv 1+ R2 R 1 +R 2 A full derivation of this transfer function is given in . (1) : (2) From the technology point of view, it is simple to manufacture a CFOA design in CMOS because of the availability of Channel N MOSFET and Channel P MOSFET transistors in most popular CMOS technologies. A CMOS implementation of a CFOA could be easily derived from an existing bipolar implementation , where the PNP and NPN transistors are replaced by Channel P MOSFET and Channel N MOSFET transistors, respectively. This translation yields a CMOS implementation of a CFOA, as shown in Fig. 1(c). In this case, the input offset voltage would be V n 0 V p = jv gsp j0v gsn (3) where V gsp = V Tp + 2I pl p C ox W
4 88 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: FUNDAMENTAL THEORY AND APPLICATIONS, VOL. 45, NO. 1, JANUARY 1998 Fig. 4. DC performance of the VC VIC and the CIM. and the following conditions should be satisfied: V gsn = V Tn + 2I nl n C ox W : (4) V gsp3 = V gsn1 and V gsn4 = V gsp2 (5) All V Tn, V Tp, n, p, and C ox are process- and temperaturedependent parameters. They could cause a significant input offset voltage as high as a few hundreds of a millivolt. Thus to date, it is hard to see a CFOA design in CMOS technology. To overcome the input offset voltage in CFOA s generally and in CMOS CFOA s specifically, we propose in the following section a current-mode offset compensation circuit based on error integration and current feedback. where V gsn1 = V Tn + V gsp2 = V Tp + 2I 1L 1 nc oxw 1 2I 2L 2 pc oxw 2 (6) III. OFFSET COMPENSATION METHOD The bloc diagram of the proposed CMOS CFOA with its currentmode offset voltage compensation circuitry is shown in Fig. 2. The compensation circuit consists of a voltage-comparator and voltage-tocurrent converter (VC VIC) and a current integrator/memory (CIM), are all connected in a closed loop. Any offset between V p and V n of the CFOA will generate a compensation current I cp or I cn. This current, applied in a negative feedback, conversely forces V n to become close to V p. Thus, any offset caused by process or by temperature parameters would be automatically compensated. In Fig. 1(c), the addition of one column (pseudo-negative input) V nr is necessary for offset compensation circuit and does not make any effect on the CFOA s performance, as will be seen later. The V nr voltage, which is generated by M 19 M 22, is almost equal to that of V n under the dc operating condition when a design match is taken between M 19 M 22 and M 1, M 2, M 9, and M 13. The addition of M 17 and M 18 as well as their bias current I bp and I bn, respectively, makes it possible to reduce the supply voltage of the CFOA to 4V T, instead of 6V T without them . The input offset voltage is essentially the offset of the input buffer (M 1 M 4 ) . From Fig. 1(c), it is clear that to let V n = V p, both of V gsp3 = V Tp + V gsn4 = V Tn + 2I cpl 3 pc oxw 3 2I cn L 4 n C ox W 4 : (7) In the balance case, I 1 is equal to I 2 (I n = I 2 0 I 1 = 0). The values of I 1 or I 2 depend upon the difference between the voltages V 1 and V 2 because V gsn1 + jv gsp2 j = V 1 0 V 2 : (8) Thus, V 1 V 2 is considered as a floating biasing voltage. According to (7), the best way to satisfy conditions (5) is by adjusting I cp and/or I cn, respectively, to force V gsp3 = V gsn1 and V gsn4 = V gsp2, and consequently V n = V p. For this purpose, a compensation circuit with accurate differential VC VIC and CIM are required. The block diagram of VC VIC is shown in Fig. 3(a) . Two fully symmetrical source followers BUF 1 and BUF2 are used to detect the difference between V p and V n of the CFOA when this diagram is
5 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: FUNDAMENTAL THEORY AND APPLICATIONS, VOL. 45, NO. 1, JANUARY (a) (b) (c) Fig. 5. Simulation results of the CFOA. (a) Input offset voltage with and without compensation. (b) Open-loop gain and gain bandwidth (GBW) of the CFOA. (c) Closed-loop gain and 03-dB frequency of the CFOA. integrated, as shown in Fig. 2. An imbalance current I imb would be generated if any imbalance caused by an existing offset on those two inputs. I imb is then reflected by two CM s to the output forming I o1 and I o2. The current outputs I o1 and I o2 have identical magnitudes, but opposite directions. Io1 and Io2 are then used to drive the CIM block. The exploitation of symmetrical architecture in this part makes the intrinsic error minimal. The detailed schematic of half VC VIC is shown in Fig. 3(b). The detailed schematic of the CIM is shown in Fig. 3(c) . This circuit is used to supply an additional biasing current (I cp or I cn )to the CFOA s input buffer [Fig. 1(c)] which compensate the CFOA s input offset voltage. In Fig. 3(c), Iin is the integration input current, and I feed is the feedback current. Both of them are summed into the node A. The integrated output current I cp (t) [or I cn (t)] is I cp (t)= g m C 1 0 t I in dt (9) where I in is the output current of the VC VIC, i.e., I o1 (or I o2 ), gm is the transconductance of transistors M 5 or M 6, and C is the equivalent MOS gate capacitances. From (9), we can see that the output currents of the CIM depend upon the magnitude and the direction of Iin as well as the time t. C (C 1 or C 2 ) is used to memorize a stable current in the case of I in =0, therefore, its value is not critical to the output current.
6 90 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: FUNDAMENTAL THEORY AND APPLICATIONS, VOL. 45, NO. 1, JANUARY 1998 Fig. 6. Layout of the CFOA. The previously discussed CFOA, VC VIC, and CIM were combined in one circuit. Using this circuit, any small imbalance between V p and V n would be compensated, consequently reducing the input offset voltage of the CFOA. The addition of V nr in Fig. 1(c) makes it possible to detect an input offset voltage between V p and V nr other than V p and V n. In practical applications, V n is served as a node of feedback connection and any ac variation of V p V n should not be reflected to the offset compensation circuit. Therefore, the quantity of compensation is entirely dependent upon the dispersion of process parameters, and independent of CFOA s operating condition. Once the compensation is completed, a stable output currents I cp and I cn are maintained on the CIM output. The accuracy of the compensation technique is only dependent on the error of the part of voltage comparison, not on the absolute value of currents, because the compensation procedure is executed continuously. Thus, a high accuracy compensation can be achieved by using a fully symmetrical architecture in the VC VIC s input. IV. IMPLEMENTATION AND RESULTS The proposed CMOS CFOA has been simulated with HSPICE using the 0.8-m BiCMOS technology provided by NORTEL. The simulation results of the VC VIC and the CIM are shown in Fig. 4. Even an imbalance of 1 mv at the inputs of VC VIC (V i1 Vi2) would cause a tiny output current I o1 or I o2, which drive the CIM to increase one compensation current, supposing I cp, and to simultaneously decrease the other one, here called I cn. When both the inputs of the CFOA are in balance, the output current of the CIM, I cp and I cn would keep constant, as shown in Fig. 4. The input offset voltage of less than 1 mv with compensation and more than 100 mv without compensation are shown in Fig. 5(a). A few microseconds is needed to stabilize the compensation circuit at the beginning of turn-on CFOA s power supply. In Fig. 5(b), an open-loop frequency response is shown with load capacitance C L =1pF. A maximum gain of around 112 db was obtained without special optimization of the CFOA ac performance design. The power consumption of the compensated CFOA was less than 3 mw. Fig. 5(c) shows the closed-loop gain and the 03-dB frequency of the CFOA. The layout of the CFOA is shown in Fig. 6. The complete design (with pads) occupies m 2. The CFOA occupy only m 2 and the compensation circuit occupy m 2. The layout is now in fabrication process using the 0.8-m BiCMOS technology. consumption of less than 3 mw. The presented continuous-time current mode offset compensation method is independent based upon fabrication process and temperature parameters. ACKNOWLEDGMENT The authors would like to thank the Canadian Microelectronics Corporation (CMC) and the Natural Sciences and Engineering Research Council of Canada (NSERC) for their technical support. REFERENCES  J. Zhu, M. Sawan, and K. Arabi, An offset compensated CMOS current feedback operational-amplifier, in Proc. IEEE ISCAS, Seattle, WA, April 30, 1995 May , pp  S. Franco, Analytical foundations of current-feedback amplifiers, in Proc. IEEE ISCAS, vol. 2, Chicago, IL May 3 6, 1993, pp  B. Harvey, Current-feedback OPAMP limitations: A state-of-the-art review, in Proc. IEEE ISCAS, vol. 2, Chicago, IL, May 3 6, 1993, pp  I. A. Koullias, A wide-band low-offset current-feedback OP AMP design, in Proc. IEEE Bipolar Circuits Technol. Meeting, Minnesota, Sept , 1989, pp  D. F. Browers, The so-called current-feedback operational amplifiertechnological breakthrough or engineering curiosity, in Proc. IEEE ISCAS, vol. 2, Chicago, IL, May 3 6, 1993, pp  C. Toumazou, F. J. Lidgey, and D. G. Haigh, Analogue IC Design, The Current-Mode Approach. Stevenage, U.K.: Peregrinus, 1990, pp , ,  W.-K. Chen, The Circuits and Filters Handbook, a CRC handbook published in cooperation with IEEE Press, 1995, pp V. CONCLUSION A compensated offset high-gain CMOS CFOA has been proposed. The offset is reduced to less than 1 mv with gain bandwidth (GBW) = 20 MHz, power supply voltage (VDD) = 5 V, and a power