High-Bandwidth, High-Efficiency Envelope Tracking Power Supply for 40W RF Power Amplifier Using Paralleled Bandpass Current Sources

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1 Downloaded from orbi.du.dk on: Dec 11, 2017 HighBandwidh, HighEfficiency Envelope Tracking Power Supply for 40W RF Power Amplifier Using Paralleled Bandpass Curren Sources Høyerby, Mikkel Chrisian Kofod; Andersen, Michael A. E. Published in: EEE 36h Conference on Power Elecronics Specialiss, 2005 Link o aricle, DO: /PESC Publicaion dae: 2005 Documen Version Publisher's PDF, also known as Version of record Link back o DTU Orbi Ciaion (APA): Høyerby, M. C. W., & Andersen, M. A. E. (2005). HighBandwidh, HighEfficiency Envelope Tracking Power Supply for 40W RF Power Amplifier Using Paralleled Bandpass Curren Sources. n EEE 36h Conference on Power Elecronics Specialiss, 2005 (pp ). EEE. DO: /PESC eneral righs Copyrigh and moral righs for he publicaions made accessible in he public poral are reained by he auhors and/or oher copyrigh owners and i is a condiion of accessing publicaions ha users recognise and abide by he legal requiremens associaed wih hese righs. Users may download and prin one copy of any publicaion from he public poral for he purpose of privae sudy or research. You may no furher disribue he maerial or use i for any profimaking aciviy or commercial gain You may freely disribue he URL idenifying he publicaion in he public poral f you believe ha his documen breaches copyrigh please conac us providing deails, and we will remove access o he work immediaely and invesigae your claim.

2 HighBandwidh, HighEfficiency Envelope Tracking Power Supply for 40W RF Power Amplifier Using Paralleled Bandpass Curren Sources Mikkel C. W. Høyerby Technical Universiy of Denmark Building 325 Dk2800 Lyngby Denmark Absrac This paper presens a highperformance power conversion scheme for power supply applicaions ha require very high pu volage slew raes (dv/d). The concep is o parallel 2 swiching bandpass curren sources, each opimized for is passband frequency space and he expeced load curren. The principle is demonsraed wih a power supply, designed for supplying a 40W linear RF power amplifier for efficien amplificaion of a 16QAM modulaed daa sream.. NTRODUCTON Power conversion hrough paralleled converers is useful when an applicaion calls for higher performance han can be achieved wih a single converer. Examples are he combinaion of a buck converer and a linear power sage where improved load sep performance is required in a DCDC converer [1] and he combinaion of a classd and a linear power sage for audio amplificaion wih boh high efficiency and low disorion [2]. n boh hese applicaions, he linear power sage supplies very lile average power. The combinaion of 2 or more idenical swiching converers is frequenly seen in form of he muliphase buck converers used for microprocessor power supplies. n applicaions where boh significan DC and highfrequency AC currens mus be supplied, exchanging he fas, linear converer used in [1] wih a highbandwidh swiching converer offers an opporuniy for increasing efficiency, since a swiching converer is subsanially more efficien han a linear converer a high load currens. An emerging applicaion for DCAC supplies is envelope racking power supplies for RFPAs (Radio Frequency Power Amplifiers), where QAM (Quadraure Ampliude Modulaion) is used. Michael A. E. Andersen Technical Universiy of Denmark Building 325 Dk2800 Lyngby Denmark ma@oersed.du.dk The concep of using an envelope racking power supply for an RFPA has been well known for a number of decades [3]. The basic idea is o maximize he efficiency of a linear RFPA by supplying only he minimum necessary supply volage an any given ime, as illusraed in Figure 1. Recenly, he use of swichmode echniques [4], [5] has resuled in small and efficien envelope racking power supplies for lowpower QPSK (Quadraure Phase Shif Keying) cellular mobile elephony applicaions. The increasing use of QAM over QPSK, o increase bandwidh efficiency poenially imposes higher demands on power supply pu volage slewrae (dv/d) due o fundamenal differences beween hese modulaion schemes. The UMTS (Universal Mobile Telecommunicaions Sysem) sandard for nexgeneraion mobile elephony sysems incorporaes QAM in some of is higherspeed daa ransmission modes. This paper examines a possible soluion o designing highefficiency envelope racking power supplies, based on using paralleled swiching power converers. The 3 main issues discussed in his paper are: Comparison beween a single converer and he parallel configuraion. Derivaion of a suiable conrol mehod. Experimenal verificaion.. DESN SPECFCATONS The pracical design problem considered concerns he design of an envelope racking power supply for an Xband 40W RFPA for a saellie elephony sysem. The RFPA amplifies a 16QAM modulaed daa sream wih 150kHz symbol rae, hus requiring he power supply o effecively rack a 75kHz square envelope. The following design parameers are obained: Table 1 Considered design specificaions. npu volage (V in ) 30V Oupu volage (V ) Beween 1/3 V in and 2/3 V in Oupu curren Up o 2A Equivalen load resisance 10Ω Oupu ransiion ime Less han 2µs Oupu ripple volage As low as possible Figure 1 dealized example of envelope racking supply volage for an RFPA for 16QAM signal amplificaion. Where he requiremen for a 2µs ransiion ime is se as a compromise beween maximizing RFPA efficiency and minimizing he required power supply bandwidh /05/$ EEE. 2804

3 . PROPOSED POWER CONVERSON SCHEME n high dv/d applicaions, high conrol bandwidh is required. n he considered example, around 300kHz of closedloop bandwidh is required, leading o a minimal swiching frequency of around 1.5MHz if a single buck converer is used. n he volage range considered, swiching losses will be he dominan source of power loss, so by minimizing he curren delivered by he fas swiching buck converer, is efficiency can be maximized. This can be accomplished by divering he DC load curren o a slower, more efficien buck converer (see Figure 4). However, he slow converer mus have a nonzero bandwidh, since he average (pas o fuure) pu curren, logically enough, is unknown. mus herefore adap o he curren load curren, which i should do as quickly as possible o minimize loading of he fas converer. n a proper design, he slow converer pu volage largesignal conrol bandwidh will be limied by inducor curren slew rae, which hus provides a suiable adapaion ime consan. The impac of having nonzero conrol bandwidh, limied by slewrae is shown in Figure 4. Noe ha he inducor currens shown are averaged over one swich cycle (no ripple) and ha pu capacior charging/discharging currens are disregarded. squaresignal frequency. The worscase L 2 RMS curren is a facor of 2( 3) imes higher han in he concepual case, so he error made canno seriously affec he come of he comparison. The following expressions apply for he RMS values of he shown (averaged) concepual inducor currens: V1 V2 L1, RMS = 2 2 2Rload V1 V 2 V1 V2, V1 V2 2 2 RMS = L2, RMS = Rload Rload 2R load f V 1 =20V and V 2 =10V (worscase condiion in he considered applicaion), L 1 carries 3 imes he RMS curren of L 2, and he RMS curren in L 2 is hus reduced by a facor of 10, when comparing o a single buck converer. This reducion in RMS curren is refleced direcly o he MOSFETs, allowing he R ds(on) of Q 3, Q 4 o be 10 imes higher for a fixed conducion loss. This leads o approximaely 10 imes lower gae charge, and hus, swiching losses. The decrease in swiching losses in he fas converer should hen be able o accommodae he exra losses associaed wih adding he slow buck converer. Reducing he RMS swich curren in he fas converer also causes reduced swiching (peak) currens, direcly conribuing o furher reducion of swiching losses. Oupu waveforms Oupu inducor curren waveforms n a comparable 2phase inerleaved buck soluion, each converer will deliver half he pu curren. This enables he use of MOSFETs wih 2 imes higher R ds(on) and hus 2 imes lower Q g for fixed conducion losses, compared o a single buck soluion. The FETs in he 2phase buck will hus swich wice as fas and a half he curren, reducing swiching losses by a facor of 4. So, provided ha efficiency of he slow converer in he proposed scheme is high enough, efficiency will be superior o ha of a 2phase inerleaved buck soluion. V V 1 V 2,avg Concepual case: Slow converer has almos zero bandwidh Realisic case: AC response of slow converer is primarily slewrae limied Realisic case: AC response of slow converer is less severely slewrae limied V. PROPOSED CONTROL SCHEME The iniial idea for conrolling he paralleled converers is o operae he 2 pu inducors as curren sources, since curren sources can be paralleled wih problems. This requires each inducor curren o be conrolled individually. The Laplacedomain block diagram model of he paralleled, currenconrolled buck converers is shown in Figure 3. This model is an exension of he single buck converer model uilized in [6]. ref1 cff1 (s) 1 K c1 K mod1 V PWM1 sl 1 Worscase: RMS value of L 2 curren is maximal Figure 2 Principal illusraion of he proposed power conversion scheme. Comparison beween a singleconverer and a dualconverer soluion is made based on he concepual funcion of he paralleled converers, since RMS inducor currens are oherwise dependen on boh inducor values (slewrae) and cfb1 (s) (s) ref R load sr load C V cfb1 (s) cff2 (s) ref2 V PWM2 1 K c2 K mod2 sl 2 Figure 3 Block diagram of paralleled, curren conrolled buck converers. 2805

4 The following ransfer funcion expressions are found: V ( ) 1( s) s cff c 1 = = K mod1 1 ( K c2 V = ref 1 ref 2 = K mod 2 cff 1 1 cff 2 ( K mod1 cff 2 mod 2 cfb1 cfb2 ) ) V c = = K c1c1 K c2c2 ref c (s) can be compued numerically using hese expressions. n order o minimize measuremen problems, curren esimaion via inducor volage inegraion is uilized. As discussed in [6], his mehod causes he curren loop o ransi o volage mode when he ineviable esimaor lowfrequency cuoff is reached. The ransiion ino volage mode has he benefi of lowering pu impedance [7], and is he logical reason behind calling he closed curren loop around L 1 a bandpass curren source. is obvious ha a leas one of he inducor curren loops has o operae down o DC, since paralleling volage sources would be disasrous. Therefore, curren esimaion is only used on L 1, which carries he highes RMS curren. n order o ensure ha he DC curren in L 2 is exacly 0, proporionalinegral (P) feedback is used in he curren loop around L 2. Thus he closed curren loop around L 2 is also a bandpass curren source, wih zero DC gain. The derived curren conrol scheme shown in Figure 4. The ransfer funcion from curren reference o pu volage, c (s) is ploed for various values of R load in Figure 5, using he parameers shown in Table 2. Figure 5 Combined closedloop curren conroller ransfer funcions ( c(s)) wih differen loads. Using he seleced parameers, he curren conroller ransfer funcion is well behaved, and all ransfer funcion complex pole/zero pairs have a damping facor > 1 for loads above 1Ω. Volage conrol loop design is hus relaively sraighforward. n order o increase midband loop gain (which is low a 1Ω), lag compensaion is used, alhough his has he effec of decreasing phase margin a higher load resisances. No accepable design is found suiable for he enire load range above 1Ω bu forunaely, he converer aims for applicaions wih load resisances above he 48Ω range. The problem observed is general for curren conrolled designs. Figure 4 Principal illusraion of he proposed curren conrol scheme. Table 2 Parameers used in curren conrol loop design. Oupu filer capacior C 200nF Slow buck inducor L 1 50µH Fas buck inducor L 2 2.2µH Curren esimaor ime consan τ es 300µs Curren esimaor gain K cfb1 1 nducor sense winding raio n L 1:1 P curren compensaor ime consan τ icfb 300µs Slow PWM modulaor gain K mod1 100 Fas PWM modulaor gain K mod2 100 Slow curren loop gain K c1 1 Fas curren loop gain K c Figure 6 Openloop volage conrol loop ransfer funcions wih differen loads, demonsraing worscase phase margin. Table 3 Parameers used in volage conrol loop design Lag compensaor pole ime consan τ p 10µs Lag compensaor zero ime consan τ z 0.82µs Conroller proporional gain K P 5

5 Using he volage loop compensaor parameers given in Table 3 resuls in he open and closedloop Bode plos shown in Figure 6 and Figure 7. The corresponding closedloop sep response is shown in Figure 8. Figure 7 Closedloop Bode plos of volage conrol loop. Adequae phase margin is obained a all loads, while he pu volage seles a he correc value wihin 2µs for load resisances above 4Ω. as a compromise beween minimizing ripple curren and minimizing inducor size. MOSFETs for he fas converer are chosen wih emphasis on low Q g and C DS o minimize he penaly for operaing a high swiching frequency, leading o use of he Fairchild FDD5612. This device has he lowes Q g among considered 60V DPAK MOSFETs (7.5nC), bu sill leads o swiching losses being dominan. The slow converer swiching frequency is chosen for maximal efficiency. The L 1 filer inducor is finally chosen so ha he slow converer conribues wih accepable pu ripple volage. Closedloop conrol bandwidh B 3dB 300kHz Fas converer swiching frequency f sw2 1.5MHz Fas converer pu filer cuoff 1 240kHz frequency 2π L 2 C Fas buck inducor L 2 2.2µH Oupu filer capacior C 200nF Slow converer swiching frequency f sw1 250kHz Slow buck inducor L 1 50µH V. SMULATED RESULTS A PSpice simulaion model is used o verify he power supply design. As shown in Figure 9 and Figure 10, he designed conrol sysem leads o absence of DC curren in L 2 while mainaining sabiliy and fas response ime ( 1.5µs) over he inended load range. Figure 8 Sep responses of closed volage conrol loop showing ha fas and well damped responses are achievable using he proposed conrol scheme. The resuls obained wih he linear model are mainly useful for confirming ha he paralleled converers can be conrolled in a sable and fas manner. n he acual sysem, inducor curren slew raes will limi he response speed of he power supply, regardless of he volage loop gain provided. As will be shown, however, he calculaed response imes are well wihin range provided ha pu filer componens are seleced correcly. V. PROTOTYPE DESN Hyseresis conrol is used in boh converers o maximize he conrol bandwidh per swiching frequency raio [6], [8]. The swiching frequency of he fas converer is se o 1.5MHz, reflecing he conrol bandwidh requiremen. The fas converer pu filer cuoff frequency is chosen o allow sufficien pu volage slew rae. The L 2 filer inducor value is chosen Figure 9 Simulaed pu (red) and reference volages (magena), L 2 (blue) and L 1 (green) buck inducor curren. Converer driving 100kHz 10Vpp15VDC square wave response ino 8Ω. Figure 10 Simulaed pu (red) and reference volages (magena), L 2 (blue) and L 1 (green) buck inducor curren. Converer driving 100kHz 10Vpp15VDC square wave response ino open load. 2807

6 V. ACHEVED PRACTCAL RESULTS A prooype power supply has been implemened, as shown in Figure 11, using a simple 2layer PCB and lowcos componens. Some precauions are necessary o preven he 2 hyseresis conrollers from synchronizing wih each oher hrough coupled swiching noise. The problem is defeaed hrough filering a all hyseresis comparaor inpu pins. Figure 13 Oupu and reference volages (op), HF (middle) and LF (boom) buck inducor curren, condiions as in Figure 12. The unloaded sep response is shown in Figure 14. A small overshoo occurs as prediced by simulaion. Figure 11 The consruced prooype power supply. The 100kHz sep response ino 8Ω is shown along wih PWM signal waveforms and inducor currens in Figure 13 and Figure 12. The responseseling ime is 2µs, in accordance wih specificaions. The pu volage response is very similar o he simulaed resul (in Figure 9) apar from a small overshoo. This is probably due o unmodeled implemenaion dynamics in he simulaion. The curren responses are in good agreemen, boh regarding peak ransien currens and ripple currens. is especially eviden ha he fas converer supplies only he AC pu curren, while he slow converer handles he DC curren, and as much AC curren as allowed by L 1 curren slew rae. The laer leads o he slow converer locking ono he reference signal frequency, which is a feaure of he hyseresis conroller. Figure 14 Oupu and reference volages (op), HF (middle) and LF (boom) buck PWM pu volages. Converer driving 20kHz 12Vpp15VDC square ino open load. The longerm response of he inducor currens o an pu volage sep is shown in Figure 15. This measuremen clearly illusraes ha he slow converer operaes o is maximum capabiliy during ransiens, and hus ha he fas converer delivers an absolue minimum fracion of he load curren. The absence of DC curren in L 2 is also apparen. Figure 12 Oupu and reference volages (op), HF (middle) and LF (boom) buck PWM pu volages. Converer driving 100kHz 12Vpp15VDC square ino 8Ω. Figure 15 Oupu and reference volages (op), HF (middle) and LF (boom) buck inducor curren. Converer driving 20kHz 12Vpp15VDC square ino 8Ω. 2808

7 A power loss esimaion model for he paralleled buck converers has been implemened in MATLAB. Figure 16 shows a comparison beween esimaed and measured efficiency for a consan pu volage. A highspeed oscilloscope wih curren probes is used for inpu/pu power measuremen since here is significan ripple, especially on pu volage. Oscilloscope measuremen errors (measuremen resoluion is 8 bis) should accoun for some of he deviaion beween calculaed and measured efficiency. Figure 16 Calculaed and measured efficiency figures for saionary 15VDC pu volage. V. CONCLUSON A power conversion and conrol scheme for power supplies requiring high slewrae and high efficiency has been presened. The power conversion scheme has been compared o a simpler soluion, hereby jusifying he proposed, more complex, soluion. Comparison wih a 2phase buck soluion has proven a complicaed ask, a leas requiring complee loss calculaion models for boh opologies. However, simple iniial consideraions show ha he proposed opology probably can perform a leas as well as he more common 2phase buck opology. A fully operaional prooype has demonsraed high efficiency, considering he bandwidh and slewrae provided. The high efficiency naurally resuls from he use of a highly efficien lowbandwidh converer unloading he highbandwidh converer in parallel, allowing reduced swiching losses in he highbandwidh converer. For he conrol par, operaion has been explained by linear modeling, and verified boh hrough simulaion and experimenal work. The resuls presened in his paper are currenly saeofhear wihin he field of highbandwidh power supplies wih paralleled swiching power conversion. REFERENCES [1] Andrés Barrado, Ramon Vasques, Emilio Olías, Theoreical Sudy and mplemenaion of a Fas Response Hybrid Power Supply, EEE ransacions on power elecronics, vol. 19, No. 4, July 2004 [2] R. A. R. van der Zee, E. van Tujil, A powerefficien audio amplifier combining swiching and linear echniques, EEE J. SolidSae Circ. Vol. 34, July 1999 [3] L. Kahn, Singlesided Transmission by Envelope Eliminaion and Resoraion, Proc. RE, pp , July 1952 [4]. Hanningon, P.F. Chin, P.M. Asbeck, L.E. Larson, HighEfficiency Power Amplifier Using Dynamic Power Supply for CDMA Applicaions, EEE ransacions on microwave heory and echniques, vol. 47, Augus 1999 [5] B. Sahu,. A. RincónMora, A HighEfficiency Linear RF Power Amplifier Wih a PowerTracking Dynamically Adapive BuckBoos Supply, EEE ransacions on microwave heory and echniques, vol. 52, January 2004 [6] Mikkel C. W. Høyerby, Dennis R. Andersen, Lars Peersen, Michael A. E. Andersen, High Bandwidh Auomoive Power Supply for Lowcos PWM Audio Amplifiers, proc. of NORPE 2004, June 2004, Trondheim, Norway [7] Allen F. Rozman, Jeffrey J. Boylan, Band Pass Curren Conrol, proc. of APEC 1994, February 1994, Orlando, USA, pp [8] Rais Mifakhudinov, An Analyical Comparison of Alernaive Conrol Techniques for Powering Nex eneraion Microprocessors, Texas nsrumens Power Supply Design Seminar 2001 Series, slup133.pdf 2809

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