A new method of waveform digitization based on time-interleaved A/D conversion *

Transcription

1 Subitted to Chinese Physics C A new ethod of wavefor digitization based on tie-interleaved A/D conversion * YE Chun-Feng ( 叶春逢 ) 1,2,3 ZHAO Lei ( 赵雷 ) 1,2;1) FENG Chang-Qing ( 封常青 ) 1,2 LIU Shu-Bin ( 刘树彬 ) 1,2 AN Qi ( 安琪 ) 1,2 1 State Key Laboratory of Particle Detection & Electronics, University of Science and technology of China, 2 Anhui Key Laboratory of Physical Electronics, Departent of Modern Physics, University of Science and technology of China, Hefei 2326, China 3 75 Research Division of Electronic Engineering Institute, Hefei 2337, China Abstract: Tie interleaved analog-to-digital conversion (TIADC) based on parallelis is an effective way to eet the requireent of the ultra-fast wavefor digitizer beyond Gsps. Different ethods to correct the isatch errors aong different analog-to-digital conversion channels have been developed previously. To overcoe the speed liitation in hardware design and to ipleent the isatch correction algorith in real tie, this paper proposes a fully parallel correction algorith. A 12-bit 1-Gsps wavefor digitizer with ENOB around 1.5 bit fro 5 MHz to 2 MHz is ipleented based on the real-tie correction algorith. Key words: wavefor digitizer, tie-interleaved analog-to-digital conversion, tie-skew error, digital correction algoriths PACS: 7.5.Hd 1 Introduction Copared with the traditional ethod based on charging integration, shaping, and low speed data acquisition, odern wavefor digitizers (WFDs) can be utilized to obtain the ost coprehensive physics inforation in nuclear and particle physics experients [1-9]. A nuber of wavefor digitizing systes have been developed based on fast analog-to-digital converters (ADCs) or switched capacitor arrays (SCAs) [1, 11]. An ultra high sapling speed up to ultiple Gsps can be achieved in SCAs; however, they have the disadvantage of a liited continuous recording length (e.g. DRS4, 124-bin window) and a lower resolution (with an ENOB usually less than 8 bits). Therefore, great efforts have been devoted to the research of wavefor digitization based on fast ADCs, which has been applied in physics experients. In the data acquisition syste of the MAGIC telescope [7], for instance, relative slow flash ADCs (3-Msps 8-bit) are used as WFDs. Due to the liitation of the sapling rate, pulse stretching circuits are used to expand the input pulse to a FWHM of about 6.5 ns. Wavefor digitization is also included in the readout electronics for LHAASO (the Large High Altitude Air Shower Observatory) KM2A [8], which is based on 12-bit ADCs with a sapling rate of 5 Msps. Considering that the rising tie of photoultiplier tubes (PMTs) is about 3 ~ 4 ns,the sapling rate is not adequate to record the original wavefor directly; thus a pulse stretching circuit is also needed. If a higher sapling speed is achieved, ore detailed inforation of the original wavefor can be obtained directly. To eet the requireent of the ultra-fast WFDs beyond Gsps, the tie interleaved analog-to-digital conversion (TIADC) ethod is eployed in this paper. TIADC is an effective way to achieve a high sapling rate with relatively slower, cheaper and lower power consuption ADC chips, which is based on parallelis. In a TIADC syste with M A/D conversion channels, the total sapling rate can be enhanced to M ties higher by adjusting the sapling phases of the ADCs [12, 13]. However, due to the isatches aong different channels, additional errors are introduced. There * Supported by Knowledge Innovation Progra of The Chinese Acadey of Sciences (KJCX2-YW-N27) and National Natural Science Foundation of China ( , ) 1) Eail: zlei@ustc.edu.cn

2 exist three ain isatch errors, including the gain isatch error, the offset isatch error and the tie-skew error between the clock signals distributed to the. These errors will ultiately liit the syste perforance, causing the so-called pattern noises and significantly degrading the signal to noise and distortion ratio (SINAD) [14-17]. Detailed discussions about the isatch errors can be found in Refs. [18-21]. Different ethods to correct these isatch errors have been proposed. Correction of gain and offset isatch errors is siple; however, correction of tie-skew error is quite difficult, especially when it is ipleented in real-tie algorith logic. There are several ethods [22-28] for the tie-skew error correction. Copared with the blind copensation [22, 23], interpolation [24] and fractional delay filters based ethod [25], the perfect reconstruction ethod [26-28] could be a favorable choice considering its sipler architecture and better feasibility in hardware ipleentation. Based on the perfection reconstruction, a ultichannel-filtering approach was recently developed to further reduce coputation coplexity and the requireent on processing speed. However, under the situation of high resolution and high speed, it is still too difficult to ipleent the correction ethod in real-tie algoriths. This paper proposes a fully parallel correction algorith that apparently has not been reported before, which overcoes the speed liitation in hardware design and can be utilized to correct the isatch errors in real tie. To further verify the efficiency of the ethod, a 12-bit 1-Gsps WFD is presented, which is coposed of four 12-bit 25-Msps A/D conversion channels. The test results indicate that this WFD achieves an effective nuber of bits (ENOB) around 1.5 bits fro 5 MHz to 2 MHz with real-tie correction algoriths applied. This syste also integrates a high perforance interface based on Peripheral Coponent Interconnect (PCI) Express v2.. The outline of this paper is as follows: Section 2 describes the syste architecture. Section 3 discusses a real-tie correction ethod, which deliberates the parallel structure of the correction ethod and its ipleentation of the algoriths within a single FPGA device. In Section 4, we show a series of test results. In the last section, we conclude this paper and suarize what has been achieved. 2 Syste architecture As shown in Fig. 1, the WFD consists of three ain parts: front end circuits, ulti-phase clock generation circuits, as well as real-tie correction algoriths and the PCI Express interface integrated within one FPGA. Fig. 1. (color online) Block diagra of the 12-bit 1-Gsps WFD. The input analog signal is split into two channels, which is fed to two A/D converters KAD5512P5 [29]. Each ADC chip consists of two 12-bit 25-Msps A/D cores, the analog bandwidth of which is up to 1.3 GHz. There actually exist four A/D conversion channels in this syste. A 5 MHz sapling clock is generated and converted to two signals with a phase shift of 18 degrees. Each of these two clock signals is inputted to one ADC chip, and further converted to a pair of 25 MHz signals with reverse phases, as the sapling clocks for two A/D cores. Thus, four interleaved sapling

3 clocks with a phase shift of 9 degrees are finally obtained. The output data streas of the four A/D cores are transferred to an FPGA device (XC6VLX13T). The data are processed with the real-tie correction algoriths, buffered and then transferred to a personal coputer (PC) through the PCI Express interface, which is also integrated in the FPGA. 2.1 Front end circuits In high-speed high-resolution A/D conversion systes, the front end coupling circuit is a crucial part, which is used to ipleent single to differential conversion and ipedance atch. Cascaded transission-line transforers (TC1-1-13M) are eployed to provide additional isolation and iprove coon-ode rejection for a good balance between the differential output signals [3], as shown in Fig. 2. Fig. 2. (color online) Block diagra of the ADC front end circuits. 2.2 Multi-phase clock generation circuits In clock generation circuits, there are two ajor issues with great concern -- the clock jitter and the tie-skew between channels [31, 32]. Clock tie-skew degrades the spurious free dynaic range (SFDR) and SINAD of an A/D conversion syste and can be corrected by algoriths; eanwhile, the clock jitter deteriorates the signal-to-noise ratio (SNR) perforance. The theoretical relationship [33] between clock jitter (t jitter ) and SNR is shown in SNR 2log(2 f t ). (1) Considering this is a 12-bit digitizer, we ai to achieve a SNR of 7 db up to 2 MHz, which requires a axiu tolerated RMS jitter better than fs. The structure of the clock generation circuits is shown in Fig. 3. in jitter Fig. 3. (color online) Block diagra of the clock generation circuits. A 1 MHz reference clock generated by a high perforance oscillator VC-82 is fed to a low-noise clock jitter cleaner (LMK431B) with cascaded phase-locked loops (PLL) inside. The reference clock is converted to a 1 MHz signal by the first PLL with an external voltage controlled crystal oscillator (VCXO) odule (CVHD-95), which is sent to the second PLL with an internal voltage controlled oscillator (VCO) to generate a 15 MHz signal. Through the divider in the distribution part in LMK431B, two 5 MHz clock signals are obtained, which are based on the low voltage positive eitter-coupled logic (LVPECL) level. Ultra low jitter is achieved by allowing the external VCXO's phase noise to doinate the final output phase noise at low offset frequencies and the internal VCO's phase noise to doinate the final output phase noise at high offset frequencies. These result in best overall phase noise and jitter

4 perforance [34]. A phase shift of 18 degrees between the two 5 MHz clock signals can be achieved by reversing the positive and negative signal lines of the second clock. The internal clock anageent block inside the ADC chip further converts the 5 MHz clock signal to a pair of 25 MHz signals in phase opposition as the sapling clocks for two A/D cores. Thus, four interleaved sapling clocks in phase quadrature are finally obtained. Siulation has been conducted to evaluate the phase noise of the clock circuits, as shown in Fig. 4. The integrated RMS jitter (1 Hz to 1 MHz) of the 5 MHz clock signal is estiated about fs, which is beyond the requireent. -7 Phase Noise (dbc/hz) Clock Frequency: 5MHz Type: LVPECL RMS Jitter: fs (1Hz - 1MHz) Offset Frequency (Hz) Fig. 4. (color online) Phase noise siulation results of the clock generation circuits. 2.3 Multiple ADC synchronization The input 5 MHz clock signal is divided by two inside the ADC chip KAD5512P5, and then two 25MHz clock signals in phase opposition are supplied to the two ADC cores respectively. Fig. 5 shows a conceptual view of the internal data clocking anageent circuitry. 3ps 5ps 7ps 9ps 11ps 13ps 15ps ADC1 5MHz º ADC2 5MHz 18º ADC1_ CLKOUTP 25MHz tdc ADC1_ D[11:] ADC1_Core1 ADC1_Core2 Data N+ Data N+2 Data N+4 Data N+6 ADC2_ D[11:] (I) ADC2_Core1 ADC2_Core2 Data N+1 Data N+3 Data N+5 Data N+7 ADC2_ CLKOUTP ( Phase I ) tdc I ADC2_ D[11:] (II) ADC2_Core2 ADC2_Core1 Data N+1 Data N+3 Data N+5 Data N+7 ADC2_ CLKOUTP ( Phase II ) A tdc II Fig. 5. (color online) Data clocking circuits inside KAD5512P5 and two possible sapling sequences aong four ADC cores. ADC internal data clocking anageent circuitry. Two saple sequences aong four ADC Cores. This WFD consists of two ADC chips, each with two cores. The clock divider norally coes out of the reset signal in a rando phase of the input clock [35]. So there exist two possible sapling sequences aong the four ADC cores, as shown in Fig. 5. The first sapling sequence is ADC1_core1, ADC2_core1, ADC1_core2, ADC2_core2, when ADC2_CLKOUT (the output clock of ADC2) is in the state of Phase I; the second sapling sequence is ADC1_core1, ADC2_core2, ADC1_core2, ADC2_core1, when ADC2_CLKOUT is in the state of Phase II. Different filters are

5 required to process the different sequences, so a predeterined sequence ust be guaranteed in the circuit design. As shown in Fig. 6, a reset circuitry is designed to generate two reset signals in our work, which are sent to the two ADC chips, respectively. These two reset signals are asserted high level in sequence in this design, and eanwhile a phase difference of 18 degrees between the is achieved (the phase difference between ADC1_CLK and ADC2 CLK is 18 degrees). Therefore, we can guarantee a 9 degrees phase difference aong the four sapling clock signals of the ADC cores. With this sequence of the two reset signals, the sapling sequence is also deterined -- the first sapling sequence in Fig. 5; therefore, the data streas of these two ADCs are well synchronized. Fig. 6. (color online) Reset circuit for the two ADCs. 2.4 Real-tie correction algoriths within the FPGA As shown in Fig. 7, the 5-Mbps digital sequences of two A/D converters are received by a single FPGA with the double data rate (DDR) technique. By using the input serial-to-parallel logic resources (ISERDES) in the FPGA, the data streas are converted to four-channel data of 12-bit, 25 Msps, which are further deserialized to 16 channels with a data rate of 62.5 Msps. In the real-tie correction block, the gain and offset errors are corrected by adders and ultipliers, and tie-skew error is corrected based on a fully parallel correction ethod, which will be presented in detail in Section 3. Fig. 7. (color online) Data processing procedure inside the FPGA. 3 Real-tie correction ethods 3.1 Algorith architecture As entioned in Section 1, the perfect reconstruction ethod is a favorable choice for tie-skew error correction. In this ethod, the filter banks are eployed, where the ADC output data streas are processed by a digital FIR filter F i (z) with the ipulse response f [n] shown as below [36]: M 1 sin(( n d d ) ) M f [ n] ( n d d ) sin(( d d j) ) j, j M, i i M ( ), M 1 w n n d d L n d d L. (2)

6 Here, d = t /T s, and t denotes the tie-skew between the other A/D channel and the first channel; d denotes the delay which is a constant integer; T s denotes the period of the syste sapling clock; f [n] can be designed if the tie skews t are acquired. w [n] corresponds to a Kaiser windowing function to sooth the tie response of the filters. Those FIR filters are of the length 2L. However, this ethod requires up-sapling the data sequence of each A/D channel to the syste sapling rate of f s ; therefore, it cannot be applied in real-tie correction in ultra high speed situation. Poly-phase realization of the reconstruction filters was proposed [37], which increased the parallelis and reduced the coputational coplexity of the digital filter systes, since up-sapling was not further required. Thus, it is a feasible ethod to enhance the processing speed of the correction algorith. The relation between the reconstruction filters F i (z) and the poly phase filters can be expressed as M 1 k M F ( z) z Fk[ z ],,1,..., M 1. (3) k Here, F k (z) are the poly-phase coponents of F (z), and the overall filter bank can be written as F,( z) F,1( z) F, M 1( z) F1, ( z) F1,1 ( z) F1, M 1( z) F( z). F M 1, ( z) FM 1,1 ( z) FM 1, M 1( z) (4) In this TIADC syste, there are four A/D conversion channels of 25-Msps. With the poly-phase filter structure, the throughout processing rate is still too high to be applied in the logic design inside the FPGA. We eployed a fully parallel filtering ethod, which reduces the requireent on the processing speed. Based on this ethod, we successfully ipleented real-tie correction algoriths in the FPGA. Considering an M-channel TIADC syste, as shown in Fig. 8, the output data strea of each ADC channel is converted to N-channel data sequences by a deserializer; therefore, a total of M N channel data sequences are processed by the following poly-phase filter bank at a uch lower speed than the original data rate. x [k] x 1[k] x M-1 [k] Deserializer 1:N 1:N 1:N x [l] x [l+1] x [l+n-1] x 1[l] x 1[l+1] x 1 [l+n-1] x M-1 [l] x M-1 [l+1] x M-1 [l+n-1] Reorder MN:MN x [l] x 1[l] x M-1 [l] x [l+1] x 1 [l+1] x M-1 [l+n-1] x [l+n-1] x 1[l+N-1] x M-1 [l+n-1] Ploy-phase filters F (z) MN MN y [l] y 1[l] y M-1 [l] y [l+1] y 1 [l+1] y M-1 [l+n-1] y [l+n-1] y 1[l+N-1] y M-1 [l+n-1] Multiplexer y[n] Fig. 8. Scheatic of the fully parallel processing algorith. The kernel part is the poly-phase filter atrix of MN MN. The tie-skew error aong the M N channel data sequences can be derived fro that aong the original M channel data streas. Based on the tie-skew error values, the filter atrix can be ipleented. As for this TIADC syste, the filter atrix is of with N set to 4, and now the final processing speed is reduced to 62.5 Msps (25 Msps/4). 3.2 Siulation of the fully parallel ethod

7 In order to confir the function of this fully parallel ethod, corresponding siulations have been conducted in a 4-channel TIADC syste. The input signal x c (t) is supposed to be the su of four sinusoid ters with a unit aplitude and frequencies of f s /15, 2f s /15, 3f s /15 and 4f s /15 respectively. And we assue that the gain, offset and tie-skew isatches are [1, 1.2,.97, 1.3], [, -2, 1, 3] LSB, and [, -.4,.2, -.1] T s. In the siulation, the continuous tie signal x c (t) is quantized by the 12-bit 4-channel TIADC odel, and the data streas of 4 channels are split into 16 channels (N=4). And now the tie-skew isatches are [, -.4,.2, -.1,, -.4,.2, -.1,, -.4,.2, -.1,, -.4,.2, -.1] T s. The reconstruction filter for each channel is designed to be of 8 taps, which is equivalent to 16 5-tap filter cells in one row of the atrix in Eq. (4). Fig. 9 shows the frequency spectru of x c (t) before correction, in which the distortions caused by the three types of isatches can be observed. By applying the correction algoriths entioned above, the isatch errors can be effectively eliinated, as shown in Fig Aplitude(dB) Aplitude(dB) Noralized frequency (fs) Noralized frequency (fs) Fig. 9. (color online) Siulation results of the fully parallel filters. The frequency spectru before correction. The frequency spectru after correction. 3.3 Real-tie algorith ipleented in the FPGA We ipleented the real-tie algoriths within the FPGA device XC6VLX13T fro Xilinx Virtex-6 faily. The gain, offset, and tie-skew isatch errors are evaluated by the sine-wave fitting ethod [38]. As entioned above, the correction algoriths for the gain and offset isatch errors are coparatively sipler; therefore, we elaborate on the tie-skew error correction. The tie-skew error between the first ADC and the other three ADCs was easured, and the results is [,-.76,-.46,-.89] T s, with the axiu value around T s. Based on the aforeentioned fully parallel ethod, the data strea of each A/D conversion channel is split into four channels; the four-channel TIADC syste is converted to a 16-channel TIADC, with rearranged tie-skew error of [, -.76, -.46, -.89,,-.76, -.46, -.89,, -.76, -.46, -.89,, -.76, -.46, -.89] T s. According to the siulation results in the Matlab, an 8-tap FIR filter for every channel is adequate for tie-skew error correction. We can calculate the FIR filter coefficients according to Eq. (2), and further ipleent this 8-tap filter with 16 5-tap filter cells based on the poly-phase ethod, as shown in Fig. 1. Fig. 1 shows the structure of the 5-tap FIR filter atrix ipleented in the FPGA.

8 x [l] x 1[l] 5-tap FIR filter Matrix Pipeline adder F, F,1 F...,2 F,15 y [l] Multiplexer x 2[l] x 3[l+3] F 1, F 1,1 F,2... F 1,15 F 2, F 2,1 F 2,2... F 2,15 F 15, F 15,1 F 15,2... F 15,15 y 1[l] y 2[l] y 3[l+3] y[n] 16-bit Fig. 1. (color online) Block diagra of the correction algoriths. Structure of the poly-phase filter atrix. Block diagra of the filter atrix ipleented in the FPGA. Based on the fully parallel filter structure, the processing data strea is decreased fro 25 MHz to 62.5 MHz, which can be ipleented easily in real tie. As shown in Fig. 1, considering Channel 1, 5, 9 and 13 of the TIADC of the extracted 16 channels have no tie-skew error, Row 4, 8 12 and 16 have just one delay cell in the poly-phase filter atrix and about tap FIR filters are eployed. In theory, a total of 98 ultipliers are needed in this ethod. We verify this algorith with a 12-bit 1-Gsps syste, and of course we can ipleent these 98 ultipliers operating at 62.5 Msps. If the speed is enhanced to 25 Msps, this fully parallel correction algorith can support a real-tie processing with a speed up to 4 Gsps. In this application, we ultiplex the ultiplications to reduce the logic resource consuption and about 392 ultipliers (2 ultipliers for one 5-tap FIR filter) are ipleented, which operates at MHz (3 62.5MHz). The WFD photo is shown in Fig. 11. Fig. 11. (color online) The WFD photo. 4 Test results To evaluate the syste perforance, a series of tests were conducted. The WFD is plugged into the PC ainboard via a standard PCI Express connector. The input signal fro 5 MHz to 2 MHz is generated by a signal source R&S SMA1A, filtered by a coaxial band pass filter (BPF), and then input to the digitizer. The data results are transferred to the PC eory and analyzed with the software on the Matlab platfor. 4.1 Misatch error results Tests were conducted with signals with different frequencies, and then the four paraeter sine fit algorith was

9 applied to obtain the isatch values, as shown in Fig. 12. Correction algoriths were then designed with these isatch paraeters Offset(LSB) adc1_core1 adc1_core2 adc2_core1 adc2_core Input Signal Frequency (MHz) Gain(dB) adc1_core2-adc1_core1 adc2_core1-adc1_core1 adc2_core2-adc1_core Input Signal Frequency (MHz) Tie Skew Error(Ts) adc1_core2-adc1_core1 adc2_core1-adc1_core1 adc2_core2-adc1_core Input Signal Frequency (MHz) Fig. 12. (color online) Misatch errors easured. Offset isatch error. Gain isatch error. (c) Tie-skew error. (c) 4.2 Dynaic perforance test results Dynaic analysis of this TIADC syste is ipleented based on the IEEE Std [38]. The data before and after correction are acquired, with a length of saple points in each channel (4 channels in totality). Analysis is perfored through the Fast Fourier Transfor (FFT) and spectral averaging ethod. Fig. 14 shows the frequency spectra of test results with a 4.13 MHz input sinusoidal signal. Fig. 13 shows the frequency spectru of the data fro one single A/D conversion channel, no obvious spurious coponents are observed. By coparing Fig. 13 and Fig. 13(c) corresponding to the interleaved results before and after correction, the real-tie correction algoriths are proven to function well Aplitude(dB) SNR: SINAD: ENOB: 1.63 SFDR: Aplitude(dB) SNR: SINAD: ENOB: 7.89 SFDR: Aplitude(dB) SNR: SINAD: 64.3 ENOB: 1.56 SFDR: Analog Input Frequency(MHz) Analog Input Frequency(MHz) Analog Input Frequency(MHz) (c) Fig. 13. (color online) The frequency spectra of test results with a input sinusoidal signal of 4.13 MHz. The frequency spectru of one single A/D converter channel with saple frequency of 25 MHz; The frequency spectru of the TIADC syste with saple frequency of 1-Gsps before calibration; (c) The frequency spectru of the TIADC syste with saple frequency of 1-Gsps after calibration. Turning the input frequency fro 5 MHz to 2 MHz, systeatic tests were conducted on SINAD, SFDR, ENOB and SNR, as shown in Fig. 14. The test results indicate that the real-tie correction algoriths have significantly iproved the syste perforance, achieving an ENOB around 1.5 bits fro 5 MHz to 2 MHz.

10 SINAD(dBFS) 4 2 after correction before correction SFDR(dB) after correction before correction Analog Input Frequency (MHz) Analog Input Frequency (MHz) 12 8 ENOB(Bit) after correction before correction SNR(dBFS) after correction before correction Analog Input Frequency (MHz) Analog Input Frequency (MHz) (c) (d) Fig. 14. (color online) Dynaic test results before and after correction. SINAD test result. SFDR test result. (c) ENOB test result. (d) SNR test result. 4.3 PMT pulse signal test result PMTs are widely used in nuclear and particle physics [8, 4, 41]. We sapled a signal wavefor fro a PMT with a high-speed oscilloscope, and then used a 14-bit arbitrary wavefor generator Tektronix AFG3251 [42] to regenerate the PMT output signal (the rising tie is 3.1 ns, the falling tie is 9.9 ns) as the input pulse of this WFD. We also digitized this pulse with a LeCroy Oscilloscope 14MXi at the sae saple rate of 1-Gsps for coparison. As shown in Fig. 15, no obvious difference exists between the results of the WFD and the coercial oscilloscope, except that the WFD exhibits a better perforance with uch lower noise. 1-1 Aplitude (V) bit 1-Gsps wavefor digitizer LeCroy Oscilloscope 14MXi Tie (ns) Fig. 15. (color online) Coparison of the PMT pulse test results between the WFD and a 1-Gsps oscilloscope. 5 Suary

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