NCV7382/D. MARKING DIAGRAM. Features PIN CONNECTIONS ORDERING INFORMATION V7382 SO-8 D SUFFIX CASE 751 ALYW

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1 Enhanced LIN Transceiver The NCV7382 is a physical layer device for a single wire daa link capable of operaing in applicaions where high daa rae is no required and a lower daa rae can achieve cos reducions in boh he physical media componens and in he microprocessor which uses he nework. The NCV7382 is designed o work in sysems developed for LIN 1.3 or LIN 2.0. The IC furhermore can be used in ISO9141 sysems. Because of he very low curren consumpion of he NCV7382 in he sleep mode i's suiable for ECU applicaions wih low sandby curren requiremens. This mode allows a shudown of he whole applicaion. The included wakeup funcion deecs incoming dominan bus messages and enables he volage regulaor. Feaures Operaing Volage V S = 7.0 o 18 V Very Low Sandby Curren Consumpion of Typ. 6.5 A in Sleep Mode LIN-Bus Transceiver: Slew Rae Conrol for Good EMC Behavior Fully Inegraed Receiver Filer BUS Inpu Volage -27 V o 40 V Inegraed Terminaion Resisor for LIN Slave Nodes (30 k ) Wakeup Via LIN Bus Baud Rae up o 20 kbaud Will Work in Sysems Designed for Eiher LIN 1.3 or LIN 2.0 Compaible o ISO9141 Funcions High EMI Immuniy Bus Terminals Proec Agains Shor-Circuis and Transiens in he Auomoive Environmen High Impedance Bus Pin for Loss of Ground and Undervolage Condiion Thermal Overload Proecion High Signal Symmery for use in RC-Based Slave Nodes up o 2% Clock Tolerance when Compared o he Maser Node 1000 V ESD Proecion, Charged Device Model Conrol Oupu for Volage Regulaor wih Low On-Resisance for Swichable Maser Terminaion NCV Prefix for Auomoive and Oher Applicaions Requiring Sie and Change Conrol AEC Qualified PPAP Capable Pb-Free Packages are Available 8 1 SO-8 D SUFFIX CASE 751 PIN CONNECTIONS 1 8 (Top View) ORDERING INFORMATION MARKING DIAGRAM INH EN 2 7 V S V CC 3 6 BUS TxD 4 5 GND Device Package Shipping NCV7382D SO-8 95 Unis/Rail NCV7382DG V7382 A L Y W SO-8 (Pb-Free) 95 Unis/Rail NCV7382DR2 SO Tape & Reel NCV7382DR2G SO-8 (Pb-Free) V7382 ALYW 2500 Tape & Reel For informaion on ape and reel specificaions, including par orienaion and ape sizes, please refer o our Tape and Reel Packaging Specificaions Brochure, BRD8011/D. 8 1 = Specific Device Code = Assembly Locaion = Wafer Lo = Year = Work Week = Pb-Free Package Semiconducor Componens Indusries, LLC, 2007 Ocober, Rev. 4 1 Publicaion Order Number: NCV7382/D

2 INH NCV7382 V S Inernal Supply and References Biasing & Bandgap Thermal Shudown V CC POR 30 K TxD SLEW RATE CONTROL BUS Driver BUS EN MODE CONTROL Wakeup Filer GND Receive Comparaor Inpu Filer Figure 1. Block Diagram PACKAGE PIN DESCRIPTION Pin Symbol Descripion 1 RXD Receive daa from BUS o microprocessor, LOW in dominan sae. 2 EN Enables he normal operaion mode when HIGH. 3 V CC 5.0 V supply inpu. 4 TXD Transmi daa from microprocessor o BUS, LOW in dominan sae. 5 GND Ground. 6 BUS LIN bus pin, LOW in dominan sae. 7 V S Baery inpu volage. 8 INH Conrol oupu for volage regulaor, erminaion pin for maser pullup. 2

3 Elecrical Specificaion All volages are referenced o ground (GND). Posiive currens flow ino he IC. The maximum raings (in accordance wih IEC 134) given in he able below are limiing values ha do no lead o a permanen damage of he device bu exceeding any of hese limis may do so. Long erm exposure o limiing values may effec he reliabiliy of he device. OPERATING CONDITIONS Characerisic Symbol Min Max Uni V S V S V V CC V CC V Operaing Ambien Temperaure T A C MAXIMUM RATINGS Raing Symbol Condiion Min Max Uni V S V S < 1 min 30 V -0.3 Load Dump, < 500 ms 40 V CC V CC V Transien Supply Volage V S.r1 ISO 7637/1 Pulse 1 (Noe 1) V Transien Supply Volage V S..r2 ISO 7637/1 Pulses 2 (Noe 1) V Transien Supply Volage V S..r3 ISO 7637/1 Pulses 3A, 3B V BUS Volage V BUS < 500 ms, Vs = 18 V -27 < 500 ms,vs = 0 V -40 Transien Bus Volage V BUS..r1 ISO 7637/1 Pulse 1 (Noe 2) V Transien Bus Volage V BUS.r2 ISO 7637/1 Pulses 2 (Noe 2) V Transien Bus Volage V BUS.r3 ISO 7637/1 Pulses 3A, 3B (Noe 2) V DC Volage on Pins TxD, V DC V ESD Capabiliy, Charged Device Model V ESDCDM (Noe 3) kv ESD Capabiliy of BUS,, TxD, V CC, EN Pins ESD Capabiliy of V S Pin V ESDHBM Human Body Model, equivalen o discharge 100 pf wih 1.5 k (Noe 3) Maximum Lachup Free Curren a Any Pin I LATCH ma Maximum Power Dissipaion P o A T A = 125 C mw Thermal Impedance JA In Free Air C/W Sorage Temperaure T sg C Juncion Temperaure T J C LEAD TEMPERATURE SOLDERING REFLOW Lead Free, 60 sec -150 sec above 217, 40 sec Max a Peak T SLD Peak C Leaded, 60 sec -150 sec above 183, 30 sec Max a Peak T SLD Peak C Sresses exceeding Maximum Raings may damage he device. Maximum Raings are sress raings only. Funcional operaion above he Recommended Operaing Condiions is no implied. Exended exposure o sresses above he Recommended Operaing Condiions may affec device reliabiliy. 1. ISO 7637 es pulses are applied o V S via a reverse polariy diode and > 2.0 F blocking capacior. 2. ISO 7637 es pulses are applied o BUS via a coupling capaciance of 1.0 nf. 3. This device incorporaes ESD proecion and is esed by he following mehods: ESD HBM esed per AEC-Q (EIA/JESD22-A 114C) ESD CDM esed per EIA/JESD22-C 101C, Field Induced Model V kv 3

4 ELECTRICAL CHARACTERISTICS (V S = 7.0 o 18 V, V CC = 4.5 o 5.5 V and T A = -40 o 125 C unless oherwise noed.) Characerisic Symbol Condiion Min Typ Max Uni GENERAL V CC Undervolage Lockou V CC_UV EN = H, TxD = L V Supply Curren, Dominan I Sd V S = 18 V, V CC = 5.5 V, TxD = L ma Supply Curren, Dominan I CCd V S = 18 V, V CC = 5.5 V, TxD = L ma Supply Curren, Recessive I Sr V S = 18 V, V CC = 5.5 V TxD = H A Supply Curren, Recessive I CCr V S = 18 V, V CC = 5.5 V TxD = H A Supply Curren, Sleep Mode I Ssl V S = 12 V, V CC and TxD = 0 V, T A = A Supply Curren, Sleep Mode I Ssl V S = 12 V, V CC and TxD = 0 V A Thermal Shudown T sd (Noe 4) C Thermal Recovery T hys (Noe 4) C BUS TRANSMIT Shor Circui Bus Curren Pullup Curren Bus I BUS_LIM (Noes 5 and 6) I BUS_PU (Noes 5 and 6) V BUS = V S, Driver On ma V BUS = 0, V S = 12 V, Driver Off A Pullup Curren Bus I BUS_PU_SLEEP V BUS = 0, V S = 12 V, Sleep Mode A Bus Reverse Curren, Recessive Bus Reverse Curren Loss of Baery Bus Curren During Loss of Ground Transmier Dominan Volage Transmier Dominan Volage I BUS_PAS_rec (Noes 5 and 6) I BUS (Noes 5 and 6) I BUS_NO_GND (Noes 5 and 6) V BUSdom_DRV_2 (Noe 5) V BUSdom_DRV_3 (Noe 5) V BUS > V S, 8.0 V < V BUS < 18 V 7.0 V < V S < 18 V, Driver Off A V S = 0 V, 0 V < V BUS < 18 V A V S = 12 V, 0 < V BUS < 18 V ma V S = 7.0 V, Load = V V S = 18 V, Load = V Bus Inpu Capaciance C BUS (Noe 4) Pulse Response via 10 k V PULSE = 12 V, V S = Open pf BUS RECEIVE Receiver Dominan Volage Receiver Recessive Volage Cener Poin of Receiver Threshold V BUSdom (Noes 5 and 6) V BUSrec (Noes 5 and 6) V BUS_CNT (Noes 4, 5 & 6) *V S - - V *V S V V BUS_CNT = (V BUSdom + V BUSrec )/ *V S 0.5*V S 0.512*V S V Receiver Hyseresis V HYS (Noes 4, 5 & 6) 4. No producion es, guaraneed by design and qualificaion. 5. In accordance o LIN physical layer specificaion In accordance o LIN physical layer specificaion 2.0. V BUS_CNT = (V BUSrec - V BUSdom ) *V S - V 4

5 ELECTRICAL CHARACTERISTICS (V S = 7.0 o 18 V, V CC = 4.5 o 5.5 V and T A = -40 o 125 C unless oherwise noed.) Characerisic Symbol Condiion Min Typ Max Uni TXD, EN High Level Inpu Volage V ih Rising Edge *V CC V Low Level Inpu Volage V il Falling Edge 0.3*V CC - - V TxD Pullup Resisor R IH_TXD V TxD = 0 V k EN Pulldown Resisor R IL_EN V EN = 5.0 V k RXD Low Level Oupu Volage V ol_rxd I = 2.0 ma V Leakage Curren V leak_rxd V = 5.5 V, Recessive A INH On Resisance R on_inh Normal or Sandby Mode, V INH = V S V, V S = 12 V Leakage Curren I INH_lk EN = L, V INH = 0 V A AC CHARACTERISTICS Characerisic Symbol Condiion Min Typ Max Uni Propagaion Delay Transmier (Noes 7 and 9) Propagaion Delay Transmier Symmery (Noes 8 and 9) Propagaion Delay Receiver (Noes 7, 9, 12, 13 and 14) Propagaion Delay Receiver Symmery (Noes 9, 11 and 12) rans_pdf rans_pdr Bus Loads: 1.0 K /1.0 nf, 660 /6.8 nf, 500 /10 nf s rans_sym Calculae rans_pdf - rans_pdr s rec_pdf C = 20 pf s rec_pdr rec_sym Calculae rans_pdf - rans_pdr s Slew Rae Rising and Falling Edge, High Baery (Noes 8, 11 and 12) Slew Rae Rising and Falling Edge, Low Baery (Noes 8, 11 and 12) Slope Symmery, High Baery (Noes 11 and 12) Bus Duy Cycle (Noe 13) SR_HB Bus Loads: V S = 18 V, 1.0 K /1.0 nf, 660 /6.8 nf, 500 /10 nf SR_LB Bus Loads: V S = 7.0 V, 1.0 K /1.0 nf, 660 /6.8 nf, 500 /10 nf ssym_hb Bus Loads: V S = 18 V, 1.0 k /1.0 nf, 660 /6.8 nf, 500 /10 nf, Calculae sdom srec D1 D2 Calculae BUS_rec(min) /100 s Calculae BUS_rec(max) /100 s V/ s V/ s s s/ s s/ s Receiver Debounce Time (Noes 8, 11 and 14) rec_deb BUS Rising and Falling Edge s Wakeup Filer Time wu Sleep Mode, BUS Rising & Falling Edge EN - Debounce Time en_deb Normal -> Sleep Mode Transiion s s 7. Propagaion delays are no relevan for LIN proocol ransmission, value only informaion parameer. 8. No producion es, guaraneed by design and qualificaion. 9. See Figure 2 - Inpu/Oupu Timing. 10.See Figure 8 - Slope Time Calculaion. 11. See Figure 3 - Receiver Debouncing. 12.In accordance o LIN physical layer specificaion In accordance o LIN physical layer specificaion This parameer is esed by applying a square wave o he bus. The minimum slew rae for he bus rising and falling edges is 50 V/ s. 5

6 TIMING DIAGRAMS TxD 50% V BUS rans_pdf 95% 100% rans_pdr BUS 50% 50% 0% 5% rec_pdf rec_pdr 50% Figure 2. Inpu/Oupu Timing < rec_deb < rec_deb V BUS 60% 40% V 50% Figure 3. Receiver Debouncing 6

7 V BUS > wu V INH wu V CC V EN V wakeup inerrup Figure 4. Sleep Mode and Wakeup Procedure 7

8 TEST CIRCUITS FOR DYNAMIC AND STATIC CHARACTERISTICS NCV7382 V S V CC R L 100 nf 100 nf BUS EN C L TxD 2.7 K 10 K INH GND 20 pf Figure 5. Tes Circui for Dynamic Characerisics F + V S NCV7382 V CC EN 100 n 1 nf BUS TxD GND Oscilloscope Schaffner- Generaor Puls3a,3b Puls1,2,4 12 V + - Figure 6. Tes Circui for Auomoive Transiens 8

9 Funcional Descripion Iniializaion Afer power on, he chip auomaically eners he V BAT -sandby mode. In his inermediae mode he INH oupu will become HIGH (V S ) and herefore he ECU - volage regulaor will provide he V CC -supply. The ransceiver will remain in he V BAT sandby mode unil he conroller ses i o normal operaion (EN = High). Bus communicaion is only possible in normal mode. The NCV7382 swiches iself o he V BAT -sandby mode if V CC is missing or below he undervolage lockou hreshold. Operaing Modes The EN pin is used o swich he NCV7382 ino differen operaing modes. Normal Mode All of he NCV7382 is acive. Swiching o normal mode can only be done wih EN = high. Sleep Mode The sleep mode (EN = LOW) can only be reached from normal mode and permis a very low power consumpion because he ransceiver and he exernal volage regulaor are disabled. If V CC has been swiched off, a wakeup reques from he bus line (remoe wakeup) will cause he NCV7382 o ener he V BAT -sandby mode (V CC is presen again) and ses he oupu o low unil he device eners he normal operaion mode (acive LOW inerrup a ). If he INH pin is no conneced o he regulaor or he inhibiable exernal regulaor is no he one ha provides he V CC - supply, he normal mode is direcly accessible by logic high on he EN pin. (Wakeup via mode change/local wakeup.) In order o preven an uninended wakeup caused by disurbances in he auomoive environmen, incoming dominan signals from he bus have o exceed he wakeup delay ime. Thermal Shudown Mode If he juncion emperaure T J is higher han 155 C, he NCV7382 could be swiched ino he hermal shudown mode. Transmier will be swiched off. If T J falls below he hermal shudown emperaure (yp. 140 C), he NCV7382 will be swiched o he previous sae. Table 1. Mode Conrol EN V CC Commen INH 0 0 V BAT -sandby, Power On Vs V BAT -sandby, V CC On Vs X 1 1 Normal Mode Vs V CC = Recessive 0 = Dominan 0 0 Sleep Mode Floaing Sleep Mode Regulaor no disabled Direcly swich o normal mode wih EN = 1 Floaing V CC 0 0/1 Remoe wakeup reques Vs 0 - Acive low wakeup inerrup LIN BUS Transceiver The ransceiver consiss of a bus-driver ( ma) wih slew rae conrol, curren limi, and a receiver wih a high volage comparaor wih filer circuiry. BUS Inpu/Oupu The recessive BUS level is generaed from he inegraed 30 k pullup resisor in series wih a diode. The diode prevens he reverse curren on V BUS when V BUS > V S. No addiional erminaion resisor is necessary o use he NCV7382 on LIN slave nodes. If his IC is used for LIN maser nodes, i is necessary o erminae he bus wih an exernal 1.0 k resisor in series wih a diode o V BAT or INH (See Secion Shor Circui o Ground). TxD Inpu During ransmission he signal on TxD will be ransferred o he BUS driver for generaing a BUS signal. To minimize he elecromagneic emission of he bus line, he BUS driver has inegraed slew rae conrol and wave shaping. Transmiing will be inerruped in he following cases: Sleep Mode Thermal Shudown V BAT -sandby The CMOS compaible inpu TxD direcly conrols he BUS level: TxD = low BUS = low (dominan level) TxD = high BUS = high (recessive level) 9

10 The TxD pin has an inernal pullup resisor conneced o V CC. This secures ha an open TxD pin generaes a recessive BUS level. Oupu The signal on he BUS pin will be ransferred coninuously o he pin. Shor spikes on he bus signal are filered wih inernal circuiry (Figure 3 and Figure 7). V S V BUS_CNT_max 60% BUS 50% V hhys 40% V BUS_CNT_min < rec_deb < rec_deb Figure 7. Receive Impulse Diagram The receive hreshold values V BUS_CNT_max and V BUS_CNT_min are symmerical o 0.5 * V S wih a hyseresis of 0.16 * V S (ypical). The LIN specific receive hreshold is beween 0.4 * V S and 0.6*V S. The received BUS signal will be oupu o he pin: BUS < V BUS_CNT 0.5 * V HYS = low (BUS dominan) BUS > V BUS_CNT * V HYS = high, floaing (BUS recessive) is a buffered open drain oupu wih a ypical load of: Resisance: 2.7 k Capaciance: < 20 pf EN-Pin The NCV7382 is swiched ino sleep mode wih a falling edge and ino normal mode wih a rising edge of he EN pin. I will remain in normal mode as long as EN = high (See Figure 4 - Sleep Mode and Wakeup Procedure for more deails). When he NCV7382 is swiched o sleep mode, he volage regulaor on he INH pin is swiched off. The NCV7382 can be urned off wih EN = low independen of he sae of he bus-ransceiver. The EN inpu has an inernal pulled down o guaranee a low level wih EN floaing. Daa Rae The NCV7382 is a consan slew rae ransceiver. The bus driver operaes wih a fixed slew rae range of 1.0 V/ s V/ T 3.0 V/ s. This principle provides very good symmery of he slope imes beween recessive o dominan and dominan o recessive slopes wihin he LIN bus load range (C BUS, R erm ). The NCV7382 guaranees daa raes up o 20 kbi wihin he complee bus load range under wors case condiions. The consan slew rae principle holds appropriae volage levels and can operae wihin he LIN Proocol Specificaion for RC oscillaor sysems wih a maching olerance up o 2%. Operaing Under Disurbance Loss of Baery If V S and V CC are disconneced from he baery, he bus pin is in high impedance sae. There is no impac o he bus raffic. Loss of Ground In case of an inerruped ground connecion from V S and V CC, here is no influence o he bus line. Shor Circui o Baery The ransmier oupu curren is limied o 200 ma (max) in case of shor circui o baery. Shor Circui o Ground Negaive volages on he BUS pin are limied primarily o curren hrough he inernal 30 k resisor and series diode from V S hrough a swiched device conrolled by EN. Secondary conribuions are aribued o he resisor and diode hardwired from V S o BUS. 10

11 Sysem designs can have an exernal resisor (1 k) in series wih an exernal diode o he baery, bu shor circui curren from bus o ground can be reduced dramaically by using he INH pin as erminaion pin for he maser pullup (See Figure 10 - Applicaion Circuiry). Wih his new seup, he conroller can deec a shor circui of he bus o ground ( imeou) and he ransceiver can be se ino sleep mode. The INH pin will be floaing in his case, and he exernal maser pullup resisor will be disconneced from he bus line. Addiionally, he inernal slave erminaion resisor is swiched off and only a high impedance erminaion is applied o he bus (yp. 75 A). This will reduce he failure curren of he sysem by a leas an order of magniude, prevening a fas Applicaion Hins NCV7382 discharge of he car baery. If he failure is removed, he bus level will become recessive again and will wakeup he sysem even if no local wakeup is presen or possible. Thermal Overload The NCV7382 is proeced agains hermal overloads. If he chip emperaure exceeds he hermal shudown hreshold, he ransmier is swiched off unil hermal recovery. The receiver coninues o work during hermal shudown. Undervolage V CC The V CC undervolage lockou feaure disables he ransmier unil i is above he undervolage lockou hreshold o preven undesirable bus raffic. LIN Sysem Parameer Bus Loading Requiremens Parameer Symbol Min Typ Max Uni Operaing Volage Range V BAT V Volage Drop of Reverse Proecion Diode V Drop_rev V Volage Drop a he Serial Diode in Pullup Pah V SerDiode V Baery Shif Volage V Shif_BAT V BAT Ground Shif Volage V Shif_GND V BAT Maser Terminaion Resisor R maser Slave Terminaion Resisor R slave k Number of Sysem Nodes N Toal Lengh of Bus Line LEN BUS m Line Capaciance C LINE pf/m Capaciance of Maser Node C Maser pf Capaciance of Slave Node C Slave pf Toal Capaciance of he Bus including Slave and Maser Capaciance C BUS nf Nework Toal Resisance R Nework Time Consan of Overall Sysem s Recommendaions for Sysem Design The goal of he LIN physical layer sandard is o have a universal definiion of he LIN sysem for plug and play soluions in LIN neworks up o 20 kbd bus speeds. In case of small and medium LIN neworks, i's recommended o adjus he oal nework capaciance o a leas 4.0 nf for good EMC and EMI behavior. This can be done by seing only he maser node capaciance. The slave node capaciance should have a uni load of ypically 220 pf for good EMC/EMI behavior. In large neworks wih long bus lines and he maximum number of nodes, some sysem parameers can exceed he defined limis and of he LIN sysem designer mus inervene. The whole capaciance of a slave node is no only he uni load capacior iself. Addiionally, here is he capaciance of wires and connecors, and he inernal capaciance of he LIN ransmier. This inernal capaciance is srongly dependen on he echnology of he IC manufacurer and should be in he range of 30 pf o 150 pf. If he bus lines have a oal lengh of nearly 40 m, he oal bus capaciance can exceed he LIN sysem limi of 10 nf. A second parameer of concern is he inegraed slave erminaion resisor olerance. If mos of he slave nodes have a slave erminaion resisance a he allowed maximum of 60 k, he oal nework resisance is more han 700. Even if he oal nework capaciance is below or equal o he maximum specified value of 10 nf, he nework ime consan is higher han 7.0 s. This problem can be solved only by adjusing he maser erminaion resisor o he required maximum nework ime consan of 5.0 s (max). 11

12 NOTE: The seing of he nework ime consan is necessary in large neworks (primarily resisance) and also in small neworks (primarily capaciance). The NCV7382 mees he requiremens for implemenaion in RC-based slave nodes. The LIN Proocol Specificaion requires he deviaion of he slave node clock o he maser node clock afer synchronizaion mus no differ by more han 2%. MIN/MAX SLOPE TIME CALCULATION (In accordance o he LIN Sysem Parameer Table) V BUS 100% 60% 60% 40% 40% 0% V dom sdom srec Figure 8. Slope Time and Slew Rae Calculaion (In accordance o LIN physical layer specificaion 1.3) The slew rae of he bus volage is measured beween 40% and 60% of he oupu volage swing (linear region). The oupu volage swing is he difference beween dominan and recessive bus volage. dv d 0.2 * Vswing (40%-60%) The slope ime is he exension of he slew rae angen unil he upper and lower volage swing limis: slope 5 * (40%-60%) The slope ime of he recessive o dominan edge is direcly deermined by he slew rae conrol of he ransmier: slope Vswing dv d The dominan o recessive edge is influenced from he nework ime consan and he slew rae conrol, because i's a passive edge. In case of low baery volages and high bus loads he rising edge is only deermined by he nework. If he rising edge slew rae exceeds he value of he dominan one, he slew rae conrol deermines he rising edge. 12

13 Bi Bi TxD dom(max) rec(min) V SUP 100% dom(min) 74.4% BUS 58.1% 42.2% 58.1% 28.4% rec(max) 28.4% GND 0% Figure 9. Duy Cycle Measuremen and Calculaion in Accordance o LIN Physical Layer Specificaion 2.0 Duy Cycle Calculaion Wih he iming parameers shown in Figure 9 wo duy cycles, based on rec(min) and rec(max) can be calculaed as follows: D1* = rec(min) /(2 x Bi ) D2* = rec(max) /(2 x Bi ) For proper operaion a 20 kbi/s (bi ime is 50 s) he LIN driver has o fulfill he duy cycles specified in he AC characerisics for supply volages of V and he hree defined sandard loads. Due o his simple definiion here is no need o measure slew raes, slope imes, ransmier delays and dominan volage levels as specified in he LIN physical layer specificaion 1.3. The devices wihin he D1/D2 duy cycle range also operaes in applicaions wih reduced bus speed of 10.4 kbi/s or below. In order o minimize EME, he slew raes of he ransmier can be reduced (by up o 2 imes). Such devices have o fulfill he duy cycle definiion D3/D4 in he LIN physical layer specificaion 2.0. Devices wihin his duy cycle range canno operae in higher frequency 20 kbi/s applicaions. *D1 and D2 are defined in he LIN proocol specificaion

14 Igniion Car Baery 1N F LIN BUS V BAT V IN Volage Regulaor NCV nf Slave ECU V OUT 10 k Rese 10 F 47 nf 100 nf 2.7 K V CC V S BUS P GND NCV7380* TxD GND 220 pf ECU Connecor o Single Wire LIN Bus *The NCV7380 is a pin compaible low cos ransceiver wihou INH conrol. 1N F V BAT V IN Volage Regulaor NCV8501 ENABLE 10 k 100 nf Maser ECU 10 F V OUT 10 k Rese 47 nf 100 nf 47 nf P GND 2.7 K V CC INH V S NCV7382 TxD BUS EN GND 220 pf 1 K ECU Connecor o Single Wire LIN Bus Figure 10. Applicaion Circuiry 14

15 ESD/EMC Remarks General Remarks Elecronic semiconducor producs are sensiive o Elecro Saic Discharge (ESD). Always observe Elecro Saic Discharge conrol procedures whenever handling semiconducor producs. ESD Tes The NCV7382 is esed according o MIL883D (human body model). EMC The es on EMC impacs is done according o ISO for power supply pins and ISO for daa and signal pins. POWER SUPPLY PIN V S Tes Pulse Condiion Duraion 1 1 = 5.0 s/u S = -100 V/ D = 2.0 ms 5000 Pulses 2 1 = 0.5 s/u S = 100 V/ D = 0.05 ms 5000 Pulses 3a/b U S = -150 V/U S = 100 V Burs 100 ns/10 ms/90 ms Break 1 h 5 R i = 0.5, D = 400 ms r = 0.1 ms/u P + U S = 40 V 10 Pulses Every 1 Min DATA AND SIGNAL PINS EN, BUS Tes Pulse Condiion Duraion 1 1 = 5.0 s/u S = -100 V/ D = 2.0 ms 1000 Pulses 2 1 = 0.5 s/u S = 100 V/ D = 0.05 ms 1000 Pulses 3a/b U S = -150 V/U S = 100 V Burs 100 ns/10 ms/90 ms Break 1000 Burs 15

16 PACKAGE DIMENSIONS SOIC-8 NB CASE ISSUE AJ -X- B -Y- 8 1 A 5 4 S 0.25 (0.010) M Y M K NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION THRU ARE OBSOLETE. NEW STANDARD IS Z- H G D C 0.25 (0.010) M Z Y S X S SEATING PLANE 0.10 (0.004) N X 45 M J MILLIMETERS INCHES DIM MIN MAX MIN MAX A B C D G 1.27 BSC BSC H J K M N S SOLDERING FOOTPRINT* SCALE 6:1 mm inches *For addiional informaion on our Pb-Free sraegy and soldering deails, please download he ON Semiconducor Soldering and Mouning Techniques Reference Manual, SOLDERRM/D. ON Semiconducor and are regisered rademarks of Semiconducor Componens Indusries, LLC (SCILLC). SCILLC reserves he righ o make changes wihou furher noice o any producs herein. SCILLC makes no warrany, represenaion or guaranee regarding he suiabiliy of is producs for any paricular purpose, nor does SCILLC assume any liabiliy arising ou of he applicaion or use of any produc or circui, and specifically disclaims any and all liabiliy, including wihou limiaion special, consequenial or incidenal damages. Typical parameers which may be provided in SCILLC daa shees and/or specificaions can and do vary in differen applicaions and acual performance may vary over ime. All operaing parameers, including Typicals mus be validaed for each cusomer applicaion by cusomer's echnical expers. SCILLC does no convey any license under is paen righs nor he righs of ohers. SCILLC producs are no designed, inended, or auhorized for use as componens in sysems inended for surgical implan ino he body, or oher applicaions inended o suppor or susain life, or for any oher applicaion in which he failure of he SCILLC produc could creae a siuaion where personal injury or deah may occur. Should Buyer purchase or use SCILLC producs for any such uninended or unauhorized applicaion, Buyer shall indemnify and hold SCILLC and is officers, employees, subsidiaries, affiliaes, and disribuors harmless agains all claims, coss, damages, and expenses, and reasonable aorney fees arising ou of, direcly or indirecly, any claim of personal injury or deah associaed wih such uninended or unauhorized use, even if such claim alleges ha SCILLC was negligen regarding he design or manufacure of he par. SCILLC is an Equal Opporuniy/Affirmaive Acion Employer. This lieraure is subjec o all applicable copyrigh laws and is no for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Lieraure Disribuion Cener for ON Semiconducor P.O. Box 5163, Denver, Colorado USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderli@onsemi.com N. American Technical Suppor: Toll Free USA/Canada Europe, Middle Eas and Africa Technical Suppor: Phone: Japan Cusomer Focus Cener Phone: ON Semiconducor Websie: Order Lieraure: hp:// For addiional informaion, please conac your loca Sales Represenaive NCV7382/D

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