Course Introduction. Content: 22 pages 4 questions. Learning Time: 30 minutes

Transcription

1 Course Introduction Purpose: The intent of this course is to give you a brief overview of the S08 internal clock generator (ICG) module and the internal clock source (ICS) module, including the clock modes and special features of each. Objectives: Identify all four clock modes available in the ICG module. Describe the additional and functional features in the ICG module. Identify all four clock modes available in the ICS module. Describe additional and functional features in the ICS module. Content: 22 pages 4 questions Learning Time: 30 minutes This course will present you with a brief overview of the S08 internal clock generator (ICG) and internal clock source (ICS) modules. You will learn about the important features of these modules as well as the different clock modes available. By the end of this course, you will have a better understanding of the basic functionality of the ICG and ICS modules, and you will be better prepared to select the best clock mode for your application.

2 ICG Four modes of operation: Self-clock (SCM) mode Frequency-locked loop (FLL) Engaged, Internal (FEI) clock mode FLL Bypassed, External (FBE) clock mode FLL Engaged, External (FEE) clock mode FEI and SCM require no external components All modes are software selectable User program can switch between modes at any time Bus frequency = ½ ICGOUT Let s start by looking at the ICG module. The ICG module includes four modes of operation: a Self-clock (SCM) mode; Frequency-locked loop (FLL) Engaged, Internal (FEI) mode; FLL Bypassed, External (FBE) mode; and FLL Engaged, External (FEE) mode. Two of these modes, FEI and SCM, require no external components and run off of the microcontroller s internal clock. All modes are software selectable. For greater flexibility, the user software can switch between ICG modes at any time. As a rule of thumb, the microcontroller bus frequency is equal to the ICGOUT frequency divided by two.

3 ICG Block Diagram ICGERCLK Oscillator (OSC) With External Reference Select ICG Clock Select Ref Select Frequency Locked Loop (FLL) DCO Output Clock Select R ICGOUT ICGRCLK Loss of Lock and Clock Detector Fixed Clock Select FFE Internal Reference Generators IRG Typ 243 khz Local RG Typ 8 MHz ICGLCLK Here you can see a functional block diagram of the ICG module. The ICG consists of four main functional blocks. The oscillator block allows the user to connect an external crystal or resonator with the ICG. The user can select either a high frequency range between 1 and 16 MHz or a low frequency range between 32 and 100 khz for the crystal or resonator. Also, the oscillator block can be used to route a square wave frequency from a signal generator or other equivalent oscillator source to the system. For increased flexibility, the user can also configure the oscillator block for low power or high amplitude. The internal reference generator includes an 8 MHz clock source, which can be selected as the local clock for the background debug controller, and a 243 khz clock, which can be trimmed for accuracy to provide a highly reliable, low-cost clock source. The FLL block takes the internal or external clock source and multiplies it to a higher frequency. Finally, the clock select block controls the switching of different clock sources to the system clock tree. It determines ICGOUT, which is the output ICG frequency fed to the bus clock; the ICGERCLK, which is the reference clock frequency from the crystal or external clock source; and the fixed frequency enable (FFE), which controls the system fixed frequency clock. The ICGLCLK is the 8 MHz clock source generated by the internal reference generator block for use by the background debug controller.

4 ICG Modes SCM: Default mode out of reset Fast, reliable startup at 4 MHz bus with no user programming No external connections required Oscillator pins can be used as general I/O Not trimmable but can be modified by writing ICGFLT registers (not really recommended) Least accurate of the four modes Medium power consumption (less than FEI or FEE modes) Next, let s discuss the various ICG modes available for use. SCM is the default ICG mode out of reset. ICGOUT is generally 8 MHz at this time, which results in a fast, reliable startup at 4 MHz bus frequency with no user programming. No external oscillator connections are required, so oscillator pins can be used as general I/O pins. The SCM frequency is not trimmable, but it can be modified by writing to the ICGFLT registers. However, this is not recommended without sufficient knowledge of how the ICGFLT registers operate. This mode is the least accurate of the four modes. It consumes less power than FEI or FEE modes and more power than FBE mode.

5 ICG Modes FEI clock mode: f OUT = 243,000 7 x 64 x N R N = 4 to 18, in increments of 2 R = 1 to 128, in powers of 2 Reference trimmable ± 25 percent to within 0.4 percent accuracy Loss of FLL lock software selectable as either reset or interrupt Oscillator pins can be used as general I/O No external components required Power consumption higher than SCM Now, let s move on to FEI mode. FEI is the only other ICG mode that does not require an external clock source. It allows the user to derive a clock frequency based off the internal 243 khz clock using the formula f OUT equals 243,000 divided by 7 times 64 times N divided by R. In this formula, N represents the multiplication factor between 4 and 18 in increments of 2, and R represents the reduced frequency divider (RFD) between 1 and 128 in powers of 2. Both of these values are software-programmable in ICG control register 2. In FEI mode, the reference clock is plus or minus 25 percent trimmable to within 0.4 percent accuracy. The reference clock is accurate to typically plus or minus 0.5 percent across temperature and voltage. The user can set loss of FLL lock detection in software to trigger either a reset or an interrupt condition. As in SCM mode, when the ICG is in FEI mode, oscillator pins can be used as general I/O pins. Therefore, no external pins are required. FEI mode also consumes more power than SCM mode but less power than FLL-engaged external mode consumes when the oscillator range is high.

6 ICG Modes FBE clock mode: External crystal or resonator: Low range: 32 khz to 100 khz High range: 1 MHz to 16 MHz External clock DC to 40 MHz Bus frequency = external reference (2 x RFD) Highest accuracy system clock (as accurate as the external source) Lowest power consumption Now, we will discuss the ICG modes that require an external reference clock. As in SCM mode, FBE mode does not use the FLL block to multiply the external clock frequency. When an external crystal or resonator is used as the clock source, its frequency must fall between 32 khz and 100 khz for a low range operation and between 1 MHz and 16 MHz for a high range operation. Be sure to set the REFS bit in the ICG control register 1 when using an external crystal or resonator. On the other hand, when using an external square wave clock such as the frequency generated by a signal generator, the range is ignored and the frequency is limited to 40 MHz. In this case, the REFS bit remains clear. Because the ICGOUT signal frequency is equal to the external reference clock divided by the RFD (which is specified in ICG control register 2) the bus frequency is equal to the external reference divided by two times the RFD. In other words, if the RFD equals 1 and the reference frequency equals 16 MHz, the bus frequency is 8 MHz. FBE mode provides the most accurate system clock. However, the system clock is only as accurate as the external source. FBE mode also consumes the least power of all four ICG modes.

7 ICG Modes FEE clock mode: External reference frequency range Low range: 32 khz to 100 khz, f OUT = f EXT x 64 x N R High range: 2 MHz to 10 MHz, f OUT = f EXT x N R N = 4 to 18, in increments of 2 R = , in powers of 2 High accuracy (not as accurate as the external source) Loss of lock software selectable as either reset or interrupt Power consumption slightly higher or lower than FEI, depending on external source range Lastly, FEE mode also requires an external reference clock. The generated system clock frequency is derived from the external reference clock. It is accomplished using two formulas that are programmable to multiples of the external reference depending on the frequency range. For a low range reference frequency between 32 and 100 khz, the output frequency formula shown here includes an additional multiplier of 64. For a high range reference frequency between 2 and 10 MHz, the output frequency formula shown here includes a multiplier of 1. In these formulas, N is the multiplication factor between 4 and 18 in increments of 2, and R is the RFD between 1 and 128 in powers of 2. The clock frequency generated in FEE mode is highly accurate, but not quite as accurate as the external source. As in FBE mode, loss of lock can generate either a reset or an interrupt depending on the user s preference in software. FEE mode consumes more power than FEI mode when the external reference frequency is in the high range, but less power than FEI mode in the low range.

8 ICG Features ICG Features Low power or high gain oscillator options Clock monitor Software selectable RFD Low power limits voltage swing on oscillator pins Automatically switches modes RFD is available in all ICG modes High gain drives oscillator pins to rail Software selectable for reset or interrupt Can be disabled for power savings Divides by 1, 2, 4, 8, 16, 32, 64, or 128 Allows frequency changes without losing FLL Lock Default RFD value after reset is 1 Let s look at several additional features to take note of when using the ICG module. These include low power or high gain oscillator options, a clock monitor, and the softwareselectable reduced frequency divider (RFD). Not all S08s with the ICG module include all of these features. Consult the device-specific data sheets to guarantee proper operation of the module. You can access the device-specific data sheets by visiting the Web site shown here. The high gain oscillator select (HGO) bit in ICG control register 1 determines whether the ICG operates in low power or high gain mode. To minimize power consumption, low power mode will limit the voltage swing on the oscillator pins. On the other hand, high gain mode drives rail-to rail-voltage swings on the oscillator pins in noisy environments. The clock monitor takes precautionary measures upon loss of clock and loss of lock detection. If the clock is lost, the clock monitor automatically switches clock modes. For greater flexibility, the user can configure the clock monitor in software to generate a reset or interrupt on loss of clock or loss of lock. To save power, the clock monitor can be disabled. The software-selectable RFD is located in ICG control register 2 and is available in all ICG modes. It allows the reference clock, both internal and external, to be divided by powers of 2 between 1 and 128. With the RFD, frequency changes can occur without the FLL losing lock. The default value for the RFD after reset is divide by one.

9 STOP Effects on ICG Exit from Stop 1 or Stop 2 always uses the default SCM mode to start up quickly. Exit from Stop 3 can use an external oscillator or the programmed ICG. The selected clock generator can optionally continue to run up to 20 MHz bus frequency. FEI mode startup is immediate at pre-stop frequency FEE mode Startup is immediate at 1/2 pre-stop frequency in SCM until stabilization time and then switch to external reference FBE mode Startup is delayed based on external reference stabilization time NOTE: ICG mode does not affect current before entering Stop 3. The ICG module behaves differently during STOP mode recovery, depending on the STOP state prior to wakeup. Exit from Stop 1 and Stop 2 modes always uses the default SCM mode for quick startup. Exit from Stop 3 allows usage of either an external oscillator or the programmed ICG. The selected clock generator can optionally continue to run up to 20 MHz bus frequency, which enables a faster startup time. Startup from Stop 3 occurs under different conditions, depending on the ICG mode. Here you can see a description of these conditions based on the other three ICG clock modes. Note that ICG mode does not affect current before entering Stop 3, so there is no need to switch ICG modes before executing the STOP instruction.

10 Question Can you remember the four clock modes for the ICG module? Match each mode on the left with its description on the right. Click Done when you are finished. This mode provides the most accurate system C clock, which is only as accurate as the external A SCM source. B C FEI FBE D This mode generates a clock frequency that is highly accurate, but not quite as accurate as the external source. D FEE A This mode is the default ICG mode out of reset. B This mode allows the user to derive a clock frequency based off the internal 243 khz clock using the formula f OUT = 243,000 7 x 64 x N R. Done Reset Show Solution Let s take a moment to review the ICG clock modes. Correct. The SCM mode is the default ICG mode out of reset. The FEI mode allows the user to derive a clock frequency based off the internal 243 khz clock using the formula f OUT = 243,000 7 x 64 x N R. The FBE mode provides the most accurate system clock, which is only as accurate as the external source. The FEE mode generates a clock frequency that is highly accurate, but not quite as accurate as the external source.

11 Question What are some of the features of the ICG module in the S08 series? Select all that apply and then click Done. RFD, located in ICG control register 2, is available in most ICG modes and allows the reference clock to be divided by powers of 3. The default value for the RFD after reset is divide by 2. To minimize power consumption, low power mode is available to limit the voltage swing on the oscillator pins. Not all S08s with the ICG module include all of the features described in this course. Done Please select all correct statements concerning the features of the ICG module. Correct. The RFD, which is located in the ICG control register 2, is available in all ICG modes and allows the reference clock to be divided by powers of 2, between 1 and 128. The default value for the RFD after reset is divide by 1. Low power mode, determined by the HGO bit, will limit the voltage swing on the oscillator pins. This minimizes power consumption. Not all S08s with the ICG module include all of these features. The device-specific data sheets provide further information for the proper operation of the module.

12 ICS Four modes of operation: FLL Bypassed, Internal (FBI) clock mode FLL Engaged, Internal (FEI) clock mode FLL Bypassed, External (FBE) clock mode FLL Engaged, External (FEE) clock mode FEI and FBI require no external components All modes are software selectable User program can switch between modes at any time Bus frequency = ½ ICSOUT Let s continue with a look at the ICS module. It includes four modes of operation: FLL Bypassed, Internal (FBI) mode, FEI mode, FBE mode, and FEE mode. Two of these modes, FEI and FBI, require no external components and run off of the microcontroller s internal clock. All of these modes are software selectable. For greater flexibility, the user software can switch between ICS modes at any time. As a rule of thumb, the microcontroller bus frequency is equal to the ICSOUT frequency divided by two.

13 ICS Block Diagram Oscillator (OSC) With External Reference Select ICSERCLK ICS Clock Select Ref Select Frequency Locked Loop (FLL) DCO Output Clock Select R ICSOUT ICSLCLK Filter Fixed Clock Select ICSFFCLK IRG to khz Internal Reference Generator ICSIRCLK Here you can see a functional block diagram of the ICS module. The ICS consists of four main functional blocks. The oscillator block allows the user to connect an external crystal or resonator for use with the ICS. The user can select either a high frequency range of 1 to 5 MHz in all modes, or a low frequency range of 32 to 38.4 khz for the crystal or resonator. Check the XOSC and ICS electrical characteristics in the device datasheet for additional high range frequency limits for different ICS modes. Visit the Web site shown here to access the device datasheet. Also, the oscillator block can be used to route a square wave frequency from a signal generator or other equivalent oscillator sources to the system. For increased flexibility, the user can also configure the oscillator block for low power or high amplitude. The internal reference generator includes a to khz ICS that is presented as ICSIRCLK in the block diagram. This frequency can be trimmed by writing to the ICSTRM register. The FLL block takes the internal or external clock source and filters it before locking at 512 times the filtered frequency. Finally, the clock select block controls the switching of different clock sources to the system clock tree. It manages the clock source select; the reference divider between 1 and 128, in powers of 2; and the fixed clock select, which appears as an ICSFFCLK signal. The ICSLCLK signal uses the to khz internal clock as an alternative softwareselectable clock source for the background debug controller.

14 ICS Modes FEI clock mode: Default mode out of reset Multiplier fixed to x 512 Reference is trimmable with resolution of 0.2 percent Bus frequency = DCO (2 x BDIV) DCO = internal reference x 512 Internal reference frequency = to khz DCO = 16 to 20 MHz ICSOUT signal is 8 MHZ Oscillator pins can be used as general I/O No external components required No loss of lock or loss of clock status bit Power consumption higher than FBI or FBE Next, let s discuss the various ICS modes that are available for use. FEI mode is the default ICS mode out of reset. In FEI mode, the FLL multiplier is fixed to 512. The internal reference is trimmable with a resolution of 0.2 percent. The ICSOUT signal frequency is equal to the DCO frequency divided by BDIV in ICS control register 2. The bus frequency is equal to the ICSOUT signal divided by 2. Therefore, the bus frequency in FEI mode is equal to DCO divided by two times the BDIV value. After reset, the internal reference frequency of approximately 32 khz multiplied by the fixed multiplier of 512, equals approximately 16 MHz, which is the Digitally Controlled Oscillator (DCO) frequency. The bus frequency divider (BDIV) is by default divide by 2, so the resulting ICSOUT signal is 8 MHZ. This means that the default bus frequency out of reset is approximately 4 MHz. When the ICS is in FEI mode, oscillator pins can be used as general I/O pins because no external connections are required. In FEI mode, there is no loss of lock or loss of clock status bit. Finally, FEI mode consumes more power than both FBI and FBE modes.

15 ICS Modes FEE clock mode: Multiplier fixed to x 512 External crystal, resonator, or clock: Low range: 32 to 38.4 khz High range: 1 to 5 MHz Must divide down to khz<=f REF <=39.06 khz using RDIV Bus frequency = DCO (2 x BDIV); DCO = 16 to 20 MHz No loss of lock or loss of clock status bit System clock with high accuracy (almost as accurate as the external source) Power consumption slightly higher or lower than FEI depending on external source range In FEE clock mode, the multiplier is also fixed at 512, but an external crystal, resonator, or clock source is required. The oscillator frequency must lie in a low range of 32 to 38.4 khz or a high range of 1 to 5 MHz, as selected by the RANGE bit in ICS control register 2. Before applying the fixed 512 multiplier when using an external reference frequency that falls within the high range, the Reference Divider, RDIV in ICS control register 1 must first be used to divide the reference down to a value between and khz. As in FEI mode, the bus frequency in FEE mode is equal to the DCO frequency divided by 2 times BDIV. The DCO falls between 16 and 20 MHz. Also, in FEE mode, there is no loss of lock or loss of clock status bit. FEE mode generates a highly accurate system clock; it is almost as accurate as the external source. Power consumption is slightly higher than that of FEI mode in high range, but slightly lower for low range external source frequencies.

16 ICS Modes FBI clock mode: Internal reference directly Trimmable with resolution of 0.2 percent Internal reference = to khz Bus frequency = internal reference (2 x BDIV) Oscillator pins can be used as general I/O No external components required Very accurate when trimmed Optional low power mode turns FLL off (FBILP) Low power consumption (less than FEI or FEE modes) The second ICS mode that uses the internal reference is FBI mode. This mode uses the internal reference directly, and allows trimming at a resolution of 0.2 percent. The internal reference falls between and khz. FBI mode does not use the DCO. Therefore, the bus frequency in this mode is equal to the internal reference divided by 2 times the BDIV value. As in FEI mode, oscillator pins can be used as general purpose I/O pins because no external components are required. The FBI mode reference is very accurate when trimmed. Although FBI mode does not use the FLL block, the FLL is still on. An optional low power mode (FBILP) can turn the FLL off. FBI mode consumes less power than both FEI and FEE modes.

17 ICS Modes FBE clock mode External crystal or resonator Low range: 32 khz to 38.4 khz High range: 1 MHz to 16 MHz External clock DCO to 20 MHz Bus frequency = external reference (2 x BDIV) Highest accuracy (as accurate as the external source) Optional low power mode turns FLL off (FBELP) Lowest power consumption The last ICS clock mode is FBE mode, which runs off of an external reference. When using an external crystal or resonator, the reference frequency must lie between 32 and 38.4 khz for a low range operation and between 1 MHz and 16 MHz for a high range operation, as selected by the RANGE bit in ICS control register 2. When using an external clock, the reference frequency may run up to 20 MHz. As in FBI mode, because the DCO is not used, the bus frequency in FBE mode is equal to the external reference divided by two times the BDIV value. This mode provides the highest accuracy of all ICS modes because it is as accurate as the external source. An optional low power mode (FBELP) turns the FLL off in the same way that FBILP turned the FLL off in FBI mode. This mode also consumes the lowest power of all ICS clock modes.

18 ICS Features ICS Features Low power or high gain oscillator options Software selectable BDIV Low power limits voltage swing on oscillator pins High gain drives oscillator pins to rail BDIV available in all ICS modes Divides bus clock by 1, 2, 4, or 8 Allows frequency changes without FLL losing lock Set to divide by 2 after reset Here are several additional features to take note of when using the ICS module. These include low power or high gain oscillator options, and the softwareselectable BDIV. Be sure to consult device-specific data sheets to guarantee proper operation of the module. You can access the device-specific data sheets by visiting the Web site shown here. The HGO bit in ICS control register 2 determines whether the ICS operates in low power or high gain mode. To minimize power consumption, low power mode will limit the voltage swing on the oscillator pins. On the other hand, high gain mode drives rail-to-rail voltage swings on the oscillator pins. The software-selectable BDIV is located in ICS control register 2, and is available in all ICS modes. It allows the clock source selected by the clock source select (CLKS) bits in ICS control register 1 to be divided down by 1, 2, 4, or 8. With the BDIV, frequency changes can occur without the FLL losing lock. The default value for the BDIV after reset is set to divide by 2. Note that in STOP mode, internal, external, or both references can be enabled.

19 STOP Effects on ICS Exit from Stop 1 or Stop 2 always uses the default FEI mode to start up quickly Exit from Stop 3 can use an external oscillator or the programmed internal clock generator FBI mode: Startup is immediate at trimmed frequency FEI mode: Startup is immediate at pre-stop frequency FEE mode: Startup is immediate at pre-stop frequency in Pen Loop mode until stabilization time and then switches to external reference FBE mode: Startup is delayed based on external reference stabilization time NOTE: In Stop 3, current is not affected by ICS mode before entering; it is only affected by or the service names references are the property of their respective enabled owners. Freescale in Semiconductor, STOP. Inc The ICS module behaves differently during STOP recovery depending on the STOP state prior to wakeup. Exit from Stop 1 and Stop 2 modes always uses the default FEI mode for quick startup. Exit from Stop 3 allows usage of either an external oscillator or the programmed internal clock generator. The selected clock generator can optionally continue to run, which enables faster startup. Stop 3 recovery occurs under different conditions, depending on the ICS mode in the pre-stop state. Here you can see a description of the conditions in each of the ICS modes. Note that current is not affected by the ICS mode before entering Stop 3, but it is affected by the references enabled during STOP.

20 Question Identify the ICS modes that will complete the sentence. Select the correct answers and then click Done. For the ICS module, two modes, and require no external components and run off of the microcontroller s internal clock. FBI FEE FEI FBE Consider this question concerning the ICS module. Correct. The ICS module includes four modes of operation: FBI mode, FEI mode, FBE mode, FEE mode. The FEI and FBI modes that require no external components and run off of the microcontroller s internal clock.

21 Question What are some of the features of the ICS modes? Match each mode on the left with its description on the right. Click Done when you are finished. A FEI A The default ICS mode out of reset. B FBI C This mode consumes the lowest power of all ICS clock modes. C FBE B This mode has an optional low power mode that can turn the FLL off. D FEE D This mode generates a highly accurate system clock and requires an external crystal, resonator, or clock source. Done Reset Show Solution Let s take a moment to review the ICS modes. Correct. The FEI mode is the default ICS mode out of reset. The FBI mode has an optional low power mode that can turn the FLL off. The FBE mode consumes the lowest power of all ICS clock modes. The FEE mode generates a highly accurate system clock and requires an external crystal, resonator, or clock source.

22 Course Summary ICG module: ICG clock modes: SCM FBE FEI FEE Additional and functional ICG features ICS module: ICS clock modes: FEI FEE FBI FBE Additional and functional ICS features This course provided you with a brief look at the S08 ICG and ICS modules. First, you examined a block diagram for the ICG module. Next, you learned about the features and functions of these modes. For example, all of these modes are software selectable, and the user software can switch between ICG modes at any time. You also explored how the ICG module behaves during STOP mode recovery, which depends on the STOP state prior to wakeup. Next, you examined a block diagram for the ICS module and learned about its important features. You learned about the different clock modes available in the ICS module. As in the ICG module, all of these modes are software selectable, and the user software can switch between ICS modes at any time. Finally, you focused on how the STOP mode recovery affects the ICS module. Now that you have completed this course, you should have a better understanding of the basic functionality of the ICG and ICS modules and be better prepared to select the best clock mode for your application.