A Robust Scheme for Distributed Control of Power Converters in DC Microgrids with Time-Varying Power Sharing

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1 A Robust Schee for Distributed Control of Power Converters in DC Microgrids with Tie-Varying Power Sharing Mayank Baranwal,a, Alireza Askarian,b, Srinivasa M. Salapaka,c and Murti V. Salapaka,d Abstract This paper addresses the proble of output voltage regulation for ultiple DC/DC converters connected to a icrogrid, and prescribes a schee for sharing power aong different sources. This architecture is structured in such a way that it adits quantifiable analysis of the closed-loop perforance of the network of converters; the analysis siplifies to studying closed-loop perforance of an equivalent single-converter syste. The proposed architecture allows for the proportion in which the sources provide power to vary with tie; thus overcoing liitations of our previous designs in []. Additionally, the proposed control fraework is suitable to both centralized and decentralized ipleentations, i.e., the sae control architecture can be eployed for voltage regulation irrespective of the availability of coon load-current or power easureent, without the need to odify controller paraeters. The perforance becoes quantifiably better with better counication of the deanded load to all the controllers at all the converters in the centralized case; however guarantees viability when such counication is absent. Case studies coprising of battery, PV and generic sources are presented and deonstrate the enhanced perforance of prescribed optial controllers for voltage regulation and power sharing. I. INTRODUCTION Utility grid is ost stressed during peak power deands resulting in significant increase in real-tie power prices and congestion in the local power distribution zone. Microgrids can help reduce the requireent for additional utility generation and thus iniize the deand on the utility grid by enabling integration of renewable energy sources such as solar and wind energy, distributed energy resources DERs, energy storage, and deand response. Microgrids are localized grid systes that are capable of operating in parallel with, or independently fro, the existing traditional grid []. Fig. shows a scheatic of a icrogrid with ultiple DC sources providing power for AC loads. Existing control architectures for traditional grids, which are designed for relatively large conventional sources power plants of predictable and dispatchable electric power, cannot adequately anage uncertain power sources such as solar or wind generations. Liited predictability with such resources Departent of Mechanical Science and Engineering, University of Illinois at Urbana-Chapaign, 680 IL, USA Departent of Electrical and Coputer Engineering, University of Minnesota, Minneapolis, MN, USA a baranwa@illinois.edu, b askaria@illinois.edu, c salapaka@illinois.edu, d urtis@un.edu The authors would like to acknowledge ARPA-E NODES progra for supporting this work. Fig. : A scheatic of a icrogrid. An array of DC sources provide power for AC loads. Power sources provide power at DC-link, their coon output bus, at a voltage that is regulated to a set-point. The control syste at the respective DC-DC converter that interfaces with a source is responsible for regulating the voltage at the DC-link. result in interittent power generation; oreover tievarying loads, practicability and econoics factors pose additional challenges in efficient operation of icrogrids. Thus it is required to develop efficient distributed control technologies for reliable operation of sart icrogrids [3]. In such sart grids, ultiple DC power sources connected in parallel, each interfaced with DC-DC converter, provide power at their coon output, the DClink, at a regulated voltage; this power can directly feed DC loads or be used by an inverter to interface with AC loads see Fig.. By appropriately controlling the switch duty-cycle of DC-DC converter at each power source, it becoes possible to anipulate electrical quantities such as the power output by the power source and the voltage at the DC-link. The ain goals of the control design is to regulate voltage at the DC-link and ensuring a prescribed sharing of power between different sources; for instance, econoic considerations can dictate that power provided by the sources should be in a certain proportion or according to a prescribed priority e.g. PV provides the axiu power it can to satisfy load deand, and the deficit is provided by battery. The ain challenges arise fro the uncertainties in the size and the schedules of loads, the coplexity of a coupled ulti-converter network, the uncertainties in the odel paraeters at each converter, and the adverse effects of interfacing DC power sources with AC loads, such as the 0 Hz ripple that has to be provided by the DC sources.

2 Probles pertaining to robust and optial control of converters have received recent attention. Conventional PID-based controllers often fail to address the proble of robustness and odeling uncertainties. In [4], a linear-atrix-inequality LMI based robust control design is presented for boost converters which deonstrates significant iproveents in voltage regulation over PID based control designs. In [5], [6], robust H -control fraework is eployed in the context of inverter systes. While the issue of current sharing is extensively studied [7], ost ethods assue a single power source. A systeatic control design that addresses all the challenges and objectives for the ulticonverter control is still lacking. The control architecture proposed in this paper addresses the following priary objectives - a voltage regulation at the DC-link with guaranteed robustness argins, b prescribed tie-varying power sharing in a network of parallel converters, c controlling the tradeoff between 0Hz ripple on the total current provided by the power sources and the ripple on the DC-link voltage. While these objectives are partially addressed in our prior work [] on the robust control of DC-DC converters, a ain drawback of the design proposed in [] is that the control fraework does not allow for tie-varying power sharing requireents. In this work, we propose a new architecture wherein the power requireents on each converter are iposed through external reference signals; this allows for tie-varying power sharing/priority prescriptions. This is achieved without sacrificing any advantages of the design in []. An iportant feature of the proposed architecture is that it exploits structural features of the paralleled ulti-converter syste, which results in a odular and yet coordinated control design. Accordingly at each converter, it eploys a nested outer-voltage innercurrent control structure, where all converters share the sae design for the outer-loop voltage controllers while the inner-loop current controllers are so chosen that the entire closed-loop ulti-converter syste can be reduced to an equivalent single-converter syste in ters of the transfer function fro the desired regulation setpoint V ref to the voltage at the DC-link V. An interesting aspect of the proposed ipleentation is that the sae control ipleentation works for both the centralized case, when the load power is known and counicated to all the controllers, and the decentralized case where the load is unknown. The architecture achieves better perforance in voltage regulation and power sharing when load power inforation is counicated, while it guarantees electrical viability with quantifiable bounds on deviations fro the targeted perforances in the decentralized case. II. MODELING OF CONVERTERS In this section, we describe the differential equations that govern the dynaics of DC-DC converters. These converters belong to a class of switched-ode Fig. : A scheatic of a Boost converter. The converters are assued to operate in continuous-conduction-ode CCM. power electronics, where a seiconductor based highfrequency switching echanis connected to a DC power source enables changing voltage and current characteristics at its output. The odels presented below depict dynaics for signals that are averaged over a switch cycle. Fig. shows a scheatic of a Boost converter. Boost converter regulates a voltage V at its output which is larger than the input voltage V g. The averaged dynaic odel of a Boost converter is given by L i L t = dtvt + V g, C Vt = dti L t i load t, where dt represents the duty-cycle or the proportion of ON duration at tie t. By defining d t := dt and D := V g /V ref, where Vref is the desired output voltage, can be rewritten as, L di Lt dt C dvt dt = V g d tvt, ũt:=v g ut = D + ˆ dt D i L t i load t. Note that ˆ dt = d t D is typically very sall, and therefore allows for a linear approxiation around the noinal duty-cycle, D = D. III. PROBLEM FORMULATION This paper addresses the following priary objectives siultaneously in context of Fig. - a Regulation of DC-link voltage V to a prescribed value V ref in presence of tie-varying loads/generation and paraetric uncertainties, b tie-varying current power sharing aong ultiple sources, that is, ensuring that current power outputs i k fro each converter respectively track a tie-varying signal i refk, and c 0Hz ripple current sharing between the output currents i k fro each converter and the capacitor current i C. The last objective is dealt in our prior work [] and is addressed by an appropriate design of inner-controller described in Sec. IV-A and V. In this paper, we priarily focus on achieving the first two objectives, while inheriting the properties of the inner-controller for ripple current sharing.

3 Fig. 3: Block diagra representation of the inner-outer control design. The regulated variables z, z, z 3 and z 4 correspond to weighted - a tracking error in DC-link voltage, b isatch between i ref and i load, c control effort û, and d output voltage tracking, respectively. IV. CONTROL FRAMEWORK FOR SINGLE CONVERTER In this section, we describe the inner-outer control design for a single Boost converter syste. This design for a single converter fors the basis for the analysis and design of control architecture for ultiple converters presented in Sec. V. While the design is easily extendable to include other converter types such as Buck and Buck-Boost, the discussion has been confined to Boost converters only for the sake of brevity. Note that in the proposed control architecture see Fig. 3, the inputs to outer feedback controller include i ref in addition to the typical V ref and the easured DC-link voltage V. The requireents on current sharing are iposed through this additional i ref signal explained in Sec. V by setting i ref to easured or counicated load current i load in the centralized case, and setting i ref to estiated or prespecified signals in the decentralized case. A. Design of the inner-loop controller The design for the inner-loop controller K c is inherited fro our previous work []. The ain objective for designing the inner-loop controller K c is to decide the trade-off between the 0Hz ripple on the capacitor current i C equivalently on the output voltage V and the inductor current i L of the converter. Accordingly, K c is designed such that the inner-shaped plant G c is given by ω s G + ζ ω 0 s + ω0 c s = s + ω s + ζ ω 0 s + ω0. 3 where ω 0 = π0rad/s and ω, ζ, ζ are design paraeters. The paraeter ω > ω 0 and it is used to ipleent a low-pass filter to attenuate undesirable frequency content in i L beyond ω. Thus, the bandwidth of the inner closed-loop plant is decided by the choice of ω. The ratio ζ /ζ can be appropriately designed to achieve a specified trade-off between 0Hz ripple on i C and i L, and therefore between V and i L. The readers are encouraged to refer to Sec. III in [] for further details on the inner-loop control design. B. Design of the outer-loop controller For a given choice of inner-controller K c, we present our analysis and design of controller in ters of transfer function block diagras shown in Fig. 3. In this figure, G c represents the inner shaped plant. The outer controllers are denoted by K v and K r, and are designed to regulate the output DC voltage V to the desired reference voltage V ref and the output current D i L to the reference current i ref, respectively. Note that fro, D i L is equal to i load at steady-state. The augentation of controller K r fors the basis for tie-varying power sharing and is explained in the next section. It should be rearked that the proposed design has a feature that if the load current easureent is available, i.e., i ref = i load, then the steady state DC output voltage is aintained at the reference voltage V ref. However in the absence of i load easureent, the outer controller K r regulates the output current D i L to i ref = i load resulting in an output voltage V = V ref. The isatch in voltage tracking is captured by a pre-specified drooplike coefficient η in a controlled anner, the notable difference here being the application of droop to the faster current loop when copared with the conventional droop-based design acting on the slower voltage loop. This feature is atheatically quantified in the following discussion on the proposed control design. The ain objective for the design of the controllers K v and K r is to ake the tracking errors sall and siultaneously attenuate easureent noise to achieve high resolution. This is achieved by posing a odelbased ulti-objective optiization proble, where the required objectives are described in ters of nors of the corresponding transfer functions, as described below. Note that the regulated variables z, z, z 3 and z 4 correspond to weighted - a tracking error in DC-link voltage, b isatch between i ref and i load, c control effort û, and d output voltage tracking, respectively. Fro Fig. 3, the transfer function fro exogenous inputs and auxiliary control input w = [V ref, i ref, i load, û] T to regulated output z = [z, z, z 3, z 4, e, e ] is given by z z z 3 z 4 e e } {{ } z = W 0 W G v D W G v G c ηw W ηw G v D + ηg v W G c W W 4 G v D W 4 G v G c 0 G v D G v G c η ηg v D + ηg v G c } {{ } T wz V ref i ref i load û. } {{ } w 4 The optiization proble is to find stabilizing controllers K outer = [K v, K r ] T such that the H -nor of the above transfer function fro w to z is iniized. Here the weights W, W, W 3 and W 4 are chosen to reflect the design specifications of robustness to paraetric uncertainties, tracking bandwidth, and saturation liits on the control signal. More specifically, the weight functions W jω and W jω are chosen to be large in frequency range [0, ω BW ] to ensure sall tracking errors e = V ref V and e = i ref + ηe D i L in this frequency range. The design of weight function W 3 jω entails ensuring that the control effort lies within saturation liits. The weight function W 4 is designed as a high-pass filter to ensure that the transfer function fro i load to V is sall at high frequencies to

4 provide itigation to easureent noise. Note that for the syste shown in Fig. 3, the voltage V at the DC-link is given by, V = G v iload + D G c K v e + K r e. 5 Using the fact that e = V ref V and e = i ref + ηe D G c K v e + K r e, the DC-link voltage in ters of exogenous quantities V ref, i ref and i load is given by [ D Vs = ] G c G v K v + ηk r + D G c K r + D G V ref s c G v K v + ηk r [ D + ] G c G v K r + D G c K r + D G i ref s i load s c G v K v + ηk r [ ] G v + D G c K r + D G i load s. 6 c G v K v + ηk r Let Ss, T Vref V and T iref V denote the closed-loop sensitivity transfer function and copleentary sensitivity transfer functions fro V ref to V and i ref to V, respectively. Then 6 can be rewritten as Vs = T Vref VV ref s + T iref V i ref s i load s G v Si load s. The DC gains of above closed-loop transfer functions are given by since G v = /sc has an infinite DC gain, K r j0 T Vref Vj0 =, T iref Vj0 = K v j0 + ηk r j0 G v Sj0 = D K v j0 + ηk r j0. and We now provide a sketch of the proposed design concept. Since K v and K r are chosen as high DC-gain controllers obtained by solving the H optiization proble, we have G v Sjω 0 at low-frequencies. Thus the effect of disturbance signal i load is insignificant at low frequencies. Siilarly T Vref Vjω has unity gain at low frequencies. Furtherore, if the load current i load easureent is available i.e. i ref = i load, then the Boost converter tracks the reference voltage with alost unity gain. However in the absence of i load easureent, the tracking error depends on the isatch between i ref and i load, i.e., the bound on the steady-state tracking error becoes proportional to K r j0 ultiplied by the isatch value K v j0 + ηk r j0 i ref j0 i load j0. By choosing appropriate controllers K v and K r i.e., T iref Vj0 <<, the tracking error can be ade sall. V. EXTENSION TO A SYSTEM OF PARALLEL CONVERTERS In this section we extend our control fraework for a single converter to a syste of DC-DC converters connected in parallel in the context of power sharing, keeping in ind the practicability and robustness to odeling and load uncertainties. In particular, we analyze the ulti-converter syste in Fig. 4 through an equivalent single-converter syste siilar to the syste shown in Fig. 3, where the ulti-converter syste inherits the perforance and robustness achieved by a design for the single-converter syste. Fig. 4: Many-converters syste with shaped inner plants G c. In the proposed ipleentation, we adopt the sae outer controller for different converters, i.e., K v = K v =.. = K v = K v and K r = K r =.. = K r = K r ; γ k represents the proportion of power deanded fro the k th source. Fig. 4 represents the proposed inner-outer control fraework for a syste of parallel connected converters. Note that the reference signal i ref + ηv ref V is prescaled by a tie-varying ultiplier γ k, 0 γ k. The choice of γ k dictates the power sharing requireents on the k th converter. In fact, we later show that the proposed ipleentation distributes the output power in the ratios γ : γ :.. : γ. After noting that the voltage-regulation and current reference tracking is coon to all the outer controllers, in our architecture, we ipose the sae design for outer-controllers for all the converters, i.e., K v = K v =.. = K v and K r = K r =.. = K r. This iposition enables significant reduction in the overall coplexity of the distributed control design for a parallel network of converters and power sources, thus ensuring the practicability of the proposed design which allows integration of power sources of different types and values. We design inner-controllers K ck such that the innershaped plants fro ũ k to i Lk are sae and given by, ω s G + ζ,no ω 0 s + ω0 c,no s = s + ω s + ζ,no ω 0 s + ω0, 7 where the ratio ζ,no /ζ,no deterines the tradeoff of 0Hz ripple between the total output current D i L = k= D k i L k and the capacitor current i C. Note that for given values of ζ,no, ζ,no and inductance L k, explicit design of K ck exists. Furtherore, we ipose K vk = K v and K rk = K r. Indeed, by our choice of inner and outer controllers, the transfer functions fro external references V ref, i ref and i load to the desired output V are identical for all converters. Hence the entire network of parallel converters can be analyzed in the context of an equivalent single converter syste. This iplies that K vk and K rk can be coputed by solving H -optiization proble as discussed in the previous section siilar to the single converter case. We ake these design specifications ore precise and bring out the equivalence of

5 the control design for the single and ultiple converter systes in the following theore. We say that the syste representation in Fig. 3 is equivalent to that in Fig. 4, when the transfer functions fro the reference voltage V ref, reference current i ref and load current i load to the DC-link voltage V in Fig. 3 are identical to the corresponding transfer functions in Fig. 4. Theore : Consider the single-converter syste in Fig. 3 with inner-shaped plant G c,no s as given in 7, outer controllers K v, K r, droop-coefficient η, and external references V ref, i load, i ref ; and the ulti-converter syste described in Figs. 4a and 4b with inner-shaped plants G ck = G c,no s and outer controllers K vk = K v; K rk = K r, droop-coefficient η, and sae external references V ref, i load and reference current i ref prescaled by tie-varying scalars γ k > 0 for k.. [Syste Equivalence]: If k= γ k =, then the syste representation in Fig. 3 is equivalent to the syste representation in Fig. 4.. [Power Sharing]: For any two converters k and l, k, l {,..., } in a ulti-converter syste shown in Fig. 4, the difference in the corresponding steady-state scaled output currents is given by D k i L k j0 γ k D l i L l j0 γ l η T j0 + γ k γ l T j0 e j0, D G c,no K r 8 D G c,no K v +D G c,no K r. where, T := +D G c,no K r and T := Furtherore, the steady-state tracking error e V ref V in DC-link voltage is upper bounded by, Centralized case: i ref = i load e j0 Decentralized case: i ref = i load D K v j0 + ηk r j0 i refj0 K r j0 e j0 D K v j0 + ηk r j0 i refj0 + D K r j0 + D K v j0 + ηk r j0 i loadj0 Reark : If the steady-state tracking error in DC-link voltage is zero, i.e., e j0 = 0, then 8 reduces to the following constraint: D k i L k j0 D l i L l j0 = γ k γ l. i.e., the closed-loop ulti-converter syste achieves output power sharing given by D i L j0 :... : D i L j0 = γ :... : γ l. Reark : For the decentralized ipleentation, it is required that each converter can easure its own inductor current i Lk and DC-link voltage V only. Proof: See Appendix. VI. CASE STUDIES: SIMULATIONS AND DISCUSSIONS In this section, we report soe siulation studies that cover different aspects of the proposed distributed control design. All siulations are perfored in MAT- LAB/Siulink using SiPower/SiElectronics library. For siulations, we consider a parallel network of three boost converters powered by a Li-ion battery and two generic sources noinal voltages 5V, respectively. The effectiveness of the proposed control design is well illustrated by considering a challenging practical scenario with unknown fast tie-varying load, large uncertainties in inductance and capacitance values, sensor noises and variation in input source voltages. Specifically, we consider the following siulation paraeters: Battery State-Of-Charge: 0% 35V Generic Sources: 5V and 30V Inductance: L, L, L 3 =.096,.,.4H Capacitance: C = 400µF Loading Conditions: 5kW ± kw@hz Power Sharing Requireents: 0.33 : 0.33 : 0.33, t < s 0.5 : 0. : 0.3, s t 9.5s Desired Output Voltage: V ref = 50V To illustrate the robustness of the proposed approach, the noinal or equivalent single converter inductance, capacitance and steady-state copleentary duty-cycle are chosen as L = 0.H, C = 500µF and D = V g /V ref = 0.5. The design paraeters for the inner-controller K c are: Daping factors ζ = 0.7, ζ =., and bandwidth ω = π300rad/s. The outer controllers K v and K r are obtained by solving the stacked H optiization proble see Eq. 4 [8] with the weighting functions: 0.467s s W = W s = s s W 3 = 0.04 W 4 = s Inclusion and characterization of PV odule: Photovoltaics are technically treated as current sources. In a icrogrid setup, a PV odule is interfaced with the DC-link through a Boost converter and is controlled using the axiu power point tracking MPPT algorith. The output current of PV i PV is directly proportional to the tie-varying irradiance and is included in our proposed forulation by regarding i PV as part of the disturbance signal, i.e., the net disturbance current is odeled as i load i PV. In this siulation study, we squeeze worth 8 hours of insolation data into a total duration of 9.5s aounting to rapidly varying irradiance and hence the disturbance current i PV. Results: The controllers derived for the noinal single converter syste are then extended for a parallel ulti-converter design as described in Sec. V. The initial DC-link voltage is considered at 0V. Fig. 5 shows the voltage regulation at the DC-link to the reference V ref = 50V for the centralized i load easureent available and decentralized ipleentations. Note

6 Fig. 5: DC-link voltage regulation and power sharing for centralized and decentralized scenarios. that the DC-link load changes by 4kW every second 3kW to 7kW, and 7kW to 3kW. The reference current is considered as i ref = 5kW/50V = 0A. While in the centralized case, the voltage is aintained at V ref = 50V with sall periodic spikes attributed to sudden load changes, the decentralized ipleentation results in controlled voltage droop of 0V peak-topeak around the desired DC-link voltage. In order to deonstrate tie-varying power sharing perforance, the scaled output currents D i L /γ are plotted in Fig. 5. Overlapping values of scaled currents depict excellent sharing perforance; oreover, the control design achieves step-change in power sharing sealessly at t = s. APPENDIX Sketch of Proof of Theore : Syste Equivalence Proof: The equivalence is a direct consequence of cleverly chosen architecture. Note that for the single converter syste in Fig. 3 with G c s = G c,no s, the error signal e input to controller K r is given by e = i ref + η D G c,no e D G c,no K r e. 9 For the ulti-converter syste in Fig. 4, we have e k = V ref V := e. Let us denote the total error in current isatch k= ek by e. Therefore, fro Fig. 4, e k k= e e k = γ k [i ref + ηe ] D G c,no K ve + K r e k = γ k [i ref + ηe ] D G c,no K v e K r k= k= e k e Using the fact that k= γ k =, the above equation reduces to 9. Siilarly, the expression for tracking error in voltage V ref V is identical for the single and ultiple converters case. Moreover for the ulticonverter syste, the output voltage at the DC-link is given by V = G v i load + D G c,no K v e + K r e. Since the expressions for e and e are identical for the single and ultiple converters case and are written in ters of the exogenous variables V ref, i ref, i load, the corresponding transfer functions fro the exogenous variables to the DC-link voltage V are also identical, and hence establishes the required equivalence.. Sketch of Proof of Theore : Power Sharing Proof: Fro 0, the error in current reference for the k th -converter is given by e k = γ k + D G c,no K r i ref + G c,no K v + D G e. 0 c,no K r γk η D Fro Fig. 4, the output current i k = D k i L k of the k th converter is given by [ ] i k = D G c,no K ve + K r e k. Thus fro 0 and, we obtain [ i k = D γ G k K r c,no +D G i c,no K r ref + K v+ηγ k K r +D G e c,no K ]. r Therefore, we have i k j0 i lj0 γ k γ η T j0 + l γ k γ T j0 e j0 l The expressions for the bounds on the tracking error for the two scenarios is directly obtained fro 6 and the syste equivalence described earlier. REFERENCES [] M. Baranwal, S. M. Salapaka, and M. V. Salapaka, Robust decentralized voltage control of DC-DC converters with applications to power sharing and ripple sharing, in 06 Aerican Control Conference ACC. IEEE, 06, pp [] N. Hatziargyriou, H. Asano, R. Iravani, and C. Marnay, Microgrids, Power and Energy Magazine, IEEE, vol. 5, no. 4, pp , 007. [3] J. P. Lopes, C. Moreira, and A. Madureira, Defining control strategies for icrogrids islanded operation, IEEE Transactions on power systes, vol., no., pp , 006. [4] C. Olalla, R. Leyva, A. El Aroudi, P. Garces, and I. Queinnec, LMI robust control design for boost pw converters, IET Power Electronics, vol. 3, no., pp , 00. [5] T. Hornik and Q.-C. Zhong, A current-control strategy for voltage-source inverters in icrogrids based on and repetitive control, Power Electronics, IEEE Transactions on, vol. 6, no. 3, pp , 0. [6] S. Salapaka, B. Johnson, B. Lundstro, S. Ki, S. Collyer, and M. Salapaka, Viability and analysis of ipleenting only voltage-power droop for parallel inverter systes, in Decision and Control CDC, 04 IEEE 53rd Annual Conference on. IEEE, 04, pp [7] Y. Panov, J. Rajagopalan, and F. C. Lee, Analysis and design of N paralleled DC-DC converters with aster-slave current-sharing control, in Applied Power Electronics Conference and Exposition, 997. APEC 97 Conference Proceedings 997., Twelfth Annual, vol.. IEEE, 997, pp [8] S. Skogestad and I. Postlethwaite, Multivariable feedback control: analysis and design. Wiley New York, 007, vol..