Revision. 007 PGA26E19BA. Product Standards PGA26E19BA. Established: Revised: Page 1 of 11

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1 Revision. 7 Product Standards Established: Revised: Page of

2 Revision. 7 Type Application Structure GaN-Tr For power switching N-channel enhancement mode FET Equivalent Circuit Figure Out Line DFN 8X8 Marking PGA26E9 A. ABSOLUTE MAXIMUM RATINGS ( Tj = 25 O C, unless otherwise specified ) Values No. Item Symbol Min. Typ. Max. Unit Note Drain-source voltage ( DC ) * VDSS V 2 Drain-source voltage ( pulse ) *2 VDSP V 3 Gate-source voltage ( DC ) * VGSS V *VGSS+ is given by IG ratings *See application note 4 Gate current ( DC ) * IG ma *See application note 5 Gate current ( pulse ) *3,4 IGP A *See application note 6 Electric gate charge ( pulse ) QGP nc 7 Drain current ( DC ) ( Tc = 25 O C ) * *f=2khz ID A Figure 4 *See application note 8 9 Drain reverse current ( DC ) ( Tc = 25 O C ) * Drain current ( pulse )*5 ( Tc = 25 O C )* Drain reverse current ( pulse )*5 ( Tc = 25 O C )* IDR A ID pulse A Figure 4 IDR pulse A Power dissipation ( Tc = 25 O C ) PD W Figure 2 2 Junction temperature Tj O C 3 Storage temperature Tstg O C 4 Drain-source voltage slope dv/dt V/ns [Special instructions] * : Please use this product to meet a condition of Tj within 5 O C. *2 : Spike duty cycle D <., spike duration < us, total spike time < hour. *3 : IGP is defined as (Vcc - Vplateau) / Rgon, as shown in Figure A. Vplateau is the voltage between Gate and Source. *4 : Please use this product to meet both a maximum gate current and a maximum gate pulse charge of IGP(.6A) and Q(2nC) respectively, as shown in Figure H. *5 : Pulse width limited by Tjmax. Established: Revised: Page 2 of

3 Revision. 7 B. ELECTRICAL CHARACTERISTICS ( Tj = 25 O C, unless otherwise specified ) No. Item Symbol Measurement Condition Min. Typ. Max. Unit Drain cut-off current IDSS VDS=6 V, VGS= V, Tj=25 o C μa VDS=6 V, VGS= V, Tj=5 o C μa 2 Gate-source leakage current IGSS 3 Gate forward voltage VGSF 4 Gate threshold voltage VTH VGS=-3 V VDS= V IGS= ma open drain VDS= V IDS= ma μa V V 5 Drain-source on-state resistance RDS(on) IGS= ma, IDS=5 A, Tj=25 o C mω IGS= ma, IDS=5 A, Tj=5 o C mω 6 Gate resistance RG 7 Transfer conductance gfs f=mhz open drain VDS=8 V IDS=5 A Ω S 8 Input capacitance Ciss pf 9 Output capacitance Coss VDS=4 V VGS= V pf f= MHz Reverse transfer capacitance Crss pf Turn-on delay time td(on) ns 2 Rise time tr VDD=4 V IDS=5 A (Figure A, Figure B) ns 3 Turn-off delay time td(off) Vcc=2 V Rgon=5 Ω, Rgoff=4.7 Ω, ns Rig=5 Ω, Cs=68 pf 4 Fall time tf ns 5 6 Effective output capacitance ( energy related ) Effective output capacitance ( time related ) Co(er) pf VDS=-48 V Co(tr) pf Established: Revised: Page 3 of

4 Revision. 7 C. GATE CHARGE CHARACTERISTICS ( Tj = 25 O C, unless otherwise specified ) No. Item Symbol Measurement Condition Min. Typ. Max. Unit Gate charge Qg nc 2 Gate-source charge Qgs VDD=4 V IDS=5 A (Figure C, Figure D) nc 3 Gate-drain charge Qgd -. - nc 4 Gate plateau voltage V plateau VDD=4 V IDS=5 A V D. REVERSE CONDUCTING CHARACTERISTICS ( Tj = 25 O C, unless otherwise specified ) No. Item Symbol Measurement Condition Min. Typ. Max. Unit Source-drain forward voltage VSD VGS= V ISD=5 A V 2 Reverse recovery charge Qrr - - nc 3 Reverse recovery time trr VDS=4 V - - ns 4 Peak reverse recovery current Irrm ISD=5 A - - A 5 Output charge Qoss nc E. THERMAL RESISTANCE CHARACTERISTICS No. Item Symbol Measurement Condition Min. Typ. Max. Unit 2 Thermal resistance ( junction to case ) Thermal resistance ( junction to ambient ) * Rth(j-c) Rth(j-a) o C/W o C/W 3 Reflow soldering temperature Tsold reflow MSL o C [Notes] * : Device mounted on four layers epoxy PCB (6.45 cm 2 copper area and 7 m thickness). Established: Revised: Page 4 of

5 Drain-source current IDS [A] Power [W] Rth(j-c) [ o C/W] Revision. 7 Equivalent circuit / Electrical characteristics Drain 9 Gate Top View Bottom View Source Source2,2.3,4 :Drain 5,6,9 :Source2 7 8 :Source :Gate Notice: Please connect Source pin to gate driver. Figure : Pin layout / Equivalent circuit 8 D = 5% 6 D = 2% D = % 4. D = 2% 2 Single pulse Temperature Tc [ o C] Figure 2: Max. power dissipation Time [s] Figure Figure 3: Transient 3 : Transient thermal thermal impedance impedance ID MAX(pulse). ID MAX(DC) μs* us* ms* DC * Single pulse.. Figure 4: Safe operating area Tc = 25 O C Established: Revised: Page 5 of

6 Drain-source on-state resistance RDSon[Ω] Gate-source current IGS [ma] Drain-source on-state resistance RDSon [Ω] Gate-source current IGS [A] Drain-source current IDS [A] Drain-source current IDS [A] Revision Vg=4V 3 2 Vg=3V 2 Vg=4V Vg=2V Vg=3V Vg=2V Vg=V Vg=V Figure.5:Output characteristics Tc=25 O C Figure.6:Output characteristics Tc=25 O C.5. Igs=mA, Ids = 5A open drain Tj = 25 o C.2.4 Tj = 25 o C Temperature Tj [ o C] Figure 7:Drain-source on-state resistance(rds(on)-tj).6 Ids = 5A Tj = 25 o C.2. Tj = 25 o C..... Gate-source current IGS [A] Figure 9:Drain-source on-state resistance(rds(on)-igs) Gate-source voltage VGS [V] Figure 8:Gate characteristics Gate-source voltage VGS [V] open drain Tj = 25 o C Tj = 25 o C Figure.:Gate characteristics Established: Revised: Page 6 of

7 Gate-source voltage VGS [V] Capacitance [pf] Drain-source current IDS [A] Drain-source current IDS [A] Drain-source on-state resistance RDSon[Ω] Drain-sourc current IDS [A] Revision Ids = 5A 3 Vds = 8V.3 Tj = 25 o C 2 Tc = 25 o C.2. Tj = 25 o C Tc = 25 o C Gate-source voltage VGS [V] Figure.:Drain-source on-state resistance(rds(on)-vgs) Gate-source voltage VGS [V] Figure 2:Transfer characteristics Vgs V -V -2V -3V -4V -5V Vgs V -V -2V -3V -4V -5V Figure.3:Reverse channel characteristics (Tc=25 ) Figure.4:Reverse channel characteristics (Tc=25 ) Qg Qgs Qgd Vgs = V f = MHz Ciss Coss 2 Crss Input gate charge [nc] Figure 5:Gate charge characteristics Figure 6:Capacitance characteristics Established: Revised: Page 7 of

8 Threshold voltage VTH [V] Drain-source current IDS [ma] Eoss [μj] Qoss [nc] Revision Figure 7:Output capacitance stored energy Figure 8:Output charge 2.5 Ids=mA 8 Vgs = V Temperature Tj [ o C] Figure.9:Threshold voltage (VTH-Tj) Figure.2:Drain-Source leakage current (Tc=25 ) Established: Revised: Page 8 of

9 Revision. 7 Vcc VGS % 9% Rig L VDS 9% 9% Rgon Rgoff Cs DUT VDD td (on) tr ton % % td (off) toff tf Figure A : Switching time measurement IDS IDS VGS L VGS IG(const.) Rig RL Figure B : Switching wave form VDS VG, VD VDS VGS Qgs Qgd VG DUT DUT VDD VDD Vplateau VD Charge Figure C :: Gate charge measurement Figure D : Gate charge wave form VGS IDS VDS Ipeak = VDD / L x ton VDS Rig L DUT VDD Clamp circuit VDD Figure E : Reverse bias safe operating area dv/dt measurement circuit Figure F : Reverse bias safe operating area dv/dt wave form IG DUT ISD L ISD IGP trr Irrm % Rig VDD Electrical charge Q Qrr Figure G : di/dt measurement circuit Irrm Figure H : IGP di/dtwave form Time Established: Revised: Page 9 of

10 Revision. 7 [Precautions for Use] ) The product has risks for break-down or burst or giving off smoke in following conditions. Avoid the following use. Fuse should be added at the input side or connect zener diode between Gate pin and GND, etc as a countermeasure to pass regulatory Safety Standard. Concrete countermeasure could be provided individually. However, customer should make the final judgment. () Reverse the Drain pin and gate pin connection to the power supply board. (2) Drain pin short to Source pin and Source2 pin. (3) Drain pin short to Gate pin. (4) Gate pin open. 2) This product is under development and is subject to change without notice standards. Established: Revised: Page of

11 A A2 L E3 E2 E E Revision. 7 Outline D Unit: mm D A D2 b e SYMBOL DIMENSION MIN NOM MAX A A..2.5 A b.9.. D D D E E.9.. E E e 2. B.S.C. L *Please note that technical specifications are subject to change without notice. Established: Revised: Page of

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Revision. 007 PGA26E19BA. Product Standards PGA26E19BA. Established: Revised: Page 1 of 11

Revision. 007 PGA26E19BA. Product Standards PGA26E19BA. Established: Revised: Page 1 of 11 Revision. 7 Product Standards Established: 24-9-25 Revised: 27--24 Page of Revision. 7 Type Application Structure GaN-Tr For power switching N-channel enhancement mode FET Equivalent Circuit Figure Out

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