Multi-Channel CMOS Front-End IC for Physiological Signal Acquisition 生理信号采集的多通道 CMOS 模拟前端集成电路设计 张金勇王磊于力

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1 Vol 3 No9 / Sep 29 CMOS Front-End IC for Physiological Signal Acquisition 生理信号采集的多通道 CMOS 模拟前端集成电路设计 张金勇王磊于力 ABSTRACT A compacted and low-offset multi-channel CMOS front-end IC for physiological signal acquisitions is presented in this paper The proposed mixed signal IC includes low-offset gain programmable instrumentation amplifiers, high sensitive current-to-voltage converters, voltage/current reference and analog-to-digital converter (ADC) To make the IC adaptive to different physiological signals, the gain of the IA is configurable The ASIC was fabricated using SMIC 18-μm CMOS 1P6M technology Experiment results indicated that the input offset voltage was less than 97 μv and the CMRR was more than 1 db Operating in 8-bit mode, the ADC exhibited -1/+14 LSB DNL and -2/+2 LSB INL, respectively Power dissipations of each analogue channel and the ADC were approximately 387 μw and 74 μw under a 18 V single supply voltage, respectively It is suitable for a wide range of high precision biomedical applications KEYWORDS Biomedical circuits and systems; analog front-end; multi-channel probe; low-offset; biomedical signal acquisition 摘要本本文提出并设计了一款基于生理信号采集的低失调全集成多通道模拟前端集成电路 (IC) 该混合信号集成电路包含增益可调仪表运算放大器 高灵敏度电流 - 电压转换器 基准源以及 8 位逐次逼近式模数转换器 () 为适应不同种生理信号的采集, 该集成电路具有可配置特点 整个芯片采用 SMIC 混合信号 18-μm CMOS 1P6M 工艺制作, 核心电路的芯片面积为 136 mm 2 芯片测试结果显示: 该芯片在 18V 单电源供电电压下输入失调电压小于 97μV, 可调增益范围为 3dB 至 7dB, 其中 ADC 的微分非线性 (DNL) 和积分非线性 (INL) 分别为 -1/+14 LSB -2/+2 LSB 增益可调仪表运算放大器以及 ADC 工作在采样率 25kS/s 的功耗分别是 387μW 和 74μW 该模拟前端集成电路可以适用于较低幅度 低频率生物医学信号的采集 关键词生物医学电路与系统 ; 模拟前端 ; 多通道 ; 生理信号采集 1 Introduction In recent years, healthcare technologies are increasingly important and have received extensive research interests [1, 2] Since most physiological signals exhibit relative weak signal strength and low frequency (as listed in TABLE I [3, 4] ), the front-end IC design is fundamentally crucial To accommodate different physiological signals and reproduce the signal in the digital domain, a multi-channel front-end IC with lowoffset gain programmable instrumentation amplifier () and ADC should be elaborated In addition, a high sensitive current-to-voltage converter (I-V converter) is desired for accommodating current-mode signal, such as the current output from a photodiode used for photoplethymograph (PPG) measurements This work was sponsored by Chinese Academy of Sciences the 1 Talent People Program 62 Some biomedical front-end IC designs have been reported in [5-8] However, some of them did not include an ADC; some of them did not have adjustable gain or multi-input-channel In addition, a few attempts have been made for current source signal acquisitions Meanwhile, the acquisition system should be able to Table I Properties of several physiological signals Physiological Signals Measurement Range Frequency Range EEG 25-3 μv DC-15 Hz ERG 5-9 μv DC-5 Hz EGG 1-1 μv DC-1 Hz ECG 5-4 mv 1-25 Hz EMG 1-5 mv DC-5 Hz PPG 5-1 na 5-4 Hz

2 provide enough CMRR and low-offset performance In this paper, we proposed a multi-channel configurable physiological signal acquisition front-end IC with lowoffset voltage, where a high sensitive I-V converter and an 8-bit successive-approximation register (SAR) type ADC were integrated and the gain of the system is configurable This initial version of the system was realized in a SMIC mixed-signal 18-μm CMOS 1P6M technology 2 System Architecture The architecture of the implemented multi-channel CMOS front-end IC is shown in Fig 1 It includes s, I-V converters, a multiplexer (MUX), voltage/ current reference, and a Note that the input signal is DC-coupled directly from the skin-electrodes On the other hand, the DC-coupling of signal brings extra offset introduced by electrodes, which has to be accommodated by the input stage of the Low offset and high CMRR design is the main concern that will be addressed in this paper Physiological The offset performance of the IA fundamentally Signals determines the overall system performance Low-offset operational amplifier was designed to minimize the offset voltage The gain of the IA was configurable and I-V converters were exploited for current source signals A multiplexer, time multiplexed the output of each channel 生理信号采集的多通道 CMOS 模拟前端集成电路设计 and a resolution of 8-bit was integrated to digitize the amplified signals from channels at the appropriate sampling rate Finally, a novel high precision current/ voltage reference was presented in this design A bias generator and a built-in digital control circuit were exploited to generate the bias currents and gain select signals for the front-end IC 3 Circuit Implementation A Low-offset Operational Amplifier Fig 2 shows the schematic of the low-offset operational amplifier used in the A continuous-time asymmetrical differential input structure with commonmode feedback (CMFB) circuit was used to minimize the offset of the amplifier [9] As shown in Fig 2, the circuit of low-offset amplifier is divided into four parts: input stage, CMFB stage, biasing stage and output stage In input stage, the input MOS transistor pairs were designed as asymmetrical differential structure Besides, the input transistors and active load transistors are carefully designed to obtain good matching characteristic In CMFB stage, Frequency a high gain OPA structure was adopted Range to amplify the Range difference between input and output common-mode level This is a negative feedback network By adjusting the current sink of the input stage, the VIN and VOUT common-mode level could be maintained in same level In output stage, the class-ab structure was designed to improve the power efficiency Measurement EEG 25-3 μv DC-15 Hz ERG 5-9 μv DC-5 Hz EGG 1-1 μv DC-1 Hz ECG 5-4 mv 1-25 Hz EMG 1-5 mv DC-5 Hz PPG 5-1 na 5-4 Hz Figure1 Multi-channel CMOS front-end IC architecture Figure2Circuit schematic of the low-offset operational amplifier 63 Figure3Circuit schematic of the I-V converter DAC Output Successive- Approximation Register (SAR)

3 and driving capability Finally, a careful layout was planned to reduce process-related deviations [1] B I-V Converter I-V converter plays a vital role at the current input signal acquisition systems Fig3 shows the circuit of the proposed I-V converter that consists of the converter stage, the control stage and the biasing stage The output impendence of the MOS transistors to perform current conversions technology was used in this circuit [11] But one potential problem in using such an approach was the biasing of the high-gain output nodes, which was solved by using a negative feedback circuit with a control stage C Gain Programmable Instrumentation Amplifier An IA is a crucial component for high performance physiological signal acquisition systems To solve the problems in resistors feedback network matching of a conventional IA [12], we adopted a novel IA circuit structure with current mirror [13] The consists of low-offset operational amplifiers, current mirrors and a resistor array with the built-in digital interface The gain of it is digitally configurable The block diagram of the is shown in Fig 2 As illustrated in Fig 2, Vin+ and Vin- are physiological signals sensed from human body The differential gain of the was given by: A 2[( Vin ) ( Vin )] R R (1) v a s By digitally selecting the input of the decoder to connect the resistor array via the CMOS control switches, the is capable of providing programmable voltage gains when different Ra values were set Figure4 Block diagram of the D MUX/ A MUX and a resolution of 8-bit are usually presented when they used after the analogue signal conditioning The block diagram is shown in Fig5 (a) The consists of a sample-and-hold (), an internal D/A converter (DAC), a comparator and a SAR 64 Vol 3 No9 / Sep 29 logic block The binary-weighted R-2R array is depicted in Fig5 (b) It used a repeating cascaded structure of resistor values R and 2R This improved the precision due to the relative ease of producing equal valued matched resistors Converter Start EOC, DRDY, or BUSY Timing (a) (b) DAC Comparator Output Figure5(a) Block diagram of ADC and (b) binaryweighted R-2R array E Reference/Bias Generator A novel compensation scheme for power and temperature dependency of voltage and current reference were designed The basic principle is that two outputs with the same dependency on supply and temperature were subtracted to obtain the compensation output [14] Bias voltages and bias currents were generated from the voltage/current reference 4 Measurement Results Successive- Approximation Register (SAR) Control Logic The proposed multi-channel CMOS front-end IC was fabricated using SMIC 18-μm CMOS 1P6M technology Fig 6 shows the microphotograph of the chip, where the core circuit occupies about 136 mm 2 silicon area (excluding the Pads and ESD protection circuits) The low offset amplifier drews only 193 μa current from a single 18 V supply Fig 7 shows the measured following characteristic of the amplifier connected as a unit-gain buffer The measured results showed good following characteristic between input and output signal Fig 8 displays the measured input offset voltage The mean input offset was 75 μv whereas the maximum deviation of the offset was 963 μv Measured frequency response of the is shown in Fig 9 It is shown that the gain was configurable from Converter Start EOC, DRDY, or BUSY T

4 db to 7 db Fig1 shows the measured waveform of one channel output, where the analog input was a voltage signal with amplitude about 2 mvpp The signal was amplified by 36 db 2 m 生理信号采集的多通道 8 CMOS 模拟前端集成电路设计 DNL was within -1/+14 LSB and the INL was within -2/+2 LSB common mode voltage/v MUX/8-bit SARADC Low-offset OPA Buffer CUR Bandgap1 REF Bandgap2 IVC_IA 22 m Figure1 Measured waveform of the output K m m e K 22 m 22 m A Pads 2 + ESD mprote 12 MUX/8-bit SARADC 1 Low-offset OPA Buffer 8 CUR Bandgap1 IVC_IA REF Bandgap OTHER 2 WORK common mode voltage/v t common mode voltage/v Figure8 Measured input common offset voltage mode voltage/v VS input common mode voltage Figure6 Microphotograph of the CMOS front-end IC 13 Figure 7 The measured following characteristic of the amplifier: (a) Pads input 8 + ESD sinwave protection 6 of circuits 2mVpp 7 8 at 91 1Hz; 12 (b) input 1 rampwave 7 of common -18V mode voltage/v 12 Figure9 Measured frequency response of the The ADC operated up to 25 ks/s and consumed μw (excluding S/H circuit) from a 18 V supply The 8 1 measured differential nonlinearity (DNL) and integral nonlinearity (INL) of the ADC are shown in Fig 11 The m Figure11 Measured DNL and INL of the Figure12 Measurement supply voltage dependences of the voltage/current reference at room temperature Finally, the measured results of supply voltage dependences of the voltage and current reference are shown in Fig 12 The current reference offered 148 μa output current The line regulation of the current reference was about 57%/V and the relative variation of the voltage reference was 21% respectively, when supply voltage was varied 8 V to 3 V Table II gives a summary of the measured performance of our design The proposed system has selectable system gain and supports multi-channel input It offered a good solution of physiological signal acquisitions However, the input range of the ADC is limited, and the power consumption is relatively large, so our future work will focus on improving the linearity and reducing the power dissipation of the ADC In addition, lower offset design is also the main concern in our future work 5 Conclusions A CMOS multi-channel front-end IC with low input offset and reasonable power dissipation has demonstrated 1 D/V

5 including IA and a In particular, I-V converters are designed for current source signals and gain of IA is digitally controllable, leading to an adaptive interface capable of different physiological signal applications The system offered more than 1 db CMRR and less than 97 μv input offset, one channel consumes only 387 μw from a single 18 V supply The 8-bit exhibited -1/+14 LSB DNL, -2/+2 LSB INL The proposed CMOS front-end IC was fabricated in SMIC mixed-signal 18-μm CMOS technology and the core area measured 136 mm 2 Table II Measured performance of the front-end IC BLOCK PARAMETER VALUE SAR ADC Supply Voltage (Typical) CMRR Gain Selection Offset Voltage 18 V >1 db 3~7 db <97 μv THD (@2 mvpp input sinwave) <61 % Power Dissipation 387 μw Die area μm 2 Supply Voltage Resolution Sampling Rate Range DNL/INL 18 V 8-bit 1~5 ksps 16~13V -1~+14LSB/ LSB Gain Error <1% Power Dissipation (measured excluding the S/H circuit) Figure of Merit 74 khz 112 pj/conv Die area 1 2 μm 2 REFERENCES [1] Qiang Li, et al, A 1-V 36-pW low-noise adaptive interface IC for portable biomedical applications, 33rd European Solid State Circuits Conference, Sept 27, pp [2] C J Yen, et al, Micro-Power Low-Offset Instrumentation Amplifier IC Design for Biomedical System Applications, IEEE Trans Circuits Syst-I: Regular Papers, vol 51, no 4, April 24, pp [3] J G Webster, Medical Instrumentation: Application and Design, 3rd ed New York: Wiley, 1998 [4] J G Webster, Design of Pulse Oximeters, Institute of Physics, London 23, pp [5] R F Yazicioglu, etal, A 6μW 6nV/ Hz readout front-end for portable biopotential acquisition systems, IEEE Int Solid-State Circuits Conf, San Francisco, CA, Feb 5 9, 26, pp [6] K A Ng and P K Chan, A CMOS analog front-end IC for portable EEG/ECG monitoring applications, IEEE Trans Circuits Syst-I: Regular Papers, vol 52, no 11, Nov 25, pp [7] R F Yazicioglu, etal, Low-power low-noise 8-channel EEG front-end ASIC for ambulatory acquisition systems, European Solid-State Circuits Conf, Montreux, Switzerland, Sep 18 22, 26, pp Vol 3 No9 / Sep 29 [8] Maryam Shojaei-Baghini, etal, A low-power and compact analog CMOS processing chip for portable ecg recorders, IEEE Asian Solid-State Circuits Conf, Hsinchu, Taiwan, Nov 1 3, 25, pp [9] Kyu-Tae Lim, Seong-Joong Kim, Oh-Kyong Kwon, The OPamplifier with offset cancellation circuit, 23 IEEE Conference on Electron Devices and Solid-StateCircuits, Dec 23, pp [1] Christopher Saint and Judy Saint, IC Mask Design: Essential Layout Techniques McGraw-Hill Professional, 22 [11] CWang and JWang, Design of Linear Transimpedance Amplifiers, the 4th International Conference on ASIC, Oct 21, pp [12] HC Chow, J Y Wang, High CMRR instrumentation amplifier for biomedical applications, the 9th International Symposium on Signal Processing and Its Applications, Feb 27, pp 1-4 [13] A Harb and M Sawan, New low-power low-voltage high- CMRR CMOS instrumentation amplifier, IEEE International Symposium on Circuits and Systems, Volume 6, 3 May-2 June 1999, pp 97 1 [14] C Yoo, J Park, CMOS current reference with supply and temperature compensation, Electronics Letters, Volume 43, Issue 25, Dec 6 27, pp Author Introduction Jinyong Zhang: He received the BE degree in electrical engineering from the Huazhong University of Science and Technology, Wuhan, 27 He is currently pursuing the ME degree in microelectronics from the South China University of Technology, Guangzhou Since 28, he has been a visiting student in the medical chip design lab, SIAT, CAS His research interests include low-power and high-performance circuit and CMOS analog interface for biomedical application Lei Wang : refer to cover II Li Yu: He received his master degree in IC Design Engineering from The Hong Kong University of Science and Technology (HKUST) Now he is a research assistant of biomedical IC design group in MIS, IBEH, SIAT His research interests include low-power ADC design