MPC5607B. MPC5607B Microcontroller Data Sheet. Freescale Semiconductor Data Sheet: Advance Information. Document Number: MPC5607B Rev.

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1 Freescale Semiconductor Data Sheet: Advance Information Document Number: MPC5607B Rev. 3, 01/2010 MPC5607B Microcontroller Data Sheet Features Single issue, 32-bit CPU core complex (e200z0h) Compliant with the Power Architecture embedded category Enhanced instruction set allowing variable length encoding (VLE) for code size footprint reduction. With the optional encoding of mixed 16-bit and 32-bit instructions, it is possible to achieve significant code size footprint reduction. Up to 1.5 Mbytes on-chip Flash supported with the Flash controller Up to 96 Kbytes on-chip SRAM Memory protection unit (MPU) with 8 region descriptors and 32-byte region granularity on certain family members Interrupt controller (INTC) capable of handling 204 selectable-priority interrupt sources Frequency modulated phase-locked loop (FMPLL) Crossbar switch architecture for concurrent access to peripherals, Flash, or RAM from multiple bus masters 16-channel edma controller with multiple transfer request sources using DMA multiplexer Boot assist module (BAM) supports internal Flash programming via a serial link (CAN or SCI) Timer supports I/O channels providing a range of 16-bit input capture, output compare, and pulse width modulation functions (emios) 2 analog-to-digital converters (ADC): one 10-bit and one 12-bit Cross Trigger Unit to enable synchronization of ADC conversions with a timer event from the emios or PIT This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. Freescale Semiconductor, Inc., All rights reserved. 176LQFP (24 x 24) 144 LQFP (20 x 20 ) MPC5607B 208 MAPBGA (17 x 17 ) 100 LQFP (14 x 14 ) Up to 6 serial peripheral interface (DSPI) modules Up to 10 serial communication interface (LINFlex) modules Up to 6 enhanced full CAN (FlexCAN) modules with configurable buffers 1 inter-integrated circuit (I 2 C) interface module Up to 149 configurable general purpose pins supporting input and output operations (package dependent) Real-Time Counter (RTC) Clock source from internal 128 khz or 16 MHz oscillator supporting autonomous wakeup with 1 ms resolution with maximum timeout of 2 seconds Optional support for RTC with clock source from external 32 khz crystal oscillator, supporting wakeup with 1 sec resolution and maximum timeout of 1 hour Up to 8 periodic interrupt timers (PIT) with 32-bit counter resolution Nexus development interface (NDI) per IEEE-ISTO Class Two Plus Device/board boundary scan testing supported per Joint Test Action Group (JTAG) of IEEE (IEEE ) On-chip voltage regulator (VREG) for regulation of input supply for all internal levels

2 1 General description Block diagram Package pinouts LQFP pin configuration LQFP pin configuration MAPBGA pin configuration Electrical characteristics Parameter classification NVUSRO register NVUSRO[PAD3V5V] field description NVUSRO[OSCILLATOR_MARGIN] field description NVUSRO[WATCHDOG_EN] field description Absolute maximum ratings Recommended operating conditions Thermal characteristics External ballast resistor recommendations Package thermal characteristics Power considerations I/O pad electrical characteristics I/O pad types I/O input DC characteristics I/O output DC characteristics Output pin transition times I/O pad current specification nrstin electrical characteristics Power management electrical characteristics Voltage regulator electrical characteristics Voltage monitor electrical characteristics Low voltage domain power consumption Flash memory electrical characteristics Program/Erase characteristics Flash power supply DC characteristics Table of Contents Start-up/Switch-off timings Electromagnetic compatibility (EMC) characteristics Designing hardened software to avoid noise problems Electromagnetic interference (EMI) Absolute maximum ratings (electrical sensitivity) Fast external crystal oscillator (4 to 16 MHz) electrical characteristics Slow external crystal oscillator (32 khz) electrical characteristics FMPLL electrical characteristics Fast internal RC oscillator (16 MHz) electrical characteristics Slow internal RC oscillator (128 khz) electrical characteristics ADC electrical characteristics Introduction Input impedance and ADC accuracy ADC electrical characteristics On-chip peripherals Current consumption DSPI characteristics Nexus characteristics JTAG characteristics Package characteristics Package mechanical data LQFP LQFP LQFP MAPBGA Ordering information Revision history Freescale Semiconductor

3 General description 1 General description The MPC5607B is a new family of next generation microcontrollers built on the Power Architecture embedded category. This document describes the features of the family and options available within the family members, and highlights important electrical and physical characteristics of the device. The MPC5607B family of 32-bit microcontrollers is the latest achievement in integrated automotive application controllers. It belongs to an expanding family of automotive-focused products designed to address the next wave of body electronics applications within the vehicle. The advanced and cost-efficient host processor core of the MPC5607B automotive controller family complies with the Power Architecture embedded category and only implements the VLE (variable-length encoding) APU (Auxillary Processor Unit), providing improved code density. It operates at speeds of up to 64 MHz and offers high performance processing optimized for low power consumption. It capitalizes on the available development infrastructure of current Power Architecture devices and is supported with software drivers, operating systems and configuration code to assist with users implementations. Table 1. MPC5607B Family Comparison 1 Feature Package 100 LQFP CPU Execution speed 3 MPC5605B MPC5606B MPC5607B 144 LQFP 176 LQFP 144 LQFP e200z0h Up to 64 MHz 176 LQFP 176 LQFP Code Flash 768 KB 1 MB 1.5 MB Data Flash 64 (4 x 16) Kbyte RAM 64 KB 80 KB 96 KB MPU DMA 10-bit ADC 12-bit ADC shared with 12-bit ADC 8-entry 16 ch dedicated 4 7ch 15ch 29ch 15ch 29ch dedicated 5 shared with 10-bit ADC Total timer I/O 6 emios Counter / OPWM / ICOC 7 O(I)PWM / OPWFMB / OPWMCB / ICOC 8 37 ch, 16-bit Yes 19 ch Yes 5 ch 19 ch 10 ch 7ch 64 ch, 16-bit O(I)PWM / ICOC 9 7ch 14ch OPWM / ICOC ch 33 ch SCI (LINFlex) SPI (DSPI) CAN (FlexCAN) MAP BGA 2 Freescale Semiconductor 3

4 General description Table 1. MPC5607B Family Comparison 1 (continued) Feature MPC5605B MPC5606B MPC5607B 1.1 Block diagram Figure 1 shows a top-level block diagram of the MPC5607B. 4 I 2 C 1 32 khz oscillator Yes GPIO Debug JTAG N2+ 1 Feature set dependent on selected peripheral multiplexing; table shows example MAPBGA package is for debug use only. 3 Based on 105 C ambient operating temperature. 4 Not shared with 12-bit ADC, but possibly shared with other alternate functions. 5 Not shared with 10-bit ADC, but possibly shared with other alternate functions. 6 Refer to emios section of device reference manual for information on the channel configuration and functions. 7 Each channel supports a range of modes including Modulus counters, PWM generation, Input Capture, Output Compare. 8 Each channel supports a range of modes including PWM generation with dead time, Input Capture, Output Compare. 9 Each channel supports a range of modes including PWM generation, Input Capture, Output Compare, Period and Pulse width measurement. 10 Each channel supports a range of modes including PWM generation, Input Capture, and Output Compare. 11 Maximum I/O count based on multiplexing with peripherals. Freescale Semiconductor

5 General description JTAG Port Nexus Port NMI Clocks Interrupt Request Legend: FMPLL Nexus Voltage Regulator RTC SIUL Reset Control External Interrupt Request IMUX GPIO & Pad Control STM I/O JTAG NMI SIUL Interrupt requests from peripheral blocks CMU SWT 19 ch 10bit/12bit ADC ECSM e200z0h Nexus ch 10-bit ADC... PIT INTC ADC Analog-to-Digital Converter BAM Boot Assist Module CAN Controller Area Network (FlexCAN) CMU Clock Monitor Unit CTU Cross Triggering Unit DSPI Deserial Serial Peripheral Interface emios Enhanced Modular Input Output System FMPLL Frequency-Modulated Phase-Locked Loop I2C Inter-integrated Circuit Bus IMUX Internal Multiplexer INTC Interrupt Controller JTAG JTAG controller LINFlex Serial Communication Interface (LIN support) MC_CGM Clock Generation Module CTU Instructions (Master) Peripheral Bridge Figure 1. MPC5607B block diagram Freescale Semiconductor 5 Data (Master) MPU Registers 64 ch emios 64-bit 2 x 3 Crossbar Switch MPU 10 x LINFlex RAM 96 KB SRAM Controller (Slave) MC_RGM MC_CGM MC_ME MC_PCU... edma (Master)... 6 x DSPI... Code Flash 1.5 MB (Slave) BAM I 2 C Flash Controller WKPU... MC_ME Mode Entry Module MPU Memory Protection Unit Nexus NexuS Development Interface (NDI) Level NMI Non-Maskable Interrupt MC_PCU Power Control Unit MC_RGM Reset Generation Module PIT Periodic Interrupt Timer RTC Real-Time Clock SIUL System Integration Unit Lite SRAM Static Random-Access Memory SSCM System Status Configuration Module STM System Timer Module SWT Software Watchdog Timer DataFlash 64 KB (Slave) SSCM 6 x FlexCAN

6 General description Table 2 summarizes the functions of the blocks present on the MPC5607B. Table 2. MPC5607B series block summary Block Function 6 Analog-to-digital converter (ADC) Boot assist module (BAM) Clock generation module (MC_CGM) Crossbar switch (XBAR) Cross triggering unit (CTU) Deserial serial peripheral interface (DSPI) Enhanced modular input output system (emios) Flash memory Converts analog voltages to digital values A block of read-only memory containing VLE code which is executed according to the boot mode of the device Provides logic and control required for the generation of system and peripheral clocks Supports simultaneous connections between two master ports and three slave ports. The crossbar supports a 32-bit address bus width and a 64-bit data bus width. Enables synchronization of ADC conversions with a timer event from the emios or from the PIT Provides a synchronous serial interface for communication with external devices Provides the functionality to generate or measure events Provides non-volatile storage for program code, constants and variables FlexCAN (controller area network) Supports the standard CAN communications protocol Frequency-modulated phase-locked loop (FMPLL) Internal multiplexer (IMUX) SIU subblock Generates high-speed system clocks and supports programmable frequency modulation Allows flexible mapping of peripheral interface on the different pins of the device Inter-integrated circuit (I 2 C ) bus A two wire bidirectional serial bus that provides a simple and efficient method of data exchange between devices Interrupt controller (INTC) JTAG controller LINFlex controller Memory protection unit (MPU) Periodic interrupt timer (PIT) Real-time counter (RTC) Provides priority-based preemptive scheduling of interrupt requests Provides the means to test chip functionality and connectivity while remaining transparent to system logic when not in test mode Manages a high number of LIN (Local Interconnect Network protocol) messages efficiently with a minimum of CPU load Provides hardware access control for all memory references generated in a device Produces periodic interrupts and triggers A free running counter used for time keeping applications, the RTC can be configured to generate an interrupt at a predefined interval independent of the mode of operation (run mode or low-power mode) Freescale Semiconductor

7 Package pinouts Table 2. MPC5607B series block summary (continued) Block Function Reset generation module (MC_RGM) Static random-access memory (SRAM) 2 Package pinouts Centralizes reset sources and manages the device reset sequence of the device Provides storage for program code, constants, and variables System integration unit lite (SIUL) Provides control over all the electrical pad controls and up 32 ports with 16 bits of bidirectional, general-purpose input and output signals and supports up to 32 external interrupts with trigger event configuration System timer module (STM) Provides a set of output compare events to support AutoSAR and operating system tasks The available LQFP pinouts and the 208 MAPBGA ballmap are provided in the following figures. For pin signal descriptions, please refer to the device reference manual. Freescale Semiconductor 7

8 Package pinouts LQFP pin configuration 8 LIN0RX/WKUP[11]/SCL/E0UC[31]/GPIO[19]/PB[3] LIN2RX/WKUP[13]/E0UC[7]/GPIO[41]/PC[9] EIRQ[8]/SCK2/E0UC[14]/GPIO[46]/PC[14] EIRQ[20]/CS0_2/E0UC[15]/GPIO[47]/PC[15] E1UC[18]/SCK_5/GPIO[148]/PJ[4] VDD_HV VSS_HV E1UC[17]/SOUT_5/GPIO[127]/PH[15] E1UC[26]/CS0_3/SOUT_4/GPIO[125]/PH[13] E1UC[27]/CS1_3/SCK_4/GPIO[126]/PH[14] CS0_4/E1UC[30]/GPIO[134]/PI[6] CS1_4/E1UC[31]/GPIO[135]/PI[7] SIN_3/WKUP[18]/E1UC[14]/GPIO[101]/PG[5] SCK_3/E1UC[13]/GPIO[100]/PG[4] WKUP[17]/CS0_3/E1UC[12]/GPIO[99]/PG[3] SOUT_3/E1UC[11]/GPIO[98]/PG[2] MA[2]/WKUP[3]/E0UC[2]/GPIO[2]/PA[2] CAN5RX/WKUP[6]/E0UC[16]/GPIO[64]/PE[0] WKUP[2]/NMI/E0UC[1]/GPIO[1]/PA[1] CAN5TX/E0UC[17]/GPIO[65]/PE[1] CAN3TX/E0UC[22]/CAN2TX/GPIO[72]/PE[8] CAN3RX/CAN2RX/WKUP[7]/E0UC[23]/GPIO[73]/PE[9] EIRQ[10]/E1UC[30]/CS3_1/LIN3TX/GPIO[74]/PE[10] WKUP[19]/E0UC[13]/CLKOUT/E0UC[0]/GPIO[0]/PA[0] LIN3RX/WKUP[14]/CS4_1/E0UC[24]/GPIO[75]/PE[11] VSS_HV VDD_HV VSS_HV RESET VSS_LV VDD_LV VDD_BV LIN7RX/WKUP[21]/SCK_2/E1UC[18]/GPIO[105]/PG[9] EIRQ[15]/CS0_2/LIN7TX/E1UC[17]/GPIO[104]/PG[8] CAN4RX/CAN1RX/WKUP[5]/MA[2]/GPIO[43]/PC[11] MA[1]/CAN4TX/CAN1TX/GPIO[42]/PC[10] LIN6RX/WKUP[20]/E1UC[30]/E1UC[16]/GPIO[103]/PG[7] LIN6TX/E1UC[15]/GPIO[102]/PG[6] LIN0TX/E0UC[30]/CAN0TX/GPIO[16]/PB[0] CAN0RX/WKUP[4]/LIN0RX/E0UC[31]/GPIO[17]/PB[1] CAN2RX/CAN3RX/WKUP[22]/CS5_0/E1UC[1]/GPIO[89]/PF[9] CAN2TX/CS4_0/CAN3TX/GPIO[88]/PF[8] LIN5TX/E1UC[25]/GPIO[92]/PF[12] E1UC[28]/LIN1TX/GPIO[38]/PC[6] LIN1RX/WKUP[12]/E1UC[29]/GPIO[39]/PC[7] E1UC[2]/LIN4TX/CS1_0/GPIO[90]/PF[10] LIN4RX/WKUP[15]/E1UC[3]/CS2_0/GPIO[91]/PF[11] WKUP[10]/E0UC[1]/SCK_0/CS0_0/GPIO[15]/PA[15] LIN5RX/WKUP[16]/E1UC[26]/GPIO[93]/PF[13] EIRQ[4]/E0UC[0]/CS0_0/SCK_0/GPIO[14]/PA[14] LIN5RX/WKUP[9]/CS0_1/E0UC[4]/GPIO[4]/PA[4] E0UC[29]/SOUT_0/GPIO[13]/PA[13] EIRQ[17]/SIN_0/CS3_1/E0UC[28]/GPIO[12]/PA[12] VDD_LV VSS_LV XTAL VSS_HV EXTAL VDD_HV Note: Availability of port pin alternate functions depends on product selection. PB[2]/GPIO[18]/LIN0TX/SDA/E0UC[30] PC[8]/GPIO[40]/LIN2TX/E0UC[3] PC[13]/GPIO[45]/E0UC[13]/SOUT_2 PC[12]/GPIO[44]/E0UC[12]/EIRQ[19]/SIN_2 PI[0]/GPIO[128]/E0UC[28]/LIN8TX PI[1]/GPIO[129]/E0UC[29]/WKUP[24]/LIN8RX PI[2]/GPIO[130]/E0UC[30]/LIN9TX PI[3]/GPIO[131]/E0UC[31]/WKUP[23]/LIN9RX PE[7]/GPIO[71]/E0UC[23]/CS2_0/MA[0]/EIRQ[23] PE[6]/GPIO[70]/E0UC[22]/CS3_0/MA[1]/EIRQ[22] PH[8]/GPIO[120]/E1UC[10]/CS2_2/MA[0] PH[7]/GPIO[119]/E1UC[9]/CS3_2/MA[1] PH[6]/GPIO[118]/E1UC[8]/MA[2] PH[5]/GPIO[117]/E1UC[7] PH[4]/GPIO[116]/E1UC[6] PE[5]/GPIO[69]/E0UC[21]/CS0_1/MA[2] PE[4]/GPIO[68]/E0UC[20]/SCK_1/EIRQ[9] PC[4]/GPIO[36]/E1UC[31]/EIRQ[18]/SIN_1/CAN3RX PC[5]/GPIO[37]/SOUT_1/CAN3TX/EIRQ[7] PE[3]/GPIO[67]/E0UC[19]/SOUT_1 PE[2]/GPIO[66]/E0UC[18]/EIRQ[21]/SIN_1 PH[9]/GPIO[121]/TCK PC[0]/GPIO[32]/TDI VSS_LV VDD_LV VDD_HV VSS_HV PC[1]/GPIO[33]/TDO PH[10]/GPIO[122]/TMS PA[6]/GPIO[6]/E0UC[6]/CS1_1/EIRQ[1]/LIN4RX PA[5]/GPIO[5]/E0UC[5]/LIN4TX PC[2]/GPIO[34]/SCK_1/CAN4TX/EIRQ[5] PC[3]/GPIO[35]/CS0_1/MA[0]/EIRQ[6]/CAN4RX/CAN1RX PI[4]/GPIO[132]/E1UC[28]/SOUT_4 PI[5]/GPIO[133]/E1UC[29]/SCK_4 PH[12]/GPIO[124]/SCK_3/CS1_4/E1UC[25] PH[11]/GPIO[123]/SOUT_3/CS0_4/E1UC[5] PG[11]/GPIO[107]/E0UC[25]/CS0_4 PG[10]/GPIO[106]/E0UC[24]/E1UC[31]/SIN_4 PE[15]/GPIO[79]/CS0_2/E1UC[22] PE[14]/GPIO[78]/SCK_2/E1UC[21]/EIRQ[12] PG[15]/GPIO[111]/E1UC[1]/LIN8RX PG[14]/GPIO[110]/E1UC[0]/LIN8TX PE[12]/GPIO[76]/E1UC[19]/EIRQ[11]/SIN_2/ADC1_S[7] ADC1_S[5]/OSC32K_EXTAL/WKUP[26]/ADC0_S[1]/GPIO[25]/PB[9] ADC1_S[4]/OSC32K_XTAL/WKUP[25]/ADC_S[0]/GPIO[24]/PB[8] 176 LQFP Top view ADC0_S[6]/WKUP[8]/ANS[2]/GPIO[26]/PB[10] ADC0_S[8]/CS3_1/E0UC[10]/GPIO[80]/PF[0] ADC0_S[9]/CS4_1/E0UC[11]/GPIO[81]/PF[1] ADC0_S[10]/CS0_2/E0UC[12]/GPIO[82]/PF[2] ADC0_S[11]/CS1_2/E0UC[13]/GPIO[83]/PF[3] ADC0_S[12]/CS2_2/E0UC[14]/GPIO[84]/PF[4] ADC0_S[13]/CS3_2/E0UC[22]/GPIO[85]/PF[5] ADC0_S14]/CS1_1/E0UC[23]/GPIO[86]/PF[6] ADC0_S[15]/CS2_1/GPIO[87]/PF[7] ADC0_S[27]/CS1_5/GPIO[147]/PJ[3] ADC0_S[26]/CS0_5/GPIO[146]/PJ[2] SIN_5/ANS[25]/GPIO[145]/PJ[1] ADC0_S[24]/CS1_4/GPIO[144]/PJ[0] ADC0_S[23]/CS0_4/GPIO[143]/PI[15] SIN_4/ANS[22]/GPIO[142]/PI[14] ANP[4]/WKUP[27]/GPIO[48]/PD[0] ADC1_P[5]/ADC0_P[5]/WKUP[28]/GPIO[49]/PD[1] ADC1_P[6]/ADC0_P[6]/GPIO[50]/PD[2] ADC1_P[8]/ADC0_P[7]/GPIO[51]/PD[3] ADC1_P[8]/ADC0_P[8]/GPIO[52]/PD[4] ADC1_P[9]/ADC0_P[9]/GPIO[53]/PD[5] ADC0_P[10]/ADC0_P[10]/GPIO[54]/PD[6] ADC1_P[11]/ADC0_P[11]/GPIO[55]/PD[7] VDD_HV VSS_HV ADC1_P[12]/ADC0_P[12]/GPIO[56]/PD[8] ADC1_P[0]/ADC0_P[0]/GPIO[20]/PB[4] Figure LQFP pin configuration (top view) PA[11]/GPIO[11]/E0UC[11]/SCL/EIRQ[16]/LIN2RX/ADC1_S[3] PA[10]/GPIO[10]/E0UC[10]/SDA/LIN2TX/ADC1_S[2] PA[9]/GPIO[9]/E0UC[9]/CS2_1/FAB PA[8]/GPIO[8]/E0UC[8]/E0UC[14]/EIRQ[3]/ABS[0]/LIN3RX PA[7]/GPIO[7]/E0UC[7]/LIN3TX/EIRQ[2]/ADC1_S[1] PE[13]/GPIO[77]/SOUT_2/E1UC[20] PF[14]/GPIO[94]/CAN4TX/E1UC[27]/CAN1TX PF[15]/GPIO[95]/E1UC[4]/EIRQ[13]/CAN4RX/CAN1RX VDD_HV VSS_HV PG[0]/GPIO[96]/CAN5TX/E1UC[23] PG[1]/GPIO[97]/E1UC[24]/EIRQ[14]/CAN5RX PH[3]/GPIO[115]/E1UC[5]/CS0_1 PH[2]/GPIO[114]/E1UC[4]/SCK_1 PH[1]/GPIO[113]/E1UC[3]/SOUT_1 PH[0]/GPIO[112]/E1UC[2]/SIN_1 PG[12]/GPIO[108]/E0UC[26]/SOUT_4 PG[13]/GPIO[109]/E0UC[27]/SCK_4 PA[3]/GPIO[3]/E0UC[3]/LIN5TX/CS4_1/EIRQ[0]/ADC1_S[0] PI[13]/GPIO[141]/CS1_3/ADC0_S[21] PI[12]/GPIO[140]/CS0_3/ADC0_S20] PI[11]/GPIO[139]/ANS[19]/SIN_3 PI[10]/GPIO[138]/ADC0_S[18] PI[9]/GPIO[137]/ADC0_S[17] PI[8]/GPIO[136]/ADC0_S[16] PB[15]/GPIO[31]/E0UC[7]/CS4_0/ADC0_X[3] PD[15]/GPIO[63]/CS2_1/E0UC[27]/ADC0_S[7] PB[14]/GPIO[30]/E0UC[6]/CS3_ 0/ADC0_X[2] PD[14]/GPIO[62]/CS1_1/E0UC[26]/ADC0_S[6] PB[13]/GPIO[29]/E0UC[5]/CS2_0/ADC0_X[1] PD[13]/GPIO[61]/CS0_1/E0UC[25]/ADC0_S[5] PB[12]/GPIO[28]/E0UC[4]/CS1_0/ADC0_X[0] PD[12]/GPIO[60]/CS5_0/E0UC[24]/ADC0_S[4] VDD_HV_ADC1 VSS_HV_ADC1 PB[11]/GPIO[27]/E0UC[3]/CS0_0/ADC0_S[3] PD[11]/GPIO[59]/ADC0_P[15]/ADC1_P[15] PD[10]/GPIO[58]/ADC0_P[14]/ADC1_P[14] PD[9]/GPIO[57]/ADC0_P[13]/ADC1_P[13] PB[7]/GPIO[23]/ADC0_P[3]/ADC1_P[3] PB[6]/GPIO[22]/ADC0_P[2]/ADC1_P[2] PB[5]/GPIO[21]/ADC0_P[1]/ADC1_P[1] VDD_HV_ADC0 VSS_HV_ADC0 Freescale Semiconductor

9 Package pinouts LQFP pin configuration LIN0RX/WKUP[11]/SCL/E0UC[31]/GPIO[19]/PB[3] LIN2RX/WKUP[13]/E0UC[7]/GPIO[41]/PC[9] EIRQ[8]/SCK2/E0UC[14]/GPIO[46]/PC[14] EIRQ[20]/CS0_2/E0UC[15]/GPIO[47]/PC[15] SIN_3/WKUP[18]/E1UC[14]/GPIO[101]/PG[5] SCK_3/E1UC[13]/GPIO[100]/PG[4] WKUP[17]/CS0_3/E1UC[12]/GPIO[99]/PG[3] SOUT_3/E1UC[11]/GPIO[98]/PG[2] MA[2]/WKUP[3]/E0UC[2]/GPIO[2]/PA[2] CAN5RX/WKUP[6]/E0UC[16]/GPIO[64]/PE[0] WKUP[2]/NMI[0]/E0UC[1]/GPIO[1]/PA[1] CAN5TX/E0UC[17]/GPIO[65]/PE[1] CAN3TX/E0UC[22]/CAN2TX/GPIO[72]/PE[8] CAN3RX/CAN2RX/WKUP[7]/E0UC[23]/GPIO[73]/PE[9] EIRQ[10]/E1UC[30]/CS3_1/LIN3TX/GPIO[74]/PE[10] WKUP[19]/E0UC[13]/CLKOUT/E0UC[0]/GPIO[0]/PA[0] LIN3RX/WKUP[14]/CS4_1/E0UC[24]/GPIO[75]/PE[11] VSS_HV VDD_HV VSS_HV RESET VSS_LV VDD_LV VDD_BV LIN7RX/EIRQ[21]/SCK_2/E1UC[18]/GPIO[105]/PG[9] EIRQ[15]/CS0_2/LIN7TX/E1UC[17]/GPIO[104]/PG[8] CAN4RX/CAN1RX/WKUP[5]/MA[2]/GPIO[43]/PC[11] MA[1]/CAN4TX/CAN1TX/GPIO[42]/PC[10] LIN6RX/WKUP[20]/E1UC[30]/E1UC[16]/GPIO[103]/PG[7] LIN6TX/E1UC[15]/GPIO[102]/PG[6] E0UC[30]/CAN0TX/GPIO[16]/PB[0] LIN0RX/CAN0RX/WKUP[4]/E0UC[31]/GPIO[17]/PB[1] CAN2RX/CAN3RX/WKUP[22]/CS5_0/E1UC[1]/GPIO[89]/PF[9] CAN2TX/CS4_0/CAN3TX/GPIO[88]/PF[8] LIN5TX/E1UC[25]/GPIO[92]/PF[12] E1UC[28]/LIN1TX/GPIO[38]/PC[6] Note: Availability of port pin alternate functions depends on product selection PB[2]/GPIO[18]/LIN0TX/SDA/E0UC[30] PC[8]/GPIO[40]/LIN2TX/E0UC[3] PC[13]/GPIO[45]/E0UC[13]/SOUT_2 PC[12]/GPIO[44]/E0UC[12]/EIRQ[19]/SIN_2 PE[7]/GPIO[71]/E0UC[23]/CS2_0/MA[0]/EIRQ[23] PE[6]/GPIO[70]/E0UC[22]/CS3_0/MA[1]/EIRQ[22] PH[8]/GPIO[120]/E1UC[10]/CS2_2/MA[0] PH[7]/GPIO[119]/E1UC[9]/CS3_2/MA[1] PH[6]/GPIO[118]/E1UC[8]/MA[2] PH[5]/GPIO[117]/E1UC[7] PH[4]/GPIO[116]/E1UC[6] PE[5]/GPIO[69]/E0UC[21]/CS0_1/MA[2] PE[4]/GPIO[68]/E0UC[20]/SCK_1/EIRQ[9] PC[4]/GPIO[36]/E1UC[31]/EIRQ[18]/SIN_1/CAN3RX PC[5]/GPIO[37]/SOUT_1/CAN3TX/EIRQ[7] PE[3]/GPIO[67]/E0UC[19]/SOUT_1 PE[2]/GPIO[66]/E0UC[18]/EIRQ[21]/SIN_1 PH[9]/GPIO[121]/TCK PC[0]/GPIO[32]/TDI VSS_LV VDD_LV VDD_HV VSS_HV PC[1]/GPIO[33]/TDO PH[10]/GPIO[122]/TMS PA[6]/GPIO[6]/E0UC[6]/EIRQ[1]/LIN4RX/CS1_1 PA[5]/GPIO[5]/E0UC[5]/LIN4TX PC[2]/GPIO[34]/SCK_1/CAN4TX/EIRQ[5] PC[3]/GPIO[35]/CS0_1/MA[0]/EIRQ[6]/CAN4RX/CAN1RX PG[11]/GPIO[107]/E0UC[25]/CS0_4 PG[10]/GPIO[106]/E0UC[24]/E1UC[31]/SIN_4 PE[15]/GPIO[79]/CS0_2/E1UC[22] PE[14]/GPIO[78]/SCK_2/E1UC[21]/EIRQ[12] PG[15]/GPIO[111]/E1UC[1]/LIN8RX PG[14]/GPIO[110]/E1UC[0]/LIN8TX PE[12]/GPIO[76]/E1UC[19]/EIRQ[11]/SIN_2\ANS[7] LQFP Top view LIN1RX/WKUP[12]/E1UC[29]/GPIO[39]/PC[7] E1UC[2]/LIN4TX/CS1_0/GPIO[90]/PF[10] EMIOS[1]\LIN4RX/WKUP[15]/E1UC[3]/CS2_0/GPIO[91]/PF[11] WKUP[10]/E0UC[1]/SCK_0/CS0_0/GPIO[15]/PA[15] LIN5RX/WKUP[16]/E1UC[26]/GPIO[93]/PF[13] EIRQ[4]/E0UC[0]/CS0_0/SCK_0/GPIO[14]/PA[14] CSO_1\LIN5RX/WKUP[9]/E0UC[4]/GPIO[4]/PA[4] E0UC[29]/SOUT_0/GPIO[13]/PA[13] CS3_1\EIRQ[17]/SIN_0/E0UC[28]/GPIO[12]/PA[12] VDD_LV VSS_LV XTAL VSS_HV EXTAL VDD_HV EIRQ[26]\ADC1_S[5]\OSC32K_EXTAL//WKUP[26]/ADC0_S[1]/GPIO[25]/PB[9] EIRQ[25]\OSC32K_XTAL//WKUP[25]/ANS[0]/GPIO[24]/PB[8] ADC1_S[6]\WKUP[8]/ADC0_S[2]/GPIO[26]/PB[10] ADC0_S[8]/CS3_1/E0UC[10]/GPIO[80]/PF[0] ADC0_S[9]/CS4_1/E0UC[11]/GPIO[81]/PF[1] ADC0_S[10]/CS0_2/E0UC[12]/GPIO[82]/PF[2] ADC0_S[11]/CS1_2/E0UC[13]/GPIO[83]/PF[3] ADC0_S[12]/CS2_2/E0UC[14]/GPIO[84]/PF[4] ADC0_S[13]/CS3_2/E0UC[22]/GPIO[85]/PF[5] ADC0_S[14]/CS1_1/E0UC[23]/GPIO[86]/PF[6] ADC0_S[15]/CS2_1/GPIO[87]/PF[7] EIRQ[27]\ANP[4]//WKUP[27]/GPIO[48]/PD[0] EIRQ[28]\ANP[5]/WKUP[28]/GPIO[49]/PD[1] ADC1_P[7]/ADC0_P[6]/GPIO[50]/PD[2] ADC1_P[7]/ADC0_P[7]/GPIO[51]/PD[3] ADC1_P[8]/ADC0_P[8]/GPIO[52]/PD[4] ADC1_P[9]/ADC0_P[9]/GPIO[53]/PD[5] ADC1_P[10]/ADC0_P[10]/GPIO[54]/PD[6] ADC1_P[11]/ADC0_P11]/GPIO[55]/PD[7] ADC1_P[12]/ADC0_P[12]/GPIO[56]/PD[8] ADC1_P[0]/ADC0_P[0]/GPIO[20]/PB[4] Figure LQFP pin configuration (top view) Freescale Semiconductor PA[11]/GPIO[11]/E0UC[11]/SCL/EIRQ[16]/LIN2RX/ADC1_S[3] PA[10]/GPIO[10]/E0UC[10]/SDA/LIN2TX/ADC1_S[2] PA[9]/GPIO[9]/E0UC[9]/FAB/CS2_1 PA[8]/GPIO[8]/E0UC[8]/E0UC[14]/EIRQ[3]/ABS[0]/LIN3RX PA[7]/GPIO[7]/E0UC[7]/LIN3TX/EIRQ[2]/ADC1_S[1] PE[13]/GPIO[77]/SOUT_2/E1UC[20] PF[14]/GPIO[94]/CAN4TX/E1UC[27]/CAN1TX PF[15]/GPIO[95]/E1UC[4]/EIRQ[13]/CAN4RX/CAN1RX VDD_HV VSS_HV PG[0]/GPIO[96]/CAN5TX/E1UC[23] PG[1]/GPIO[97]/E1UC[24]/EIRQ[14]/CAN5RX PH[3]/GPIO[115]/E1UC[5]/CS0_1 PH[2]/GPIO[114]/E1UC[4]/SCK_1 PH[1]/GPIO[113]/E1UC[3]/SOUT_1 PH[0]/GPIO[112]/E1UC[2]/SIN_1 PG[12]/GPIO[108]/E0UC[26]/SOUT_4 PG[13]/GPIO[109]/E0UC[27]/SCK_4 PA[3]/GPIO[3]/E0UC[3]/LIN5TX/EIRQ[0]/CS4_1/ADC1_S[0] PB[15]/GPIO[31]/E0UC[7]/CS4_0/ADC0_X[3] PD[15]/GPIO[63]/CS2_1/E0UC[27]/ADC0_S[7] PB[14]/GPIO[30]/E0UC[6]/CS3_ 0/ADC0_X[2] PD[14]/GPIO[62]/CS1_1/E0UC[26]/ADC0_S[6] PB[13]/GPIO[29]/E0UC[5]/CS2_0/ADC0_X[1] PD[13]/GPIO[61]/CS0_1/E0UC[25]/ADC0_S[5] /GPIO[28]/E0UC[4]/CS1_0 VDD_HV_ADC1 VSS_HV_ADC1 PD[11]/GPIO[59]/ADC0_P[15]/ADC1_P[15] PD[10]/GPIO[58]/ADC0_P[14]/ADC1_P[14] PD[9]/GPIO[57]/ADC0_P[13]/ADC1_P[13] PB[7]/GPIO[23]/ADC0_P[3]/ADC1_P[3] PB[6]/GPIO[22]/ADC0_P[2]/ADC1_P[2] PB[5]/GPIO[21]/ADC0_P[1]/ADC1_P[1] VDD_HV_ADC0 VSS_HV_ADC0

10 Package pinouts MAPBGA pin configuration A B C D E PC[8] PC[1 3] PH[1 5] PC[9] PB[2] PH[1 3] PC[14 ] PH[14 ] VDD_ HV PI[6] PJ[4] PH[8] PH[4] PC[5] PC[0] PI[0] PI[1] PC[2] PI[4] PE[1 5] PC[1 2] PE[6] PH[5] PC[4] PH[9] PH[1 0] PB[3] PE[7] PH[7] PE[5] PE[3] VSS_ LV PC[1 5] PI[7] PH[6] PE[4] PE[2] VDD _LV PI[2] PC[3] PG[1 1] Figure MAPBGA configuration PG[1 5] PC[1] PI[3] PA[5] PI[5] PE[1 4] VDD _HV NC PA[6] PH[1 2] PG[1 0] PH[1 1] PG[1 4] PG[4] PG[5] PG[3] PG[2] PG[1] PG[0] PF[1 5] PE[1 2] NC NC A PA[1 1] PA[1 0] PA[9] PA[8] F PE[0] PA[2] PA[1] PE[1] PH[0] PH[1] PH[3] PH[2] F G H J K L M N P R T PE[9] PE[8] PE[1 0] VSS_ HV RESE T PE[1 1] VSS_ LV VDD _HV EVTI NC VDD _BV PA[0] NC VSS_ HV VSS_ HV NC NC VSS_ HV VDD _LV PG[9] PG[8] NC EVT O PG[7] PG[6] PC[1 0] PB[1] PC[1 1] PF[9] PB[0] VDD _HV VSS_ HV PJ[0] PA[4] VSS_ LV PF[8] PJ[3] PC[7] PJ[2] PJ[1] PA[1 4] PF[12 ] PC[6] PF[1 0] PF[1 1] NC NC NC MCK O VDD _HV NC PA[1 5] PF[1 3] VDD _LV PA[1 3] PA[1 2] VSS_ HV VSS_ HV VSS_ HV VSS_ HV EXTA L VSS_ HV VSS_ HV VSS_ HV VSS_ HV VDD _HV XTAL PB[1 0] PI[14 ] PI[15 ] VSS_ HV VSS_ HV VSS_ HV VSS_ HV PF[0] PF[4] VSS_ HV_ ADC 1 VDD _HV MDO 3 PF[1 4] PI[12 ] MDO 2 PE[1 3] PI[13 ] MDO 0 PI[8] PI[9] PI[10 ] VDD _HV_ ADC 1 PB[1 5] PB[1 3] PB[1 1] PG[1 2] PD[1 5] PD[1 3] PD[1 0] PF[1] PF[5] PD[0] PD[3] VDD _HV_ ADC 0 PA[7] VDD _HV MSE O MDO 1 PI[11 ] PA[3] PG[1 3] PD[1 4] PD[1 2] XTAL PF[3] PF[7] PD[2] PD[4] PD[7] VSS_ HV_ ADC 0 EXTA L PB[1 4] PB[1 2] PD[9] PD[1 1] PB[6] PB[7] PB[5] PF[2] PF[6] PD[1] PD[5] PD[6] PD[8] PB[4] NOTE: The 208 MAPBGA is available only as development package for Nexus 2+. NC = Not connected B C D E G H J K L M N P R T 10 Freescale Semiconductor

11 3 Electrical characteristics This section contains electrical characteristics of the device as well as temperature and power considerations. This product contains devices to protect the inputs against damage due to high static voltages. However, it is advisable to take precautions to avoid application of any voltage higher than the specified maximum rated voltages. To enhance reliability, unused inputs can be driven to an appropriate logic voltage level (V DD or V SS ). This could be done by the internal pull-up and pull-down, which is provided by the product for most general purpose pins. The parameters listed in the following tables represent the characteristics of the device and its demands on the system. In the tables where the device logic provides signals with their respective timing characteristics, the symbol CC for Controller Characteristics is included in the Symbol column. In the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol SR for System Requirement is included in the Symbol column. CAUTION All of the following figures are indicative and must be confirmed during either silicon validation, silicon characterization or silicon reliability trial. 3.1 Parameter classification The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding, the classifications listed in Table 3 are used and the parameters are tagged accordingly in the tables where appropriate. Table 3. Parameter classifications Classification tag P C T D NOTE The classification is shown in the column labeled C in the parameter tables where appropriate. 3.2 NVUSRO register Tag description Those parameters are guaranteed during production testing on each individual device. Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. Those parameters are derived mainly from simulations. Portions of the device configuration, such as high voltage supply, oscillator margin, and watchdog enable/disable after reset are controlled via bit values in the Non-Volatile User Options Register (NVUSRO) register NVUSRO[PAD3V5V] field description Table 4 shows how NVUSRO[PAD3V5V] controls the device configuration. Freescale Semiconductor 11

12 Table 4. PAD3V5V field description 1 Value 2 Description 0 High voltage supply is 5.0 V 1 High voltage supply is 3.3 V 1 See the device reference manual for more information on the NVUSRO register. 2 '1' is delivery value. It is part of shadow Flash, thus programmable by customer. The DC electrical characteristics are dependent on the PAD3V5V bit value NVUSRO[OSCILLATOR_MARGIN] field description Table 5 shows how NVUSRO[OSCILLATOR_MARGIN] controls the device configuration. Table 5. OSCILLATOR_MARGIN field description 1 Value 2 Description 0 Low consumption configuration (4 MHz/8 MHz) 1 High margin configuration (4 MHz/16 MHz) 1 See the device reference manual for more information on the NVUSRO register. 2 '1' is delivery value. It is part of shadow Flash, thus programmable by customer. The main external crystal oscillator consumption is dependent on the OSCILLATOR_MARGIN bit value NVUSRO[WATCHDOG_EN] field description Table 5 shows how NVUSRO[WATCHDOG_EN] controls the device configuration. Table 6. WATCHDOG_EN field description 1 Value 2 Description 0 Disable after reset 1 Enable after reset 1 See the device reference manual for more information on the NVUSRO register. 2 '1' is delivery value. It is part of shadow Flash, thus programmable by customer. 12 Freescale Semiconductor

13 3.3 Absolute maximum ratings Table 7. Absolute maximum ratings Symbol Parameter Conditions V SS SR Digital ground on VSS_HV pins V DD SR Voltage on VDD_HV pins with respect to ground (V SS ) V SS_LV SR Voltage on VSS_LV (low voltage digital supply) pins with respect to ground (V SS ) V DD_BV SR Voltage on VDD_BV pin (regulator supply) with respect to ground (V SS ) V SS_ADC SR Voltage on VSS_HV_ADC 0, VSS_HV_ADC 1 (ADC reference) pin with respect to ground (V SS ) V DD_ADC SR Voltage on VSS_HV_ADC 0, VSS_HV_ADC 1 (ADC reference) with respect to ground (V SS ) V IN SR Voltage on any GPIO pin with respect to ground (V SS ) Freescale Semiconductor 13 Min Value Max Unit 0 0 V V V SS -0.1 V SS +0.1 V V Relative to V DD -0.3 V DD +0.3 V SS -0.1 V SS +0.1 V V Relative to V DD V DD 0.3 V DD V Relative to V DD V DD 0.3 V DD +0.3

14 Table 7. Absolute maximum ratings (continued) Symbol Parameter Conditions I INJPAD SR Injected input current on any pin during overload condition I INJSUM SR Absolute sum of all injected input currents during overload condition I AVGSEG SR Sum of all the static I/O current within a supply segment T STORAGE SR Storage temperature NOTE Stresses exceeding the recommended absolute maximum ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification are not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During overload conditions (V IN >V DD or V IN <V SS ), the voltage on pins with respect to ground (V SS ) must not exceed the recommended values. 3.4 Recommended operating conditions ma V DD = 5.0 V ± 10%, PAD3V5V = 0 V DD = 3.3 V ± 10%, PAD3V5V = 1 70 ma C Table 8. Recommended operating conditions (3.3 V) Symbol Parameter Conditions 64 Min Value V SS SR Digital ground on VSS_HV pins 0 0 V 1 V DD SR Voltage on VDD_HV pins with respect to ground (V SS ) V V 2 SS_LV SR Voltage on VSS_LV (low voltage digital supply) pins with respect to ground (V SS ) V SS 0.1 V SS +0.1 V V 3 DD_BV SR Voltage on VDD_BV pin (regulator V supply) with respect to ground (V SS ) Relative to V DD V DD 0.1 V DD +0.1 Min Value Max Max Unit Unit 14 Freescale Semiconductor

15 Table 8. Recommended operating conditions (3.3 V) (continued) Electrical characteristics Symbol Parameter Conditions V SS_ADC V DD_ADC 4 V IN I INJPAD I INJSUM SR Voltage on VSS_HV_ADC0, VSS_HV_ADC1 (ADC reference) pin with respect to ground (V SS ) SR Voltage on VSS_HV_ADC0, VSS_HV_ADC1 (ADC reference) with respect to ground (V SS ) SR Voltage on any GPIO pin with respect to ground (V SS ) SR Injected input current on any pin during overload condition SR Absolute sum of all injected input currents during overload condition V SS 0.1 V SS +0.1 V V Relative to V DD V DD 0.1 V DD +0.1 V SS 0.1 V Relative to V DD V DD ma TV DD SR V DD slope to ensure correct power up V/µs T A SR Ambient temperature under bias f CPU < 64 MHz C T J SR Junction temperature under bias nf capacitance needs to be provided between each V DD /V SS pair nf capacitance needs to be provided between each V DD_LV /V SS_LV supply pair nf capacitance needs to be provided between V DD_BV and the nearest V SS_LV (higher value may be needed depending on external regulator characteristics) nf capacitance needs to be provided between V DD_ADC /V SS_ADC pair. 5 Full electrical specification cannot be guaranteed when voltage drops below 3.0 V. In particular, ADC electrical characteristics and I/Os DC electrical specification may not be guaranteed. When voltage drops below V LVDHVL, device is reset. 6 Guaranteed by device validation Table 9. Recommended operating conditions (5.0 V) Symbol Parameter Conditions Freescale Semiconductor 15 Min Value V SS SR Digital ground on VSS_HV pins 0 0 V 1 V DD SR Voltage on VDD_HV pins with respect to ground (V SS ) V V SS_LV 3 V DD_BV 4 V SS_ADC SR Voltage on VSS_LV (low voltage digital supply) pins with respect to ground (V SS ) SR Voltage on VDD_BV pin (regulator supply) with respect to ground (V SS ) SR Voltage on VSS_HV_ADC0, VSS_HV_ADC1 (ADC reference) pin with respect to ground (V SS ) Min Value Max Max Voltage drop Unit V SS -0.1 V SS +0.1 V V Voltage drop Relative to V DD V DD -0.1 V DD +0.1 Unit V SS -0.1 V SS +0.1 V

16 Table 9. Recommended operating conditions (5.0 V) (continued) 16 Symbol Parameter Conditions V DD_ADC 5 SR Voltage on VSS_HV_ADC0, VSS_HV_ADC1 (ADC reference) with respect to ground (V SS ) NOTE RAM data retention is guaranteed wi th V DD_LV not below 1.08 V V Voltage drop Relative to V DD V DD -0.1 V DD +0.1 V IN SR Voltage on any GPIO pin with respect to ground (V SS ) V SS V I INJPAD I INJSUM SR Injected input current on any pin during overload condition SR Absolute sum of all injected input currents during overload condition Relative to V DD - V DD ma TV DD SR V DD slope to ensure correct power up V/µs 3 V/s T A C-Grade SR Ambient temperature under bias f CPU < 64 MHz C Part T J C-Grade SR Junction temperature under bias Part T A V-Grade SR Ambient temperature under bias f CPU < 64 MHz Part T J V-Grade SR Junction temperature under bias Part T A M-Grade SR Ambient temperature under bias f CPU < 60 MHz Part T J M-Grade Part SR Junction temperature under bias nf capacitance needs to be provided between each V DD /V SS pair 2 Full device operation is guaranteed by design when the voltage drops below 4.5V down to 3.6V. However, certain analog electrical characteristics will not be guaranteed to stay within the stated limits nf capacitance needs to be provided between each V DD_LV /V SS_LV supply pair nf capacitance needs to be provided between V DD_BV and the nearest V SS_LV (higher value may be needed depending on external regulator characteristics). This decoupling need to be increased as recommended in Section 3.5.1, External ballast resistor recommendations incase external ballast resistor is planned to be used nf capacitance needs to be provided between V DD_ADC /V SS_ADC pair 6 Guaranteed by device validation Min Value Max Unit Freescale Semiconductor

17 3.5 Thermal characteristics External ballast resistor recommendations External ballast resistor on V DD_BV pin helps in reducing the overall power dissipation inside the device. This resistor is required only when maximum power consumption exceeds the limit imposed by package thermal characteristics. As stated in Table 10 LQFP thermal characteristics, considering thermal resistance of LQFP144 as 48.3 C/W, at ambient T A = 125 C, the junction temp T j will cross 150 C if total power dissipation > ( )/48.3 = 517 mw. Therefore, total device current I DDMAX at 125 C/5.5V must not exceed 94.1 ma (i.e. PD/VDD). Assuming an average I DD (V DD_HV ) of ma consumption typically during device RUN mode, the LV domain consumption I DD (V DD_BV ) is thus limited to I DDMAX - I DD (V DD_HV ) i.e. 80 ma. Therefore, respecting the maximum power allowed as explained in Section 3.5.2, Package thermal characteristics, it is recommended to use this resistor only in the 125 C/5.5V operating corner as per the following guidelines: If I DD (V DD_BV ) < 80 ma, then no resistor is required. If 80 ma < I DD (V DD_BV ) < 90 ma, then 4 Ohm resistor can be used along with 14.7 µf decoupling. If I DD (V DD_BV ) > 90 ma, then 8 Ohm resistor can be used along with 33 µf decoupling. Using resistance in the range of 4-8 Ohm, the gain will be around 10-20% of total consumption on V DD_BV. For example, if 8 Ohm resistor is used, then power consumption when I DD (V DD_BV ) is 110 ma is equivalent to power consumption when I DD (V DD_BV ) is 90 ma (approximately) when resistor not used Package thermal characteristics Table 10. LQFP thermal characteristics 1 Symbol C Parameter Conditions 2 R θja CC D Thermal resistance, junction-toambient natural convection 4 Single-layer board 1s Four-layer board 2s2p Pin count 1 Thermal characteristics are targets based on simulation that are subject to change per device characterization. 2 V DD = 3.3 V ± 10% / 5.0 V ± 10%, T A = 40 to 125 C. 3 All values need to be confirmed during device validation. 4 Junction-to-ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets JEDEC specification for this package. When Greek letters are not available, the symbols are typed as R thja and R thjma. Value 3 Min Typ Max Freescale Semiconductor 17 Unit C/W

18 Table MAPBGA thermal characteristics 1 Symbol C Parameter Conditions Value Unit Power considerations The average chip-junction temperature, T J, in degrees Celsius, may be calculated using Equation 1: 18 R θja CC Thermal resistance, junction-to-am bient natural convection 2 1 Thermal characteristics are targets based on simulation that are subject to change per device characterization. 2 Junction-to-ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets JEDEC specification for this package. When Greek letters are not available, the symbols are typed as R thja and R thjma. T J = T A + (P D x R θja ) Eqn. 1 Where: T A is the ambient temperature in C. R θja is the package junction-to-ambient thermal resistance, in C/W. P D is the sum of P INT and P I/O (P D = P INT + P I/O ). P INT is the product of I DD and V DD, expressed in watts. This is the chip internal power. P I/O represents the power dissipation on input and output pins; user determined. Most of the time for the applications, P I/O < P INT and may be neglected. On the other hand, P I/O may be significant, if the device is configured to continuously drive external modules and/or memories. An approximate relationship between P D and T J (if P I/O is neglected) is given by: Therefore, solving equations 1 and 2: P D = K / (T J C) Eqn. 2 K = P D x (T A C) + R θja x P D 2 Eqn. 3 Where: K is a constant for the particular part, which may be determined from Equation 3 by measuring P D (at equilibrium) for a known T A. Using this value of K, the values of P D and T J may be obtained by solving equations 1 and 2 iteratively for any value of T A. 3.6 I/O pad electrical characteristics I/O pad types Single-layer board 1s Four-layer board 2s2p The device provides four main I/O pad types depending on the associated alternate functions: Slow pads - are the most common pads, providing a good compromise between transition time and low electromagnetic emission. Medium pads - provide transition fast enough for the serial communication channels with controlled current to reduce electromagnetic emission. TBD C/W Freescale Semiconductor

19 Fast pads - provide maximum speed. These are used for improved Nexus debugging capability. Input only pads - are associated with ADC channels and 32 khz low power external crystal oscillator providing low input leakage. Medium and Fast pads can use slow configuration to reduce electromagnetic emission, at the cost of reducing AC performance I/O input DC characteristics Table 12 provides input DC electrical characteristics as described in Figure 5. Figure 5. I/O input DC electrical characteristics definition Table 12. I/O input DC electrical characteristics Symbol C Parameter Conditions 1 Value 2 Unit Min Typ Max V IH V IL V HYS V DD V IH V IL PDIx = 1 (GPDI register of SIUL) PDIx = 0 V IN SR P Input high level CMOS (Schmitt Trigger) SR P Input low level CMOS (Schmitt Trigger) CC C Input hysteresis CMOS (Schmitt Trigger) 0.65V DD V DD +0.4 V V DD 0.1V DD Freescale Semiconductor 19 V HYS

20 Table 12. I/O input DC electrical characteristics (continued) 20 Symbol C Parameter Conditions 1 Value 2 Unit Min Typ Max I LKG CC P Digital input leakage No injection T A = 40 C 2 na P on adjacent pin T A = 25 C 2 D T A = 105 C W FI P T A = 125 C SR P Width of input pulse surely filtered 40 ns by analog filter 3 W NFI SR P Width of input pulse surely not 1000 ns filtered by analog filter 3 1 V DD = 3.3 V ± 10% / 5.0 V ± 10%, T A = 40 to 125 C, unless otherwise specified 2 All values need to be confirmed during device validation. 3 Analog filters are available on all wakeup lines. Freescale Semiconductor

21 3.6.3 I/O output DC characteristics The following tables provide DC characteristics for bidirectional pads: Table 13 provides weak pull figures. Both pull-up and pull-down resistances are supported. Table 15 provides output driver characteristics for I/O pads when in SLOW configuration. Table 16 provides output driver characteristics for I/O pads when in MEDIUM configuration. Table 14 provides output driver characteristics for I/O pads when in FAST configuration. Table 13. I/O pull-up/pull-down DC electrical characteristics Symbol C Parameter Conditions 1 I WPU CC P C Weak pull-up current absolute value V IN = V IL, V DD = 5.0 V ± 10% P V IN = V IL, V DD = 3.3 V ± 10% I WPD CC P C Weak pull-down current absolute value V IN = V IH, V DD = 5.0 V ± 10% P V IN = V IH, V DD = 3.3 V ± 10% PAD3V5V = 0 PAD3V5V = 1 2 PAD3V5V = 1 PAD3V5V = 0 PAD3V5V = 1 PAD3V5V = 1 1 V DD = 3.3 V ± 10% / 5.0 V ± 10%, T A = 40 to 125 C, unless otherwise specified. 2 The configuration PAD3V5 = 1 when V DD = 5 V is only a transient configuration during power-up. All pads but RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state. Freescale Semiconductor 21 Value Min Typ Max Unit µa µa

22 Table 14. FAST configuration output buffer electrical characteristics 22 Symbol C Parameter Conditions 1 Value V OH CC P Output high level FAST configurati on V OL CC P Output low level FAST configurati on Push Pull I OH = 14mA, V DD = 5.0 V ± 10%, PAD3V5V = 0 (recomme nded) C I OH = 7mA, V DD = 5.0 V ± 10%, PAD3V5V = 1 2 C I OH = 11mA, V DD = 3.3 V ± 10%, PAD3V5V = 1 (recomme nded) C Push Pull I OL = 14mA, V DD = 5.0 V ± 10%, PAD3V5V = 0 (recomme nded) I OL = 7mA, V DD = 5.0 V ± 10%, PAD3V5V = 1 2 C I OL = 11mA, V DD = 3.3 V ± 10%, PAD3V5V = 1 (recomme nded) Min Typ Max Unit 0.8V DD V 0.8V DD V DD V DD V 0.1V DD 0.5 Freescale Semiconductor

23 1 V DD = 3.3 V ± 10% / 5.0 V ± 10%, T A = 40 to 125 C, unless otherwise specified 2 The configuration PAD3V5 = 1 when V DD = 5 V is only a transient configuration during power-up. All pads but RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state Output pin transition times Table 15. Output pin transition times Symbol C Parameter Conditions 1 Value 2 Unit Min Typ Max T tr CC D Output transition time output pin 3 SLOW configurati on C L = 25 pf T C L = 50 pf D C L = 100 pf D C L = 25 pf T C L = 50 pf D C L = 100 pf T tr CC D Output transition time output pin 3 MEDIUM configurati on C L = 25 pf T C L = 50 pf D C L = 100 pf D C L = 25 pf T C L = 50 pf D C L = 100 pf V DD = 5.0 V ± 10%, PAD3V5V = 0 V DD = 3.3 V ± 10%, PAD3V5V = 1 V DD = 5.0 V ± 10%, PAD3V5V = 0 SIUL.PCR x.src = 1 V DD = 3.3 V ± 10%, PAD3V5V = 1 SIUL.PCR x.src = 1 50 ns ns Freescale Semiconductor 23

24 Table 15. Output pin transition times (continued) I/O pad current specification The I/O pads are distributed across the I/O supply segment. Each I/O supply segment is associated to a V DD /V SS supply pair as described in Table 16. Table 17 provides I/O consumption figures. In order to ensure device reliability, the average current of the I/O on a single segment should remain below the I AVGSEG maximum value. In order to ensure device functionality, the sum of the dynamic and static current of the I/O on a single segment should remain below the I DYNSEG maximum value. 24 T tr CC D Output transition time output pin 3 FAST configurati on C L = 25 pf C L = 50 pf C L = 100 pf C L = 25 pf C L = 50 pf C L = 100 pf V DD = 5.0 V ± 10%, PAD3V5V = 0 V DD = 3.3 V ± 10%, PAD3V5V = 1 1 V DD = 3.3 V ± 10% / 5.0 V ± 10%, T A = 40 to 125 C, unless otherwise specified 2 All values need to be confirmed during device validation. 3 C L includes device and package capacitances (C PKG < 5 pf). Package 208 MAPBGA 1 Symbol C Parameter Conditions 1 Value 2 Unit Min Typ Max 176 LQFP pin7 pin27 pin28 pin LQFP pin20 pin LQFP pin16 pin35 Table 16. I/O supply segments Supply segment 4 ns Equivalent to 176 LQFP segment pad distribution MCKO MDOn /MSEO pin51 pin99 pin37 pin69 pin59 pin85 pin100 pin122 pin70 pin83 pin86 pin123 pin 123 pin19 pin84 pin MAPBGA available only as development package for Nexus2+ pin124 pin150 pin151 pin6 Freescale Semiconductor

25 Table 17. I/O consumption Symbol C Parameter Conditions 1 Value 2 Unit Min Typ Max I DYNSEG SR D Sum of all the dynamic and static I/O current within a supply segment I SWTSLW,3 CC D Dynamic I/O current for SLOW configurati on I 3 SWTMED CC D Dynamic I/O current for MEDIUM configurati on I SWTFST 3 CC D Dynamic I/O current for FAST configurati on V DD = 5.0 V ± 10%, PAD3V5V = 0 V DD = 3.3 V ± 10%, PAD3V5V = 1 C L = 25 pf C L = 25 pf C L = 25 pf V DD = 5.0 V ± 10%, PAD3V5V = 0 V DD = 3.3 V ± 10%, PAD3V5V = 1 V DD = 5.0 V ± 10%, PAD3V5V = 0 V DD = 3.3 V ± 10%, PAD3V5V = 1 V DD = 5.0 V ± 10%, PAD3V5V = 0 V DD = 3.3 V ± 10%, PAD3V5V = ma ma ma ma 50 Freescale Semiconductor 25

26 Table 17. I/O consumption (continued) 26 Symbol C Parameter Conditions 1 Value 2 Unit Min Typ Max I RMSSLW CC D Root medium square I/O current for SLOW configurati on I RMSMED CC D Root medium square I/O current for MEDIUM configurati on C L = 25 pf, 2 MHz C L = 25 pf, 4 MHz C L = 100 pf, 2 MHz C L = 25 pf, 2 MHz C L = 25 pf, 4 MHz C L = 100 pf, 2 MHz C L = 25 pf, 13 MHz C L = 25 pf, 40 MHz C L = 100 pf, 13 MHz C L = 25 pf, 13 MHz C L = 25 pf, 40 MHz C L = 100 pf, 13 MHz V DD = 5.0 V ± 10%, PAD3V5V = 0 V DD = 3.3 V ± 10%, PAD3V5V = 1 V DD = 5.0 V ± 10%, PAD3V5V = 0 V DD = 3.3 V ± 10%, PAD3V5V = ma ma Freescale Semiconductor

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