AN937 APPLICATION NOTE

Transcription

1 AN937 APPLICATION NOTE DESIGNING WITH L497,.5A HIGH EFFICIENCY DC-DC CONVERTER INTRODUCTION The L497 is a.5a monolihic dc-dc converer, sep- down, operaing a fix frequency coninuous mode. I is realised in BCD60 II echnology, and i is available in wo plasic packages, DIP8 and SO6L. One direc fixed oupu volage a 3.3V ±% is available, adjusable for higher oupu volage values, ill 40V, by an exernal volage divider. The operaing inpu supply volage ranges from 8V o 55V, while he absolue value, wih no load, is 60V. New inernal design soluions and superior echnology performance allow o generae a device wih improved efficiency in all he operaing condiions and wih reduced EMI due o an innovaive inernal driving circui, and reduced exernal componen couns. While inernal limiing curren and hermal shudown are oday considered sandard proecion funcions, mandaory for a safe load supply, oscillaor wih volage feedforward improves line regulaion and overall conrol loop. Sof-sar avoids oupu overvolages a urn-on, while, shoring his pin o ground, he device is compleely disabled, going ino zero consumpion sae. Figure.. AN937/0505 Rev. 4 /9

2 2 DEVICE DESCRIPTION For a beer undersanding of he device and i s working principle, a shor descripion of he main building blocks is given here below, wih packaging opions and complee block diagram. Figure 2 show s he wo packaging opions, wih he pin funcion assignmens. Figure 2. Pins Connecions. N.C. 6 N.C. GND 8 FB GND 2 5 N.C. SS_INH 2 7 COMP SS_INH 3 4 FB OSC 3 6 BOOT OSC 4 3 COMP OUT 4 5 VCC OUT 5 2 BOOT D97IN595 OUT 6 VCC N.C. 7 0 N.C. N.C. 8 9 N.C. DIP8 D97IN596 SO6L Figure 3. Block Diagram. 5 VCC SS_INH COMP FB V THERMAL SHUTDOWN INHIBIT E/A OSCILLATOR VOLTAGES MONITOR SOFTSTART PWM INTERNAL INTERNAL 3.3V REFERENCE SUPPLY 5.V R S Q DRIVE CBOOT CHARGE CBOOT CHARGE AT LIGHT LOADS 6 BOOT 3 4 OSC GND OUT D97IN594 3 POWER SUPPLY, UVLO AND VOLTAGE REFERENCE. The device is provided wih an inernal sabilised power supply (of abou 2V yp.) ha powers he analog and digial conrol blocks and he boosrap secion. From his preregulaor, a 3.3V reference volage ±2%, is inernally available. 2/9

3 3. Oscillaor and volage feedforward Jus one pin is necessary o implemen he oscillaor funcion, wih inheren volage feedforward. Figure 4. Oscillaor Inernal Circui V CC R OSC TO PWM COMPARATOR Osc 5R - + CLOCK C OSC Q R Q 2 V D97IN655A A resisor Rosc and a capacior Cosc conneced as shown in fig. 4, allow he seing of he desired swiching frequency in agreemen wih he below formula: F SW = ( R oasc C osc )In C osc Where F sw is in khz, R osc in KΩ and C osc in nf. The oscillaor capacior, C osc, is discharged by an inernal mos ransisor of 00Ω of R dson (Q) and during his period he inernal hreshold is seed a V by a second mos, Q2. When he oscillaor volage capacior reaches he V hreshold he oupu comparaor urn-off he mos Q and urn-on he mos Q2, resaring he C osc charging. The oscillaor block, shown in fig. 4, generaes a sawooh wave signal ha ses he swiching frequency of he sysem. This signal, compared wih he oupu of he error amplifier, generaes he PWM signal ha will modulae he conducion ime of he power oupu sage. The way he oscillaor has been inegraed,does no require addiional exernal componens o benefi of he volage feedforward funcion. The oscillaor peak-o-valley volage is proporional o he supply volage, and he volage feedforward is operaive from 8V o 55V of inpu supply. V CC V osc = Also he V/ of he sawooh is direcly proporional o he supply volage. As Vcc increases, he Ton ime of he power ransisor decreases in such a way o provide o he chocke, and finally also he load, he produc Vol. sec consan. Fig 6 show how he ducy cycle varies as a resul of he change on he V/ of he sawooh wih he Vcc. The oupu of he error amplifier doesn change o mainain he oupu volage consan and in regulaion. Wih his funcion on board, he oupu response ime is greaely reduced in presence of an abrup change on he supply volage, and he oupu ripple volage a he mains frequency is greaely reduced oo. 3/9

4 Figure 5. Device swiching frequency vs Rosc and Cosc. fsw (KHz) 500 Tamb=25 C D97IN nF.2nF 2.2nF 3.3nF nF 4.7nF R2(KΩ) Figure 6. Volage Feedforward Funcion. V Vi=30V Vi=5V Vc V2-3 Vi=30V Vi=5V D97IN684 Figure 7. Maximum Duy Cycle vs. Rosc and Cosc as parameer. Dmax 5.3nF D97IN nF 2.2nF.2nF 0.8nF ROSC(KΩ) 4/9

5 In fac, he slope of he ramp is modulaed by he inpu ripple volage, generally presen in he order of some ens of Vol, for boh off-line and dc-dc converers using mains ransformers. The charge and discharge ime is approximable o: Tch = R osc C osc In Tdis = 00 C osc The maximum duy cycle is a funcion of Tch, Tdis and an inernal delay and is represened by he equaion: and is rapresened in figure 7: Dmax = R osc C osc In R osc C osc In C osc 3.2 Curren proecion The L497 has wo curren limi levels, pulse by pulse and hiccup modes. Increasing he oupu curren ill he pulse by pulse limiing curren reshold (Ih yp. value of 2.5A) he conroller reduces he on-ime ill he value of T B = 300ns ha is a blanking ime in which he curren limi proecion does no rigger. This minimun ime is necessary o avoid undesirable inervenion of he proecion due o he spike curren generaed during he recovery ime of he freewheeling diode. In his condiion, because of his fixed balnking ime, he oupu curren is given by: [ V CC T B F SW V f ( T B F SW )] I max = [ R O + ( R D + R L )( T B F SW ) + ( R dson + R L )T B F SW ] In fig 8, he pulse by pulse proecion is sufficien o limi he curren. In fig 9 he pulse by pulse proecion is no more effecive o limi he curren due o he minimun Ton fixed by he blanking ime TB, and he hiccup proecion inervenes because he oupu peak curren reachs he relaive hreshold. A he pulse by pulse inervenion (poin A) he oupu volage drops because of he Ton reducion, and he curren is almos consan. Going versus he shor circui condiion, he curren is only limied by he series resisances RD and RL (see relaion above) and could reach he hiccup reshold (poin B), se 20% higher han he pulse by pulse. Once he hiccup limiing curren is operaing, in oupu shor circui condiion, he delivered average oupu curren decreases dramaically a very low values (poin C). Figure 8. Oupu Characerisics Figure 9. Oupu Characerisics V O V O A A B C D98IN908A 2.5A 3A I O D97IN A 3A I O 5/9

6 Figure 0. Curren Limiing Inernal Schemaic Circui. OSC S Q R V CC V Th V Th OSC PWM THERMAL HICCUP SOFT START LATCH S Q 2V OUT UNDERVOLTAGE R VFB VREF C SS D97IN658 - Figure. Oupu curren and sof sar volage 5.4A 4.5A Fig. 0 shows he inernal curren limiing circuiry. Vh is he pulse by pulse while Vh2 is he hiccup hreshold. The sense resisor is in series wih a small mos realised as a pariion of he main DMOS. The Vh2 comparaor (20% higher han Vh) ses he sof sar lach, iniialising he discharge of he sof sar capacior wih a consan curren (abou 22mA). Reaching abou 0.4V, he valley comparaor reses he sof sar lach, resaring a new recharge cycle. Fig. Shows he ypical waveforms of he curren in he oupu inducor and he sof sar volage (pin 2). During he recharging of he sof sar capacior, he Ton increases gradually and, if he shor circui is sill presen, when Ton>TB and he oupu peak curren reachs he hreshold, he hiccup proecion inervenes again. So, he value of he sof sar capacior mus no be oo high (in his case he Ton increases slowly hus aking much ime o reach he TB value) o avoid ha during he sof sar slope, he curren exceeds he limi before he proecion acivaion. The following diagrams of Fig2 and Fig3 show he maximum allowed sof-sar capacior as a funcion of he inpu volage, inducor value and swiching frequency. A minimun value of he 6/9

7 sof sar capaciance is necessary o guaranee, in shor circui condiion, he funcionaliy of he limiing curren circuiry. Infac, wih a capacior oo small, he frequency of he curren peaks (see figure ) is high and he mean curren value in shor circui increases. Example: for a maximum inpu volage of 55V a 00kHz, wih an inducor of 260mH, i is possible o use a sof sar capacior lower han 470mF. Wih such a value, he sof sar ime (see fig. 6) of abou 0ms for an oupu volage of 5V Figure 2. Maximum sof sar capaciance wih f sw = 00kHz Figure 3. Maximum sof sar capaciance wih f sw = 200kHz L (µh) 400 fsw=00khz 680nF D97IN nF L (µh) 300 fsw=200khz D97IN746 56nF 47nF nF nF nF 00nF 00 22nF V CCmax (V) V CC max(v) 3.3 Sof Sar and Inhibi Funcions The sof sar and he inhibi funcions are realised using one pin only, pin2. Sof-sar is requesed o inizialise all inernal funcions wih a correc sar-up of he sysem wihou oversressing he power sage, avoiding he inervenion of he curren proecion, and having an oupu volage rising smoohly wihou oupu overshoos. A Vcc Turn-on or having had an inervenion of inhibi funcion, an iniial 5µA inernal curren generaor sars o charge he sof-sar capacior, from 0V o abou.8v. From his hysereic hreshold, a 40µA curren generaor is acivaed, puing in off sae he previous generaor. Figure 4. Sof-Sar and inhibi funcions Inernal Circui 2V 40µA S 5µA S4 Comp + -.2V.8V UNDERVOLTAGE PROT. HICCUP PROT. S Q SS_INH THERMAL PROT. R Comp2 0µA KΩ C SS - S2 S3 +.3V D97IN808A 7/9

8 A his poin, he oupu PWM sars, iniiaing he rising phase of he oupu volage. The sof-sar capacior is quickly discharged in case of: Thermal proecion inervenion Hiccup limiing curren condiion Supply volage lower han UVLO off hreshold. The sof-sar and inhibi schemaic diagram is shown in fig 4. A device urn-on, he sof-sar capacior has no charge, wih 0V a is erminals. From 0V o.8v, swich S3 is opened and S4 is closed. Sof-sar capacior is charged wih 5µA. A.8V, comp change he oupu saus, opening S4 and closing S3, and he device sars o generae he PWM signal, rising smohly he oupu volage. Till his momen, S2 is opened, S closed. By closing S3, he sof-sar capacior is charged wih 40µA reaching is sauraion volage. This procedure is repeaed a each Vcc urn-on. Figure 5. Timing Diagram in Inhibi, overcurren and urn off condiion INHIBIT OVER-CURRENT TURN-OFF V SS/INH.8V.3V.2V I C I LIM I LIM I O PWM V O V CC D97IN8 UVLO OFF 8/9

9 Figure 6. Figure b. Sar up sequence. V CC UVLO ON V SS/INH.8V I C PWM V O 2 D97IN82 Turning Vcc off, he sof-sar capacior is discharged wih a consan 0µA (S2 closed, S3 closed, S and S4 open), from he momen when Vcc is crossing he UVLO off hreshold. The final discharge value is.2v. In case of he Css is discharged using an exernal grounded elemen when he volage a Css reaches he hreshold of.3v Comp2 reses he flip flop, S is closed, S2 is opened and he 40mA curren generaor is acivaed. The exernal swich, sinking some ma, discharges he sof-sar under he.2v Comp hreshold, opening S3 and closing S4. A his poin he device is in disable, sourcing only 5µA hrough pin 2. When he exernal grounding elemen is removed, he device resars charging he sof sar capaciance, iniially, wih 5µA ill he volage reaches he.8v hreshold and Comp connecs he 40µA charging curren generaor. In case of hermal shudown or overcurren proecion inervenion he power is urned off and he flip flop urns off S2 and urns on S. The sof-sar is discharged ill he volage reaches he.3v hreshold, and Comp2 reses he flip flop. S is closed, S2 is opened and he sof-sar capaciance is charged again. Fig 5 shows he sysems signals during Inhibi, overcurren and Vcc urn off. and 2 can be calculaed by he following equaions: = 0.36 Css; 2 V O = Ich D C ss max where Dmax is 0.95, Css is in µf and Ich is in µa. Sof-sar ime (2) versus oupu volage and Css is shown in Fig7. Thanks o he volage feedforward, he sar-up ime (2) is no affeced by he inpu volage. Fig8 shows he oupu volage sar-up using differen sof-sar capaciance values: I is mandaory a minimum capacior value of 22nF. The pin 2 canno be lef open. 9/9

10 Figure 7. Sof sar ime (2) vs Vo and Css Figure 8. Oupu rising volage wih Css 56nF, 00nF, 220nF.- ss (ms) D97IN µf nF 330nF 220nF 00nF V O (V) 3.4 Feedback disconnecion In case of feedback disconnecion, he duy cycle increases versus he max allowed value bringing he oupu volage close o he inpu supply. This condiion could desroy he load. To avoid his dangerous condiion, he device is forcing a lile curren (.4µA ypical) ou of he pin 8 (E/A Feedback). If he feedback is disconneced, open loop, and he impedance a pin 8 is higher han 3.5MΩ, he volage a his pin goes higher han he inernal reference volage locaed on he non-invering error amplifier inpu, and urns-off he power device. 3.5 Zero load In normal operaion, he oupu regulaion is also guaraneed because he boosrap capacior is recharged, cycle by cycle, by means of he energy flowing ino he choke. Under ligh load condiions, his opology ends o operae in burs mode, wih random repeiion rae of he burss. An inernal new funcion makes his device capable of keeping he oupu volage in full regulaion wih ma of load curren only. Beween ma and 500µA, he oupu is kep in regulaion up o 8% above he nominal value. Here he circuiry providing he conrol : ) a comparaor locaed on he boosrap secion is sensing he boosrap volage; when his is lower han 5V, he inernal power VDMOS is forced ON for one cycle and OFF for he nex.. 2) during his operaion mode, i.e. 500µA of load curren, he E/A conrol is los. To avoid oupu overvolages, a comparaor wih one inpu conneced o pin 8, and he second inpu conneced o a hreshold 8% higher ha nominal oupu, urns OFF he inernal power device he oupu is reaching ha hreshold. When he oupu curren, or raher, he curren flowing ino he choke, is lower han 500µA, ha is also he consumpion of he boosrap secion, he oupu volage sars o increase, approaching he supply volage. 3.6 Oupu Overvolage Proecion (OVP) The oupu overvolage proecion, OVP, is realized by using an inernal comparaor, which inpu is conneced o pin 8, he feedback, ha urns-off he power sage when he OVP hreshold is reached. This hreshold is ypically 8% higher han he feedback volage. 0/9

11 When a volage divider is requesed for adjusing he oupu volage, he OVP inervenion will be seed a: where Ra is he resisor conneced o he oupu. 3.7 Power Sage The power sage is realized by a N-channel D-mos ransisor wih a Vdss in excess of 60V and yp Rdson of 290mOhm (measured a he device pins). Minimising he Rdson, means also minimise he conducion losses. Bu also he swiching losses have o be aken ino consideraion. mainly for he wo following reasons: a) hey are affecing he sysem efficiency and he device power dissipaion b) because hey generae EMI. 3.8 TURN - ON A urn-on of he power elemen, or beer, he rise ime of he curren(di/d) a urn-on is he mos criical parameer o compromise. A a firs approach, i looks ha faser is he rise ime and lower are he urn-on losses. I s no compleely rue. There is a limi, and i s inroduce by he recovery ime of he recirculaion diode. Above his limi, abou 00A/usec, only disadvanages are obained: - urn-on overcurren is decreasing efficiency and sysem reliabiliy 2- big EMI encrease. The L497 has been developed wih a special focus on his dynamic area. An innovaive and proprieary gae driver, wih wo differen imings, has been inroduced. When he diode reverse volage is reaching abou 3V, he gae is sourced wih low curren (see fig 9) o assure he complee recovery of he diode wihou generaing unwaned exra peak currens and noise. Afer his hreshold, he gae drive curren is quickly increased, producing a fas rise ime ill he peak curren, so mainaining he efficiency very high. Figure 9. Turn on and Turn off (pin 2, 3) ( Ra + Rb) V OVP =.08 V fb Rb /9

12 Figure 20. Power sage inernal circui C SS Q 3 Q V i I I 2 S C SS Q 2 S RS L + Q 4 Q 5 from PWM LATCH D C V O - I 4 I 5 I 3 DELAY D97IN TURN - OFF The urn-off behavior, is shown a Fig. 9. Fig. 20 shows he deails of he inernal power sage and driver, where a Q2 is demanded he urn-off of he power swich, S. 4 TYPICAL APPLICATION. Fig. 2 shows he ypical applicaion circui, where he inpu supply volage, Vcc, can range from 8 o 55V operaing, and he oupu volage adjusable from 3.3V o 40V. The seleced componens, and in paricular inpu and oupu capaciors, are able o susain he device volage raings, and he corresponding RMS currens. 4. Elecrical Specificaion Inpu Volage Range 8V - 55V Oupu Volage 5.V ±3% (Line, Load and Thermal) Oupu Ripple 20mV Oupu Curren range ma -.5A Max Oupu Ripple curren 5% Iomax Curren limi 2.5A Swiching frequency 00kHz Targe Efficiency Vi = 505V 0.5A Vi = 2V 2/9

13 Figure 2. Applicaion Circui Vin=8V o 55V C 220µF 63V C 7 220nF R 20K C 2 2.7nF L L 220µH (7720) V O =5.V/.5A R 3 C 5 00nF C 4 22nF R 2 9.K C 6 00nF D STPS 3L60U C 8 330µF R 4 D97IN749B C=220µF/63V EKE C2=2.7nF C5=00nF C6=00nF C7=220nF/63V C8=330µF/35V CG Sanyo L=220µH KoolMu Turns - 0.5mm R=20K R2=9.K D=STPS3L60U L497 V O (V) R3(KΩ) R4(KΩ) Inpu Capacior The inpu capacior has o be able o suppor he max inpu operaing volage of he device and he max rms inpu curren. The inpu curren is squared and he qualiy of hese capaciors has o be very high o minimise is power dissipaion generaed by he inernal ESR, improving he sysem reliabiliy. Moreover, inpu capaciors are also affecing he sysem efficiency. The max Irms curren flowing hrough he inpu capaciors is: I rms I O D 2 D2 D 2 = η η 2 where η is he expeced sysem efficiency, D is he duy cycle and Io he oupu dc curren. This funcion reaches he maximum value a D = 0.5 and he equivalen rms curren is equal o Io/2. The following diagram Fig. 23 is he graphical rappresenaion of he above equaion, wih an esimaed efficiency of 85%, a differen oupu currens. The maximum and minimum duy cycles are: V O + V f V O + V f D max = = 0.66 D V ccmin + V max = = 0. f V ccmax + V f where Vf is he freewheeling diode forward volage. This formula is no aking ino accoun he power mos Rdson, considering negligible he inheren volage drop, respec inpu and oupu volages. A full load,.5a, and D=0.5, he rms capacior curren o be susained is of 0.75A. The seleced 220µF/63V Rodersain is able o suppor his curren. 3/9

14 Figure 22. Efficiency vs Oupu Curren η (%) V CC =24V V CC =2V V CC =48V V CC =8V D97IN738 Figure 23. Inpu Capaciance rms curren vs. duy cycle I RMS I O =.5A I O =.2A I O =A D97IN80 70 fsw=00khz V O =5.V 0.25 I O =0.5A 65 I O =0.2A I O (A) D 4.3 Inducor Selecion The inducor ripple curren is fixed a 0% of Iomax and is 0.5A, he inducor needed is: ( D min ) L = ( V O + V f ) = 30µH I O f sw Eq The L. I O 2 is 0.58 and he size core chose is 7720 (25µ) Magneics KoolMµ maerial and are wiring 65Turns. A full load he magneising force is abou 25 Oersed, he inducance value is reduced a abou L = 220µH and he ripple curren increases a 0.24A (6% Iomax). I is possible o graficae he Eq as a funcion of Vo and Vinmax a 00kHz and 200kHz (see Figs. 24 and 25 ). These curves are useful o define he inducor value immediaely. Example: Wih a maximum inpu volage of 5V a 00kHz, fixed he curve () in Fig24 and wih an oupu volage of 5V he inducor needed is 220µH. Figure 24. Inducor needed as a funcion of maximum inpu volage and oupu volage a fsw=00khz Figure 25. Inducor needed as a funcion of maximum inpu volage and oupu volage a fsw=200khz L O (µh) 700 VCCmax= D97IN803 L O (µh) 350 VCCmax= D97IN () 30V 50 30V 200 5V 25V 20V 35V 40V 00 5V 25V 20V 35V 40V V O (V) V O (V) 4/9

15 4.4 Core Losses Core losses are proporional o he magneic flux swing ino he core maerial. To evaluae he flux swing is used he following formula: 4 L I O 0 B = = 423Gauss N O A le where Ale is he core cross secion [m 2 ]. The choosen core maerial family has an empirical equaion o calculae he losses: P L B 2.5 = f sw VL 0 2 = 4mW Where B is in KGauss, fsw in khz and V L is he core volume in cm 3. The core increasing emperaure is: T P I = = 7 C Oupu Capaciors The selecion of Cou is driven by he oupu ripple volage required, % of Vo. This is defined by he oupu capaciance ESR and wih he maximum ripple curren (0.24A) he maximum ESR is: ESR V O 0.05 = = = 22mΩ I L 0.24 The seleced capaciance is 330µF/35V CG Sanyo wih ESR = 86mΩ and he ripple volage is 0.40% of V o (20mV). The drop due o a fas load variaion of A produce an oupu drop of: ESR I o = 86mV ha is he.6% of he oupu volage. Oupu capaciance has o suppor a load ransien unil he inducor curren reaches he increased curren. The oupu drop during an oupu curren variaion is: ( I O ) 2 L O V O = C O ( V inmin D max V O ) Eq 2 where I o is he load curren load variaion 0.5A o.5a, D max is he maximum duy cycle, 95%, V o is 5.V, L o is 220µH. Equaion 2, normalized a Vo, is represened in he following diagram, Fig. 26, as a funcion of he minimum inpu volage. These curves are rapresened for differen oupu capacior 00µF, 220µF, 2x220µF, 3x330µF. 4.6 Compensaion Nework The complee conroll loop block diagram is shown in fig. 27. a ransfer funcions described are: 5/9

16 Figure 26. Oupu drop vs minimum inpu volage Figure 27. Block diagram compensaion loop V O V O D97IN802A V REF + - A(s) Vc/Vc LC V O 0.03 α D97IN µF Figure 28. Error Amplifier Compensaion Circui x 330µF 2 x 220µF 220µF gm Ro Cc Rc Co A vo =g m R o V INmin D97IN698 Figure 29. Oupu Filer L Cou Resr D97IN Error amplifier and compensaion block C o is he parallel beween he oupu and he exernal capaciance of he Error Amplifier oupu impedence. Rc and Cc are he compensaion values. 4.8 LC Filer As ( ) A VO ( + s R c C c ) = s 2 R o C o R c C c + s ( R o C c + R o C o + R c C c ) PWM Gain + R esr C ou s A os ( ) = L C ou s 2 + R esr s + V CC V CC = V c V CC where Vc is he peak o peak sawooh oscillaor. 6/9

17 4.0Volage divider α = R R3 + R4 The Error Amplifier basic characerisics are: Ro =.2MΩ Avo = 60dB Co = 220pF The poles and zeros value are: F o = = 2 πr esr C ou 2 π = 5.6KHz F p = = = 590Hz 2 π L C ou 2 π F ocomp = = 2 π R c C c 2 π = 795Hz F p = = 2 π R o C c 2 π = 6.02Hz F p2 = = 2 π R c C o 2 π = 80KHz The compensaion is realized choosing he Focomp nearly he frequency of he double pole due o he LC filer. Using a compensaion nework wih R= 9.K, C6 = 22nF and C5 = 220pF obain he Gain and Phase Bode plo of Figg Is possible o omi C5 because does no influence he sysem sabiliy bu is useful only o reduce he noise. The cu off frequency and a phase margin are: Fc = 5KHz Phase margin = 2 Figure 30. Gain Bode open loop plo Fa (db) D97IN K 0K 00K f(hz) Figure 3. Phase Bode open loop plo φfa ( ) D97IN806A K 0K 00K f(hz) 7/9

18 5 REVISION HISTORY Table. Revision Hisory Dae Revision Descripion of Changes Ocober Firs Issue in EDOCS May Updaed he Layou look & feel. Changed name of he D on he fig. 2 8/9

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