3 * ESD5302N ESD5302N. Descriptions. Features. Applications. Order information. http//:
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1 2-Lines, Uni-directional, Ultra-low Capacitance Transient Voltage Suppressors http//: Descriptions The is an ultra-low capacitance TVS (Transient Voltage Suppressor) array designed to protect high speed data interfaces. It has been specifically designed to protect sensitive electronic components which are connected to data and transmission lines from over-stress caused by ESD (Electrostatic Discharge). The incorporates two pairs of ultra-low capacitance steering diodes plus a TVS diode. DFN6-3L (Bottom View) 2 The may be used to provide ESD protection up to ±20kV (contact and air discharge) according to IEC60-4-2, and withstand peak pulse current up to 4A (8/20μs) according to IEC The is available in DFN6-3L package. Standard products are Pb-free and Halogen-free. Features 1 Circuit diagram Stand-off voltage: 5V max. Transient protection for each line according to IEC (ESD): ±20kV (contact and air discharge) IEC (EFT): 40A (5/50ns) IEC (surge): 4A (8/20μs) Ultra-low capacitance: C J = 0.4pF typ. Ultra-low leakage current: I R <1nA typ. Low clamping voltage: V CL = 17. I PP = 16A(TLP) Solid-state silicon technology * 3 3 = Device code * = Month code ( A~Z) Marking (Top View) Applications USB 2.0 and USB 3.0 HDMI 1.3 and HDMI 1.4 SATA and esata DVI IEEE 1394 PCI Express Portable Electronics and Notebooks Order information Device Package Shipping -3/TR DFN6-3L 00/Tape&Reel Will Semiconductor Ltd. 1 Revision 1.5, 2014//16
2 Absolute maximum ratings Parameter Symbol Rating Unit Peak pulse power (t p = 8/20μs) P pk 60 W Peak pulse current (t p = 8/20μs) I PP 4 A ESD according to IEC air discharge V ESD ESD according to IEC contact discharge ±20 Operation junction temperature T J 125 Lead temperature T L 260 Storage temperature T STG -55~150 ±20 kv o C o C o C Electrical characteristics (T A = 25 o C, unless otherwise noted) Parameter Symbol Condition Min. Typ. Max. Unit Reverse maximum working voltage V RWM 5.0 V Reverse leakage current I R V RWM = 5V <1 na Reverse breakdown voltage V BR I T = 1mA V Forward voltage V F I T = ma V Clamping voltage 1) V CL I PP = 16A, t p = ns 17.5 V Dynamic resistance 1) R DYN 0.53 Ω Clamping voltage 2) Junction capacitance V CL C J I PP = 1A, t p = 8/20μs 11 V I PP = 4A, t p = 8/20μs 15 V V R = 0V, f = 1MHz Pin1 or 2 to Pin pf V R = 0V, f = 1MHz Between Pin1 and Pin pf Notes: 1) TLP parameter: Z 0 = 50 Ω, t p = ns, t r = 2ns, averaging window from 60ns to 80ns. R DYN is calculated from 4A to 16A. 2) Non-repetitive current pulse, according to IEC Will Semiconductor Ltd. 2 Revision 1.5, 2014//16
3 Typical characteristics (T A = 25 o C, unless otherwise noted) Peak pulse current (%) T Time (µs) T 1 T 2 Front time: T 1 = 1.25 T = 8µs Time to half-value: T 2 = 20µs 8/20μs waveform per IEC Current (%) 90 30ns 60ns t t r = 0.7~1ns Time (ns) Contact discharge current waveform per IEC V C - Clamping voltage (V) 14 Pulse waveform: t p = 8/20µs 12 C J - Junction capacitance (pf) Pin1 or 2 to Pin3 Between Pin1 and Pin2 f = 1MHz I PP - Peak pulse current (A) Clamping voltage vs. Peak pulse current V R - Reverse voltage (V) Capacitance vs. Reveres voltage 0 Peak pulse power (W) Pulse time (µs) Non-repetitive peak pulse power vs. Pulse time % of Rated power T A - Ambient temperature ( o C) Power derating vs. Ambient temperature Will Semiconductor Ltd. 3 Revision 1.5, 2014//16
4 Typical characteristics (T A = 25 o C, unless otherwise noted) ESD clamping (+8kV contact discharge per IEC60-4-2) ESD clamping (-8kV contact discharge per IEC60-4-2) TLP current (A) TLP voltage (V) TLP Measurement Z 0 = 50 Ω t r = 2ns t p = ns Will Semiconductor Ltd. 4 Revision 1.5, 2014//16
5 Application Information The is designed to protect two high speed line against ESD. Fig1 is shown the connection and Fig2 is shown PCB Layout guide for USB interface ESD protection VBUS DM DP ID GND VBUS DM DP ID GND Fig1 Fig2 Will Semiconductor Ltd. 5 Revision 1.5, 2014//16
6 Package outline dimensions DFN6-3L Top View Bottom View Side View Symbol Dimensions in millimeter Min. Typ. Max. A A A REF D E b b L L e BSC e BSC Recommend land pattern (Unit: mm) Notes: This recommended land pattern is for reference purposes only. Please consult your manufacturing group to ensure your PCB design guidelines are met Will Semiconductor Ltd. 6 Revision 1.5, 2014//16
7 Tape and Reel Specification Symbol Dimensions in millimeter Min. Typ. Max. A B K F P W Will Semiconductor Ltd. 7 Revision 1.5, 2014//16
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More informationIn data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.
Important notice Dear Customer, On 7 February 2017 the former NXP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic
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More informationIn data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.
Important notice Dear Customer, On 7 February 207 the former NXP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic
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More informationIn data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.
Important notice Dear Customer, On 7 February 2017 the former NXP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic
More informationIn data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.
Important notice Dear Customer, On 7 February 2017 the former NXP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic
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