3-PHASE BRIDGE DRIVER

Transcription

1 Features Floating channel designed for bootstrap operation. Fully operational to +6 V Tolerant to negative transient voltage, dv/dt immune Gate drive supply range from 1 V to 2 V (IRS2136D/ IRS21368D),11.5 V to 2 V (IRS21362D), or 12 V to 2 V (IRS21363D/ IRS21365D/ IRS21366D/IRS21367D Undervoltage lockout for all channels Over-current shutdown turns off all six drivers Independent 3 half-bridge drivers Matched propagation delay for all channels Cross-conduction prevention logic bootstrap diode function Low side output out of phase with inputs. High side outputs out of phase (IRS213(6,63, 65, 66, 67, 68)D), or in phase (IRS21362D) with inputs 3.3 V logic compatible Lower di/dt gate drive for better noise immunity Externally programmable delay for automatic fault clear All parts are LEAD-FREE Description The IRS2136xD (J&S) are high voltage, high speed power MOSFET and IGBT driver with three independent high side and low side referenced output channels for 3-phase applications. Proprietary HVIC technology enables ruggedized monolithic construction. Logic inputs are compatible with CMOS or LSTTL outputs, down to 3.3 V logic. A current trip function which terminates all six outputs can be derived from an external current sense resistor. An enable function is available to terminate all six outputs IRS2136D/ IRS21362D/ IRS21363D/ RS21365D/ IRS21366D/ IRS21367D/ IRS21368D(J&S) PbF 3-PHASE BRIDGE Packages Part IRS2136D IRS21362D IRS21363D IRS21365D IRS21366D IRS21367D IRS21368D Input Logic HIN, LIN HIN, LIN 28-Lead SOIC HIN, LIN HIN, LIN Data Sheet No. PD6247 HIN, LIN 28-Lead PDIP 44-Lead PLCC w/o 12 Leads Applications: *Motor Control *Air Conditioners/ Washing Machines *General Purpose Inverters *Micro/Mini Inverter Drives Feature Comparison: IRS2136D/IRS21362D/IRS21363D/IRS21365D/IRS21366D/IRS21367D/IRS21368D HIN, LIN HIN, LIN Ton (typ.) 53 ns 53 ns 53 ns 53 ns 2 ns 2 ns 53 ns Toff (typ.) 53 ns 53 ns 53 ns 53 ns 2 ns 2 ns 53 ns VIH (typ.) 1.9 V 1.9 V 1.9 V 1.9 V 1.9 V 1.9 V 1.9 V VIL (typ.) 1. V 1. V 1. V 1. V 1. V 1. V 1. V Vitrip+.46 V.46 V.46 V 4.3 V.46 V 4.3 V 4.3 V UVCC/BS+ 8.9 V 1.4 V 11.1 V 11.1 V 11.1 V 11.1 V 8.9 V UVCC/BS- 8.2 V 9.4 V 1.9 V 1.9 V 1.9 V 1.9 V 8.2 V simultaneously. An open-drain signal is provided to indicate that an overcurrent or undervoltage shutdown has occurred. Overcurrent fault conditions are cleared automatically after a delay programmed externally via an RC network connected to the input. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. Propagation delays are matched to simplify use in high frequency applications. The floating channels can be used to drive N- channel power MOSFETs or IGBTs in the high side configuration which operates up to 6 volts. Typical Connection Vcc HIN 1,2,3 / HIN 1,2,3 LIN 1,2,3 Vcc HIN 1,2,3/ HIN 1,2,3 VB 1,2,3 LIN 1,2,3 HO 1,2,3 VS 1,2,3 Up to 6V (Refer to Lead Assignments for correct pin configuration). This diagram shows electrical connections only. Please refer to our Application Notes and Design Tips for proper circuit board layout. LO 1,2,3 VSS IRS213 (6, 62, 63, 65, 66, 67, 68)D TO LOAD GND 1

2 Absolute Maximum Ratings Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol Definition Min. Max. Units V S High side offset voltage V B 1,2,3-2 V B 1,2,3 +.3 V B High side floating supply voltage V HO1,2,3 High side floating output voltage V S1,2,3 -.3 V B 1,2,3 +.3 V CC Low side and logic fixed supply voltage V SS Logic ground V CC - 2 V CC +.3 V LO1,2,3 Low side output voltage -.3 V CC +.3 V IN Input voltage LIN, HIN,,, V SS -.3 V CC +.3 V FLT output voltage V SS -.3 V CC +.3 dv/dt Allowable offset voltage slew rate 5 V/ns P D (28 lead PDIP) 1.5 Package power dissipation (28 lead TA +25 C 1.6 (44 lead PLCC) 2. W Rth JA (28 lead PDIP) 83 Thermal resistance, junction to (28 lead SOIC) ambient 78 (44 lead PLCC) 63 C/W T J Junction temperature 15 T S Storage temperature T L Lead temperature (soldering, 1 seconds) 3 Recommended Operating Conditions The Input/Output logic-timing diagram is shown in figure 1. For proper operation the device should be used within the recommended conditions. All voltage parameters are absolute referenced to. The V S & V SS offset ratings are tested with all supplies biased at 15 V differential. Symbol Definition Min. Max. Units IRS213(6,68)D V S1,2,3 +1 V S1,2,3 + 2 V B1,2,3 High side floating supply voltage IRS21362D V S1,2, V S1,2,3 + 2 IRS213(6,63,65,66,67)D V S1,2,3 +12 V S1,2,3 + 2 V S 1,2,3 High side floating supply voltage Note 1 6 V CC Low side supply voltage IRS213(6,68)D 1 2 IRS21362D IRS213(6,63,65,66,67)D 12 2 V HO 1,2,3 High side output voltage V S1,2,3 V B1,2,3 V LO1,2,3 Low side output voltage V CC V SS Logic ground -5 5 V FLT output voltage V SS V CC V input voltage V SS V CC V C V Note 1: Logic operational for V S of -8 V to +6 V. Logic state held for V S of -8 to V BS. (Please refer to the Design Tip DT97-3 for more details). 2

3 Recommended Operating Conditions (cont.) The Input/Output logic-timing diagram is shown in figure 1. For proper operation the device should be used within the recom-mended conditions. All voltage parameters are absolute referenced to. The V S & V SS offset ratings are tested with all supplies biased at 15 V differential. Symbol Definition Min. Max. Units V input voltage V SS V SS +5 V IN Logic input voltage LIN / HIN IRS213(6,63,65,66,67,68)D V V SS V SS +5 LIN / HIN IRS21362D, T A Ambient temperature C Note 1: HIN, LIN, and the pin are internally clamped with a 5.2 V zener diode. Static Electrical Characteristics V BIAS (V CC,V BS1,2,3 ) = 15 V unless otherwise specified. The V IN, V TH and I IN parameters are referenced to V SS and are applicable to all six channels (HIN1,2,3 and LIN1,2,3). The V O and I O parameters are referenced to and V S1,2,3 and are applicable to the respective output leads: LO1,2,3 and HO1,2,3. Symbol Definition Min Typ Max Units Test Conditions Logic input voltage LIN1,2,3 / HIN1,2,3 V IH IRS213(6,63,65,66,67,68)D 2.5 Logic 1 input voltage LIN1,2,3 / HIN1,2,3 IRS21362D Logic 1 input Voltage LIN1,2,3, HIN1,2,3 IRS213(6,63,65,66,67,68)D V IL.8 Logic input voltage LIN1,2,3 / HIN1,2,3 IRS21362D V IN, TH+ Input positive going threshold 1.9 V IN, TH- Input negative going threshold 1 V,TH+ Enable positive going threshold 2.5 V,TH- Enable negative going threshold.8 V IT,TH+ (6,62,63,66) positive going threshold V IT,HYS (6,62,63,66) hysteresis.7 V IT,TH+ (65,67,68) positive going threshold V IT,HYS (65,67,68) hysteresis.15 V, TH+ positive going threshold 8 V, HYS hysteresis 3 V OH High level output voltage, V BIAS - V O Io = 2 ma V OL Low level output voltage, V O.4.6 Io = 2 ma V CCUV+ (6,68) V CC supply undervoltage positive going threshold V CCUV- (6,68) V CC supply undervoltage negative going threshold V CCUVHY (6,68) V CC supply undervoltage hysteresis.3.7 V BSUV+ (6,68) V BS supply undervoltage positive going threshold V BSUV- (6,68) V BS supply undervoltage negative going threshold V 3

4 Static Electrical Characteristics (cont.) V BIAS (V CC,V BS1,2,3 ) = 15 V unless otherwise specified. The V IN, V TH and I IN parameters are referenced to V SS and are applicable to all six channels (HIN1,2,3 and LIN1,2,3). The V O and I O parameters are referenced to and V S1,2,3 and are applicable to the respective output leads: LO1,2,3 and HO1,2,3. Test Symbol Definition Min Typ Max Units Conditions V BSUVHY (6,68) V BS supply undervoltage hysteresis.3.7 V CCUV+ (62) V CC supply undervoltage positive going threshold V CCUV- (62) V CC supply undervoltage negative going threshold V CCUVHY (62) V CC supply undervoltage hysteresis.5 1 V BSUV+ (62) V BS supply undervoltage positive going threshold. V BSUV- (62) V BS supply undervoltage negative going threshold V BSUVHY (62) V BS supply undervoltage hysteresis.5 1 V CCUV+ V CC supply undervoltage positive going V (63,65,66,67) threshold V CCUV- (63,65,66,67) V CC supply undervoltage negative going threshold V CCUVHY.2 V (63,65,66,67) CC supply undervoltage hysteresis V BSUV+ V BS supply undervoltage positive going (63,65,66,67) threshold V BSUV- (63,65,66,67) V BS supply undervoltage negative going threshold V BSUVHY.2 V (63,65,66,67) BS supply undervoltage hysteresis I LK Offset supply leakage current 5 µa V B =V S = 6 V I QBS Quiescent V BS supply current 7 12 all µa logic value I QCC Quiescent V CC supply current 3 4 all ma logic value V IN,CLAMP Input clamp voltage (HIN, LIN, and ) V Iin=1 µa I LIN+ (6,62,63,65) Input bias current (LOUT = HI) µa Vin=4 V I LIN- (6,62,63,65) Input bias current (LOUT = LO) 15 2 µa Vin= V I LIN+ (66,67,68) Input bias current (LOUT = HI) 3 µa Vin=4 V I LIN- (66,67,68) Input bias current (LOUT = LO) 3 µa Vin= V I HIN+ (6,63,65) Input bias current (HOUT = HI) µa Vin=4 V I HIN- (6,63,65) Input bias current (HOUT = LO) 15 2 µa Vin= V I HIN+ (62) Input bias current (HOUT = HI) 5 2 µa Vin=4 V I HIN- (62) Input bias current (HOUT = LO) 3 µa Vin= V I HIN+ (66,67,68) Input bias current (HOUT = HI) 3 µa Vin=4 V I HIN- (66,67,68) Input bias current (HOUT = LO) 3 µa Vin= V I + High input bias current 5 2 µa Vin=4 V I - Low input bias current 1 µa Vin= V I + High ABLE input bias current 5 2 µa Vin=4 V I - Low ABLE input bias current 1 µa Vin= V 1 Vrcin= V or input bias current µa 15 V I 4

5 Static Electrical Characteristics (cont.) V BIAS (V CC,V BS1,2,3 ) = 15 V unless otherwise specified. The V IN, V TH and I IN parameters are referenced to V SS and are applicable to all six channels (HIN1,2,3 and LIN1,2,3). The V O and I O parameters are referenced to and V S1,2,3 and are applicable to the respective output leads: LO1,2,3 and HO1,2,3. Symbol Definition Test Min Typ Max Units Conditions I O+ Output high short circuit pulsed current 12 2 ma Vo = V, PW 1 µs I O- Output low short circuit pulsed current ma Vo =15 V, PW 1 µs R on_ low on resistance 5 1 Ω I= 1.5 ma R on_ low on resistance 5 1 Ω I= 1.5 ma R bs Internal BS diode Ron 2 Ω Dynamic Electrical Characteristics Dynamic Electrical Characteristics V CC = V BS = V BIAS = 15 V, V S1,2,3 = V SS =, TA = 25 C and CL = 1 pf unless otherwise specified. Symbol Definition Test Min Typ Max Units Conditions t on Turn-on propagation delay t off Turn-off propagation delay t on (66,67) Turn-on propagation delay 2 t off (66,67) Turn-off propagation delay 2 V IN = V & 5 V t r Turn-on rise time t f Turn-off fall time 5 75 t ABLE low to output shutdown propagation V IN, V = V delay or 5 V t (66,67) ABLE low to output shutdown propagation delay 3 V IN, V = V or 5 V t to output shutdown propagation delay V =5 V t bl blanking time 4 V IN = V or 5 V V = 5 V t FLT to propagation delay ns V IN = V or 5 V V = 5 V t FILIN Input filter time (HIN, LIN) (IRS213(6,62,63,65,68)D only) V IN = V & 5 V t filteren Enable input filter time 1 (IRS213(6,62,63,65,68)D only) 2 V IN = V & 5 V DT Deadtime External dead time MT Ton, off matching time (on all six channels) 5 External dead time >42 ns MDT DT matching (Hi->Lo & Lo->Hi on all channels) 6 External dead time s PM pulse width distortion (pwin-pwout) 75 PW input=1 µs t FLTCLR clear time : R = 2 MΩ, C = 1 nf ms V IN = V or 5 V V = V Note: For high side PWM, HIN pulse width must be 5 ns 5

6 HIN1,2,3 HIN1,2,3 LIN1,2,3 HO1,2,3 LO1,2,3 Figure 1. Input/Output Timing Diagram LIN1,2,3 HIN1,2,3 5% 5% 5% PW IN ten LIN1,2,3 HIN1,2,3 5% 5% HO1,2,3 LO1,2,3 9% ton tr PW OUT toff tf HO1,2,3 LO1,2,3 1% 9% 9% 1% Figure 2. Switching Time Waveforms Figure 3. Output Enable Timing Waveform 6

7 L IN 1,2,3 HIN1,2,3 5% 5% L IN 1,2,3 HIN1,2,3 5% 5% LO 1,2,3 5% 5% DT DT HO1,2,3 5% 5% Figure 4. Internal Deadtime Timing Waveforms 5% 5% tflt 5% 5% Any Ouput 9% tfltclr titrip Figure5. / Timing Waveforms t in,fil t in,fil n HIN/LIN on off on off on off HO/LO high low Figure 5.5 Input Filter Function 7

8 Lead Assignments 1 VCC VB1 28 HIN3 HIN2 HIN1 VCC VB1 HO1 VS1 1 VCC VB HIN1 HO HIN1 HO HIN2 VS HIN2 VS HIN3 25 LIN1 8 4 HIN LIN1 VB2 24 LIN VB2 5 LIN 1 VB LIN2 HO2 23 LIN HO2 6 LIN 2 HO LIN3 VS VS2 7 LIN 3 VS VB VB3 2 1 HO HO VSS LO3 VS3 LO 1 LO Lead PDIP VSS LO3 LO2 LO1 44 Lead PLCC w/o 12 leads VB3 HO3 VS VSS LO3 VS3 LO1 LO Lead SOIC (wide body) IRS213(6, 63, 65, 66, 67,68)D IRS213(6, 63, 65, 66, 67,68)DJ IRS213 (6, 63, 65, 66, 67,68)DS 1 VCC VB VCC VB HIN1 HO HIN1 HO HIN2 VS1 26 HIN3 HIN2 HIN1 VCC VB1 HO1 VS1 3 HIN2 VS HIN HIN LIN1 VB LIN1 VB LIN2 LIN3 HO2 23 VS2 22 LIN1 LIN2 LIN VB2 HO2 6 7 LIN2 LIN3 HO2 23 VS VS VB VB3 2 1 HO HO VSS VS VB3 HO VSS VS LO VS3 13 LO LO3 LO Lead PDIP VSS LO3 LO2 LO1 44 Lead PLCC w/o 12 leads 14 LO3 LO Lead SOIC (wide body) IRS21362D IRS 21362DJ IRS21362DS 8

9 Lead Definitions Symbol Description V CC V SS HIN1,2,3 HIN1,2,3 LIN1,2,3 V B1,2,3 HO 1,2,3 V S1,2,3 LO1,2,3 Low side supply voltage Logic Ground Logic inputs for high side gate driver outputs (HO1,2,3), out of phase [IRS213(6,63,65,66,67,68)D] Logic inputs for high side gate driver outputs (HO1,2,3), in phase (IRS21362D) Logic input for low side gate driver outputs (LO1,2,,3), out of phase Indicates over-current () or low-side undervoltage lockout has occurred. Negative logic, opendrain output Logic input to enable I/O functionality. I/O logic functions when ABLE is high (i.e., positive logic). No effect on and not latched Analog input for overcurrent shutdown. When active, shuts down outputs and activates and low. When becomes inactive, stays active low for an externally set time T FLTCLR, then automatically becomes inactive (open-drain high impedance). External RC network input used to define CLEAR delay, T FLTCLR, approximately equal to R*C. When >8 V, the pin goes back into open-drain high-impedance Low side gate drivers return High side floating supply High side gate driver outputs High voltage floating supply return Low side driver sourcing outputs Note 2: LIN, HIN,, and are internally clamped with a 5.2 V zener diode. 9

10 1 Functional Block Diagram HIN1 LIN1 HIN2 LIN2 HIN3 LIN3 VSS VB1 PREVTION PREVTION PREVTION UV UV VSS/ HV RESET SET VSS/ HV RESET SET VSS/ HV RESET SET LO1 LO2 LO3 HO2 HO3 HO1 S R SET DOMINANT Q VSS/ VSS/ VSS/.5 V VCC VB2 VS1 VS3 VB3 VS2 IRS2136D/IRS21363D/IRS21365D UV UV

11 11 Functional Block Diagram HIN1 LIN1 HIN2 LIN2 HIN3 LIN3 VSS VB1 PREVTION UV VSS/ HV RESET SET VSS/ HV RESET SET VSS/ HV RESET SET LO1 LO2 LO3 HO2 HO3 HO1 S R SET DOMINANT Q VSS/ VSS/ VSS/.5 V VCC VB2 VS1 VS3 VB3 VS2 IRS21362D UV UV UV PREVTION PREVTION

12 Functional Block Diagram HIN1 LIN1 HIN2 LIN2 HIN3 LIN3 VSS PREVTION PREVTION PREVTION IRS21366D/IRS21367D VSS/ VSS/ VSS/ HV SET RESET UV HV SET RESET UV HV SET RESET UV VB1 HO1 VS1 VB2 HO2 VS2 VB3 HO3 VS3 UV VCC.5 V S R SET Q DOMINANT VSS/ VSS/ LO1 LO2 VSS/ LO3 12

13 Functional Block Diagram HIN1 LIN1 HIN2 LIN2 HIN3 LIN3 VSS PREVTION PREVTION PREVTION IRS21368D VSS/ VSS/ VSS/ HV SET RESET UV HV SET RESET UV HV SET RESET UV VB1 HO1 VS1 VB2 HO2 VS2 VB3 HO3 VS3 UV VCC.5 V S R SET DOMINANT Q VSS/ VSS/ LO1 LO2 VSS/ LO3 VCC VBS ABLE LO1,2,3 HO1,2,3 <UV CC X X X (note 1) 15 V <UVBS V 5 V high imp LIN1,2,3 (note 2) 15 V 15 V V 5 V high imp LIN1,2,3 HIN1,2,3 15 V 15 V >V 5 V (note 3) 15 V 15 V V V high imp Note: A shoot-through prevention logic prevents LO1,2,3 and HO1,2,3 for each channel from turning on simultaneously. Note 1: U VCC is not latched, when V CC > U VCC, returns to high impedance. Note 2: When V BS < U VBS, HO goes low. After V BS goes higher than U VBS, HO stays low until a new falling IRS213(6, 63, 65, 66, 67, 68)D or rising IRS21362D transition of HIN. Note 3: When < V, returns to high-impedance after pin becomes greater than 8 V (@ V CC = 15 V) 13

14 FEATURES DESCRIPTION Bootstrap IRS2136xD family embeds an integrated bootstrap FET that allows an alternative drive of the bootstrap supply for a wide range of applications. There is one Bootstrap FET for each channel and it is connected between each of the floating supply (V B1, V B2, V B3 ) and V CC (see figure: 6). The bootstrap FET of each channel follows the state of the respective low side output stage (i.e., bootfet is ON when LO is high, it is OFF when LO is low), unless the V B voltage is higher than approximately 17 V. In that case the bootstrap FET keeps being off until V B voltage returns below that threshold (see figure 7). V CC BootFet1 BootFet2 BootFet3 Figure 6: Simplified bootfet connection V B1 V B2 V B3 parallel with the external bootstrap network (diode+resistor) or as a replacement of it. The use of the internal bootstrap as a replacement of the external bootstrap network may have some limitations in the following situations: - when used in non-complementary PWM schemes (typically 6-step modulations) - at very high PWM duty cycle due to bootstrap FET equivalent resistance (R BS, see page 5). In these cases better performances can be achieved using IRS2136x non D version with external bootstrap network. PCB LAYOUT TIPS Distance from H to L voltage The IRS2136xD family pin out lack some pins (only applies to PLCC package) (see page 8) in order to maximizing the distance between the high voltage and low voltage pins. It s strongly recommended to place the components tied to the floating voltage in the respective high voltage portions of the device (V B1,2,3, V S1,2,3 ) side. Ground plane To minimize noise coupling ground plane must not be placed under or near the high voltage floating side. Gate drive loops Current loops behave like an antenna able to receive and transmit EM noise. In order to reduce EM coupling and improve the power Phase voltage Vth~17V Vcc=15V V BX (V CC) I GC LO Bootstrap FET state BootFet ON BootFet OFF Figure 7: State diagram BootFet ON Bootstrap FET is suitable for most of the PWM modulation schemes and can be used either in HO X (LO X ) V SX () gate resistance Gate Drive Loop V GE C GC 14

15 switch turn on/off performances, gate drive loops must be reduced as much as possible. Moreover, current can be injected inside the gate drive loop via the IGBT collector-to-gate parasitic capacitance. The parasitic autoinductance of the gate loop contributes to develop a voltage across the gate-emitter increasing the possibility of self turn-on effect. Supply capacitors Supply capacitors must be placed as close as possible to the device pins (V CC and V SS for the ground tied supply, V B and V S for the floating supply) in order to minimize parasitic inductance/resistance. Routing and placement Power stage PCB parasitic may generate dangerous voltage transients for the gate driver and the control logic. In particular it s recommended to limit phase voltage negative transients. In order to avoid such undervoltage it is highly recommended to minimize high side emitter to low side collector distance and low side emitter to negative bus rail stray inductance. See DT4-4 at for more detailed information. 15

16 Figures 8-28 provide information on the experimental performance of the IRS2136D HVIC. The line plotted in each figure is generated from actual lab data. A large number of individual samples from multiple wafer lots were tested at three temperatures (-4ºC, 25ºC, and 125ºC) in order to generate the (experimental) curve. The line labeled consist of three data points (one data point at each of the tested temperatures) that have been connected together to illustrate the understood trend. The individual data points on the curve were determined by calculating the averaged experimental value of the parameter (for a given temperature). Turn-on Propagation Delay (ns) Figure 8. Turn-On Propagation Delay vs. Temperature Turn-off Propagation Delay (ns) Figure 9. Turn-Off Propagation Delay vs. Temperature 3 1 Turn-On Rise Time (ns) Turn-Off fall Time (ns) Figure 1. Turn-On Rise Time vs. Temperature Figure 11. Turn-Off Fall Time vs. Temperature 16

17 DL Turn-On Propagation Delay (ns) Figure 12. DL Turn-On Propagation Delay vs. Temperature to Output SD Propagation Delay (ns) Figure 13. to Output Shutdown Propagation Delay vs. Temperature to Propagation Delay (ns) Figure 14. to Propagation Delay vs. Temperature Low to Output SD Propagation Delay (ns) Figure 15. ABLE Low to Output Shutdown Propagation Delay vs. Temperature Low On Resistance ( Ohm) Figure 16. Low On Resistance vs. Temperature Low On Resistance ( Ohm) Figure17. Low On Resistance vs. Temperature 17

18 Quiescent VCC Supply Current (ma) Quiescent VBS Supply Current (ua) Figure 18. Quiescent V CC Supply Current vs. Temperature Figure 19. Quiescent V BS Supply Current vs. Temperature VCC Supply UV+ Going Threshold (V) VCC Supply UV- Going Threshold (V) Figure 2. V CC Supply Undervoltage Positive Going Threshold vs. Temperature Figure 21. V CC Supply Undervoltage Negative Going Threshold vs. Temperature VBS Supply UV+ Going Threshold (V) Figure 22. V BS Supply Undervoltage Positive Going Threshold vs. Temperature VBS Supply UV- Going Threshold (V) Figure 23. V BS Supply Undervoltage Negative Going Threshold vs. Temperature 18

19 8 6 EXP Figure 24. Positive Going Threshold vs.temperature Positive Going Threshold (mv Negative Going Threshold (mv) Figure 25. Negative Going Threshold vs. Temperature. Output High Short Circuit Pulsed Current (A) Figure 26. Output High Short Circuit Pulsed Current vs. Temperature Output Low Short Circuit Current (A) Figure 27. Output Low Short Circuit Current vs. Temperature Input Bias Current (ua) Figure 28. Input Bias Current vs. Temperature 19

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22 LEAD-FREE PART MARKING INFORMATION Part number IRSxxxxx Date code YWW? IR logo? P Pin 1 Identifier MARKING CODE Lead Free Released Non-Lead Free Relased?XXXX Lot Code (Prod mode 4 digit SPN code) Assembly site code Per SCOP 2-2 ORDERING INFORMATION Lead-free Part 28-Lead PDIP IRS2136DPbF 28-Lead PDIP IRS21362DPbF 28-Lead PDIP IRS21363DPbF 28-Lead PDIP IRS21365DPbF 28-Lead PDIP IRS21366DPbF 28-Lead PDIP IRS21367DPbF 28-Lead PDIP IRS21368DPbF 28-Lead SOIC IRS2136DSPbF 28-Lead SOIC IRS21362DSPbF 28-Lead SOIC IRS21363DSPbF 28-Lead SOIC IRS21365DSPbF 28-Lead SOIC IRS21366DSPbF 28-Lead SOIC IRS21367DSPbF 28-Lead SOIC IRS21368DSPbF Lead-free Part 44-Lead PLCC IRS2136DJPbF 44-Lead PLCC IRS21362DJPbF 44-Lead PLCC IRS21363DJPbF 44-Lead PLCC IRS21365DJPbF 44-Lead PLCC IRS21366DJPbF 44-Lead PLCC IRS21367DJPbF 44-Lead PLCC IRS21368DJPbF WORLDWIDE HEADQUARTERS: 233 Kansas Street, El Segundo, CA 9245 Tel: (31) This part has been qualified per Industrial Level Data and specifications subject to change without notice. 3/17/