ADP2323. Dual 3 A, 20 V Synchronous Step-Down Regulator with Integrated High-Side MOSFET. Data Sheet FEATURES TYPICAL APPLICATION CIRCUIT APPLICATIONS

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1 Dual 3 A, 0 V Synchronous Step-Down egulator with Integrated High-Side MOSFET FEATUES Input voltage: 4.5 V to 0 V ±% output accuracy Integrated 90 mω typical high-side MOSFET Flexible output configuration Dual output: 3 A/3 A Parallel single output: 6 A Programmable switching frequency: 50 khz to. MHz External synchronization input with programmable phase shift, or internal clock output Selectable PWM or PFM mode operation Adjustable current limit for small inductor External compensation and soft start Startup into precharged output Supported by ADIsimPower design tool APPLIATIONS ommunications infrastructure Networking and servers Industrial and instrumentation Healthcare and medical Intermediate power rail conversion D-to-dc point of load applications GENEAL DESIPTION The is a full featured, dual output, step-down dc-todc regulator based on current-mode architecture. The integrates two high-side power MOSFETs and two low-side drivers for the external N-channel MOSFETs. The two pulse-width modulation (PWM) channels can be configured to deliver dual 3 A outputs or a parallel-to-single 6 A output. The regulator operates from input voltages of 4.5 V to 0 V, and the output voltage can be as low as 0.6 V. The switching frequency can be programmed between 50 khz and. MHz, or synchronized to an external clock to minimize interference in multirail applications. The dual PWM channels run 80 out of phase, thereby reducing input current ripple as well as reducing the size of the input capacitor. The bidirectional synchronization pin can be programmed at a 60, 90, or 0 phase shift, providing the possibility for a stackable multiphase power solution. The can be set to operate in pulse-frequency modulation (PFM) mode at a light load for higher efficiency or in forced PWM for noise sensitive applications. External compensation and soft start provide design flexibility. Independent enable INT DV BOT OS BOT TYPIAL APPLIATION IUIT TOP INTV MODE SFG TK TK VDV TOP FB GND PGOOD PGOOD SYN T FB OMP OMP SS SS EN SS PVIN EN PVIN BST SS IN Figure. BST DL PGND DL M M IN BST BST L L V OUT OUT OUT V OUT inputs and power good outputs provide reliable power sequencing. To enhance system reliability, the device also includes undervoltage lockout (UVLO), overvoltage protection (OVP), overcurrent protection (OP), and thermal shutdown (TSD). The operates over the 40 to 5 junction temperature range and is available in a 3-lead LFSP_WQ package. EFFIIENY (%) V OUT 5V V OUT 3.3V OUTPUT UENT (A) Figure. Efficiency vs. Output urrent at V, f SW 600 khz ev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 906, Norwood, MA , U.S.A. Tel: Fax: Analog Devices, Inc. All rights reserved.

2 TABLE OF ONTENTS Features... Applications... Typical Application ircuit... General Description... evision History... Functional Block Diagram... 3 Specifications... 4 Absolute Maximum atings... 6 Thermal esistance... 6 ESD aution... 6 Pin onfiguration and Function Descriptions... 7 Typical Performance haracteristics... 9 Theory of Operation... 5 ontrol Scheme... 5 PWM Mode... 5 PFM Mode... 5 Precision Enable/Shutdown... 5 Separate Input Voltages... 5 Internal egulator (INTV)... 5 Bootstrap ircuitry... 6 Low-Side Driver... 6 Oscillator... 6 Synchronization... 6 Soft Start... 6 Peak urrent-limit and Short-ircuit Protection... 6 Voltage Tracking... 7 Parallel Operation... 7 Power Good... 7 Overvoltage Protection... 7 Undervoltage Lockout... 8 Thermal Shutdown... 8 Applications Information... 9 ADIsimPower Design Tool... 9 Input apacitor Selection... 9 Output Voltage Setting... 9 Voltage onversion Limitations... 9 urrent-limit Setting... 9 Inductor Selection... 0 Output apacitor Selection... 0 Low-Side Power Device Selection... Programming UVLO Input... ompensation omponents Design... Design Example... 3 Output Voltage Setting... 3 urrent-limit Setting... 3 Frequency Setting... 3 Inductor Selection... 3 Output apacitor Selection... 3 Low-Side MOSFET Selection... 4 ompensation omponents... 4 Soft Start Time Programming... 4 Input apacitor Selection... 4 External omponents ecommendation... 5 Typical Application ircuits... 6 Outline Dimensions... 3 Ordering Guide... 3 EVISION HISTOY 6/ ev. 0 to ev. A hange to Features Section... Added ADIsimPower Design Tool Section / evision 0: Initial Version ev. A Page of 3

3 FUNTIONAL BLOK DIAGAM.V EN_BUF UVLO PVIN EN A S OMP SS TK FB µa I SS 4µA SLOPE AMP 0.6V 0.7V AMP OVP SKIP MODE THESHOLD OP I MAX Σ MP SKIP MP HIUP MODE MODE_BUF ONTOL LOGI AND MOSFET DIVE WITH ANTIOSS POTETION DIVE VDV DIVE BOOST EGULATO NFET BST DL PGOOD 0.54V LK I MAX ZEO UENT MP UENT- LIMIT SELETION PGND MODE MODE_BUF PVIN VDV SFG SYN T OSILLATO LK SLOPE AMP LK SLOPE AMP EN_BUF EN_BUF 5V EGULATO INTV GND.V EN_BUF UVLO PVIN EN A S OMP SS TK FB µa 4µA SLOPE AMP I SS 0.6V AMP 0.7V OVP I MAX Σ SKIP MODE THESHOLD OP MP SKIP MP HIUP MODE MODE_BUF ONTOL LOGI AND MOSFET DIVE WITH ANTIOSS POTETION DIVE VDV DIVE BOOST EGULATO NFET BST DL PGOOD 0.54V LK I MAX ZEO UENT MP UENT- LIMIT SELETION Figure 3. Functional Block Diagram ev. A Page 3 of 3

4 SPEIFIATIONS PVIN PVIN V at T J 40 to 5, unless otherwise noted. Table. Parameters Symbol Test onditions/omments Min Typ Max Units POWE INPUT (PVINx PINS) Power Input Voltage ange V PVIN V Quiescent urrent (PVIN PVIN) I Q MODE GND, no switching 3 5 ma Shutdown urrent (PVIN PVIN) I SHDN EN EN GND µa PVINx Undervoltage Lockout Threshold UVLO PVINx ising V PVINx Falling V FEEDBAK (FBx PINS) FBx egulation Voltage V FB PVINx 4.5 V to 0 V V FBx Bias urrent I FB µa EO AMPLIFIE (OMPx PINS) Transconductance g m µs EA Source urrent I SOUE µa EA Sink urrent I SINK µa INTENAL EGULATO (INTV PIN) INTV Voltage V Dropout Voltage I INTV 30 ma 400 mv egulator urrent Limit ma SWITH NODE (SWx PINS) High-Side On esistance V BST to V SW 5 V mω SWx Peak urrent Limit ILIM floating, V BST to V SW 5 V A ILIM 47 kω, V BST to V SW 5 V A ILIM 5 kω, V BST to V SW 5 V A SWx Minimum On Time 3 t MIN_ON 30 ns SWx Minimum Off Time 3 t MIN_OFF 50 ns LOW-SIDE DIVE (DLx PINS ) ising Time 3 DL. nf, see Figure 9 0 ns Falling Time 3 DL. nf, see Figure 0 ns Sourcing esistor 4 6 Ω Sinking esistor 4.5 Ω OSILLATO (T PIN) PWM Switching Frequency f SW OS 00 kω khz PWM Frequency ange khz SYNHONIZATION (SYN PIN) SYN Input SYN configured as input Synchronization ange khz Minimum On Pulse Width 00 ns Minimum Off Pulse Width 00 ns High Threshold.3 V Low Threshold 0.4 V SYN Output SYN configured as output Frequency on SYN Pin f LKOUT f SW khz Positive Pulse Time 00 ns SOFT STAT (SSx PINS) SSx Pin Source urrent I SS µa ev. A Page 4 of 3

5 Parameters Symbol Test onditions/omments Min Typ Max Units TAKING INPUT (TKx PINS) TKx Input Voltage ange mv TKx-to-FBx Offset Voltage TKx 0 mv to 500 mv 0 0 mv TKx Input Bias urrent 00 na POWE GOOD (PGOODx PINS) Power Good ising Threshold % Power Good Hysteresis 5 % Power Good Deglitch Time From FBx to PGOODx 6 lock cycle PGOODx Leakage urrent V PGOOD 5 V 0. µa PGOODx Output Low Voltage I PGOOD ma mv ENABLE (ENx PINS) ENx ising Threshold..8 V ENx Falling Threshold.0. V ENx Source urrent EN voltage below falling threshold 5 µa EN voltage above rising threshold µa MODE (MODE PIN) Input High Voltage.3 V Input Low Voltage 0.4 V THEMAL Thermal Shutdown Threshold 50 Thermal Shutdown Hysteresis 5 Tested in a feedback loop that adjusts V FB to achieve a specified voltage on the OMPx pin. Pin-to-pin measurements. 3 Guaranteed by design. ev. A Page 5 of 3

6 ABSOLUTE MAXIMUM ATINGS Table. Parameter PVIN, PVIN, EN, EN, BST, BST FB, FB, SS, SS,OMP, OMP, PGOOD, PGOOD, TK, TK, SFG, SYN, T, MODE INTV, VDV, DL, DL PGND to GND Temperature ange Operating (Junction) Storage Soldering onditions ating 0.3 V to V V to V V SW 6 V 0.3 V to 6 V 0.3 V to 6 V 0.3 V to 0.3 V 40 to 5 65 to 50 JEDE J-STD-00 Stresses above those listed under Absolute Maximum atings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THEMAL ESISTANE θ JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Boundary ondition θ JA is measured using natural convection on a JEDE 4-layer board, and the exposed pad is soldered to the printed circuit board (PB) with thermal vias. Table 3. Thermal esistance Package Type θ JA Unit 3-Lead LFSP_WQ 3.7 /W ESD AUTION ev. A Page 6 of 3

7 PIN ONFIGUATION AND FUNTION DESIPTIONS PGOOD 4 SFG 3 BST SYN 3 DL GND 4 PGND TOP VIEW INTV 5 0 VDV (Not to Scale) T 6 9 DL MODE 7 8 BST PGOOD 8 7 FB OMP SS TK EN PVIN PVIN FB OMP SS TK EN PVIN PVIN NOTES. THE EXPOSED PAD SHOULD BE SOLDEED TO AN EXTENAL GND PLANE. Figure 4. Pin onfiguration (Top View) Table 4. Pin Function Descriptions Pin No. Mnemonic Description PGOOD Power-Good Output (Open Drain) for hannel. A pull-up resistor of 0 kω to 00 kω is recommended. SFG Synchronization onfiguration Input. The SFG pin configures the SYN pin as an input or output. onnect SFG to INTV to configure SYN as an output. Using a resistor to pull down to GND configures SYN as an input with various phase shift degrees. 3 SYN Synchronization. This pin can be configured as an input or an output. When configured as an output, it provides a clock at the switching frequency. When configured as an input, this pin accepts an external clock to which the regulators are synchronized and the phase shift is configured by SFG. Note that when SYN is configured as an input, the PFM mode is disabled and the device works only in continuous conduction mode (M). 4 GND Analog Ground. onnect to the ground plane. 5 INTV Internal 5 V egulator Output. The I control circuits are powered from this voltage. Place a μf ceramic capacitor between INTV and GND. 6 T onnect a resistor between T and GND to program the switching frequency between 50 khz and. MHz. 7 MODE Mode Selection. When this pin is connected to INTV, the PFM mode is disabled and the regulator works only in M. When this pin is connected to ground, the PFM mode is enabled. If the low-side device is a diode, the MODE pin must be connected to ground. 8 PGOOD Power-Good Output (Open Drain) for hannel. A pull-up resistor of 0 kω to 00 kω is recommended. 9 FB Feedback Voltage Sense Input for hannel. onnect to a resistor divider from the hannel output voltage, VOUT. onnect FB to INTV for parallel applications. 0 OMP Error Amplifier Output for hannel. onnect an network from OMP to GND. onnect OMP and OMP together for parallel applications. SS Soft Start ontrol for hannel. onnect a capacitor from SS to GND to program the soft start time. For parallel applications, SS remains open. TK Tracking Input for hannel. To track a master voltage, drive this pin from a voltage divider from the master voltage. If the tracking function is not used, connect TK to INTV. 3 EN Enable Pin for hannel. An external resistor divider can be used to set the turn-on threshold. When not using the enable pin, connect EN to PVIN. 4, 5 PVIN Power Input for hannel. onnect PVIN to the input power source, and connect a bypass capacitor between PVIN and ground. 6, 7 Switch Node for hannel. 8 BST Supply ail for the Gate Drive of hannel. Place a 0. μf capacitor between and BST. 9 DL Low-Side Gate Driver Output for hannel. onnect a resistor between DL and PGND to program the current-limit threshold of hannel. 0 VDV Low-Side Driver Supply Input. onnect VDV to INTV. Place a μf ceramic capacitor between the VDV pin and PGND. PGND Driver Power Ground. onnect to the source of the synchronous N-channel MOSFET. DL Low-Side Gate Driver Output for hannel. onnect a resistor between this pin and PGND to program the current-limit threshold of hannel. ev. A Page 7 of

8 Pin No. Mnemonic Description 3 BST Supply ail for the Gate Drive of hannel. Place a 0. µf capacitor between and BST. 4, 5 Switch Node for hannel. 6, 7 PVIN Power Input for hannel. This pin is the power input for hannel and provides power for the internal regulator. onnect to the input power source and connect a bypass capacitor between PVIN and ground. 8 EN Enable Pin for hannel. An external resistor divider can be used to set the turn-on threshold. When not using the enable pin, connect the EN pin to PVIN. 9 TK Tracking Input for hannel. To track a master voltage, drive this pin from a voltage divider from the master voltage. If the tracking function is not used, connect TK to INTV. 30 SS Soft Start ontrol for hannel. To program the soft start time, connect a capacitor from SS to GND. 3 OMP Error Amplifier Output for hannel. onnect an network from OMP to GND. onnect OMP and OMP together for a parallel application. 3 FB Feedback Voltage Sense Input for hannel. onnect to a resistor divider from the hannel output voltage, V OUT. Exposed Pad Solder the exposed pad to an external GND plane. ev. A Page 8 of 3

9 TYPIAL PEFOMANE HAATEISTIS Operating conditions: T A 5, V, V OUT 3.3 V, L 4.7 µh, OUT 47 µf, f SW 600 khz, unless otherwise noted EFFIIENY (%) INDUTO: DH05NP-33N MOSFET: FDS OUTPUT UENT (A) V OUT 5.0V V OUT 3.3V V OUT.5V V OUT.8V V OUT.5V V OUT.V Figure 5. Efficiency at V, f SW 600 khz, FPWM EFFIIENY (%) INDUTO: DH05NP-68N MOSFET: FDS OUTPUT UENT (A) V OUT 5.0V V OUT 3.3V V OUT.5V V OUT.8V V OUT.5V V OUT.V Figure 8. Efficiency at V, f SW 300 khz, FPWM EFFIIENY (%) V OUT 3.3V, FPWM V OUT 3.3V, PFM V OUT 5V, FPWM V OUT 5V, PFM EFFIIENY (%) V OUT 3.3V, FPWM V OUT 3.3V, PFM V OUT 5V, FPWM V OUT 5V, PFM 0 INDUTO: DH05NP-33N MOSFET: FDS OUTPUT UENT (A) INDUTO: DH05NP-68N MOSFET: FDS OUTPUT UENT (A) Figure 6. Efficiency at V, f SW 600 khz, PFM Figure 9. Efficiency at V, f SW 300 khz, PFM SHUTDOWN UENT (μa) T J 40 T J 5 T J 5 QUIESENT UENT (ma) T J 40 T J 5 T J (V) Figure 7. Shutdown urrent vs (V) Figure 0. Quiescent urrent vs ev. A Page 9 of 3

10 UVLO THESHOLD (V) ISING FALLING ENABLE THESHOLD (V) ISING FALLING TEMPEATUE ( ) Figure. UVLO Threshold vs. Temperature TEMPEATUE ( ) Figure 4. EN Threshold vs. Temperature EN SOUE UENT (µa) EN SOUE UENT (µa) TEMPEATUE ( ) Figure. EN Source urrent at V EN.5 V TEMPEATUE ( ) Figure 5. EN Source urrent at V EN V FEEDBAK VOLTAGE (mv) TANSONDUTANE (µs) TEMPEATUE ( ) Figure 3. FB Voltage vs. Temperature TEMPEATUE ( ) Figure 6. g m vs. Temperature ev. A Page 0 of 3

11 FEQUENY (khz) OS 00kΩ VOLTAGE (V) TEMPEATUE ( ) Figure 7. Frequency vs. Temperature (V) Figure 0. INTV Voltage vs MOSFET ESISTO (mω) TEMPEATUE ( ) Figure 8. MOSFET DSON vs. Temperature SSx PIN SOUE UENT (µa) TEMPEATUE ( ) Figure. SSx Pin Source urrent vs. Temperature SW SW DL H 5.00V H.00V M0.0ns A H.0V T 3.0% Figure 9. Low-Side Driver ising Edge Waveform, DL. nf DL H 5.00V H.00V M0.0ns A H.0V T 60.0% Figure. Low-Side Driver Falling Edge Waveform, DL. nf ev. A Page of 3

12 PEAK UENT LIMIT (A) PEAK UENT LIMIT (A) TEMPEATUE ( ) Figure 3. urrent-limit Threshold vs. Temperature, ILIM Floating TEMPEATUE ( ) Figure 6. urrent-limit Threshold vs. Temperature, ILIM 47 kω PEAK UENT LIMIT (A) TEMPEATUE ( ) Figure 4. urrent-limit Threshold vs. Temperature, ILIM 5 kω V OUT (A) I L SW H 0.0mV B W H 0.0V H4.00A Ω M.00µs A H 5.80V T 50.00% Figure 7. ontinuous onduction Mode (M) V OUT (A) V OUT (A) I L I L 4 4 SW SW H 0.0mV B W H 0.0V H4 500mA Ω M.00µs A H 9.40V T 50.0% Figure 5. Discontinuous onduction Mode (DM) H 00mV B W H 0.0V H4.00A Ω Figure 8. Power Saving Mode M400µs A H.0mV T 60.40% ev. A Page of 3

13 EN EN 3 3 V OUT V OUT PGOOD PGOOD I OUT I L 4 H.00V B W H3 0.0V H 5.00V H4.00A Ω M.00ms A H.80V T 50.40% Figure 9. Soft Start With Full Load H.00V H3 0.0V B W H 5.00V H4.00A Ω M.00ms A H.80V T 50.40% Figure 3. Precharged Output V OUT (A) V OUT (A) 3 SW I OUT I OUT 4 H 00mV B W M00µs A H4.00A H4.00A Ω T 70.0% Figure 30. Load Transient esponse, 0.5 A to.5 A H 0.0mV B W H 5.00V M.00ms A H 8.00mV H3 5.00V B W T 7.00% Figure 33. Line Transient esponse, from 8 V to 4 V, I OUT 3 A V OUT V OUT SW SW I L I L 4 H.00V B W H 0.0V H4.00A Ω M0.0ms A H 960mV T 0.60% Figure 3. Output Short H.00V B W H 0.0V H4.00A Ω M0.0ms A H.8V T 60.40% Figure 34. Output Short ecovery ev. A Page 3 of 3

14 SYN SYN 3 3 H 0.0V H3 5.00V H 0.0V M.00µs A H3.90V T 50.0% Figure 35. External Synchronization with 60 Phase Shift H 0.0V H3 5.00V H 0.0V M.00µs A H3.90V T 50.0% Figure 38. External Synchronization with 90 Phase Shift SYN 3 I L I L H 0.0V H3 5.00V H 0.0V M.00µs A H3.90V T 50.0% Figure 36. External Synchronization with 0 Phase Shift H 0.0V H3.00A Ω H 0.0V M.00µs A H 5.80V H4.00A Ω T 50.00% Figure 39. Dual Phase, Single Output, V OUT 3.3 V, I OUT 6 A V MASTE V MASTE V SLAVE V SLAVE H3.00V H.00V B B W M.00ms A H 660mV W T 43.00% Figure 37. oincident Tracking H3.00V H.00V B B W M.00ms A H 660mV W T 43.00% Figure 40. atiometric Tracking ev. A Page 4 of 3

15 THEOY OF OPEATION The is a full featured, dual output, step-down dc-todc regulator based on current-mode architecture. It integrates two high-side power MOSFETs and two low-side drivers for external MOSFETs. The targets high performance applications that require high efficiency and design flexibility. The can operate with an input voltage from 4.5 V to 0 V, and can regulate the output voltage down to 0.6 V. Additional features for flexible design include programmable switching frequency, programmable soft start, external compensation, independent enable inputs, and power good outputs. ONTOL SHEME The uses a fixed frequency, current-mode PWM control architecture during medium to full loads, but shifts to a power save mode (PFM) at light loads when the PFM mode is enabled. The power save mode reduces switching losses and boosts efficiency under light loads. When operating in the fixed frequency PWM mode, the duty cycle of the integrated N- channel MOSFET (referred to interchangeably as NFET or MOSFET) is adjusted, which, in turn, regulates the output voltage. When operating in power save mode, the switching frequency is adjusted to regulate the output voltage. PWM MODE In PWM mode, the operates at a fixed frequency that is set by an external resistor. At the start of each oscillator cycle, the high-side NFET turns on, placing a positive voltage across the inductor. The inductor current increases until the current sense signal crosses the peak inductor current threshold that turns off the high-side NFET and turns on the low-side NFET (diode). This places a negative voltage across the inductor causing the inductor current to reduce. The low-side NFET (diode) stays on for the remainder of the cycle or until the inductor current reaches zero. PFM MODE Pull the MODE pin to ground to enable the PFM mode. When the OMPx voltage is below the PFM threshold voltage, the device enters the PFM mode. When the device enters the PFM mode, it monitors the FBx voltage to regulate the output voltage. Because the high-side and low-side NFETs are turned off, the output voltage drops due to the load current discharging the output capacitor. When the FBx voltage drops below V, the device starts switching and the output voltage increases as the output capacitor is charged by the inductor current. When the FBx voltage exceeds 0.6 V, the device turns off both the high-side and low-side NFETs until the FBx voltage drops to V. In the PFM mode, the output voltage ripple is larger than the ripple in the PWM mode. PEISION ENABLE/SHUTDOWN The has two independent enable pins (EN and EN) for each channel. The ENx pin has an internal pull-down current source (5 µa) that provides default turn off when an ENx pin is open. When the voltage on the EN or EN pin exceeds. V (typical), hannel or hannel is enabled and the internal pull-down current source at the EN or EN pin is reduced to µa, which allows the user to program the input voltage undervoltage lockout (UVLO). When the voltage on the EN or EN pin drops below. V (typical), hannel or hannel turns off. When EN and EN are both below. V, all of the internal circuits turn off and the device enters the shutdown mode. SEPAATE INPUT VOLTAGES The supports two separate input voltages. This means that the PVIN and PVIN voltages can be connected to two different supply voltages. In these types of applications, the PVIN voltage needs to be above the UVLO voltage before the PVIN voltage begins to rise because the PVINvoltage provides the power supply for the internal regulator and control circuitry. This feature makes it possible for a cascading supply operation as shown in Figure 4, where PVIN is sourced from the hannel output. In this configuration, the hannel output voltage needs to be high enough to maintain hannel in regulation, and the hannel output voltage needs to be higher than the input voltage UVLO threshold. V OUT OUT L M PVIN DL PGND PVIN DL M L V OUT OUT Figure 4. ascading Supply Operation INTENAL EGULATO (INTV) The internal regulator provides a stable voltage supply for the internal control circuits and bias voltage for the low-side gate drivers. A µf ceramic capacitor is recommended to be placed between INTV and GND. The internal regulator also includes a current-limit circuit for protection. The internal regulator is active when either one of the channels is enabled. The PVIN pin provides power for the internal regulator that is used by both channels ev. A Page 5 of 3

16 BOOTSTAP IUITY The integrates the boot regulators to provide the gate drive voltage for the high-side NFETs. The regulators generate 5 V bootstrap voltages between the BSTx pin and the SWx pin. It is recommended that an X7 or an X5, 0. µf ceramic capacitor be placed between the BSTx and the SWx pins. LOW-SIDE DIVE The DLx pin provides the gate drive for the low-side N-channel MOSFET. Internal circuitry monitors the gate driver signal to ensure break-before-make switching to prevent cross conduction. The VDV pin provides the power supply to the low-side drivers. It is limited to a 5.5 V maximum input, and placing a µf ceramic capacitor close to this pin is recommended. OSILLATO A resistor from T to GND programs the switching frequency according to the following equation: f SW [khz] 60,000 OS [kω] A 00 kω resistor sets the frequency to 300 khz, and a 00 kω resistor sets the frequency to 600 khz. Figure 4 shows the typical relationship between f SW and OS. FEQUENY (khz) SYNHONIZATION OS (kω) Figure 4. f SW vs. OS The SYN pin can be configured as an input or an output by setting the SFG pin as shown in Table 5. Table 5. SFG onfiguration SFG SYN Phase Shift High Output 0 GND Input kω to GND Input 0 00 kω to GND Input When the SYN pin is configured as an output, it generates a clock with a frequency that is equal to the internal switching frequency. When the SYN pin is configured as an input, the synchronizes to the external clock that is applied to the SYN pin, and the internal clock must be programmed lower than the external clock. The phase shift can be programmed by the SFG pin. When working in synchronization mode, the disables the PFM mode and works only in the M mode. SOFT STAT The SSx pins are used to program the soft start time. Place a capacitor between SSx and GND; an internal current charges this capacitor to establish the soft start ramp. The soft start time can be calculated using the following equation: V SS TSS 0. 6 I SS where: SS is the soft start capacitance. I SS is the soft start pull-up current (3.5 µa). If the output voltage is precharged prior to power up, the prevents the low-side MOSFET from turning on until the soft start voltage exceeds the voltage on the FBx pin. During soft start, the uses frequency foldback to prevent output current runaway. The switching frequency is reduced according to the voltage present at the FBx pin, which allows more time for the inductor to discharge. The correlation between the switching frequency and the FBx pin voltage is listed in Table 6. Table 6. FBx Pin Voltage and Switching Frequency FBx Pin Voltage Switching Frequency V FB 0.4 V f SW 0.4 V > V FB 0. V / f SW V FB < 0. V /4 f SW PEAK UENT-LIMIT AND SHOT-IUIT POTETION The uses a peak current-limit protection circuit to prevent current runaway. Place a resistor between DLx and PGND to program the current-limit value listed in Table 7. The programmable current-limit threshold feature allows for the use of a small size inductor for low current applications. Table 7. Peak urrent-limit Threshold Setting ILIM Peak urrent-limit Threshold Floating 4.8 A 47 kω 3 A 5 kω.5 A ev. A Page 6 of 3

17 The uses hiccup mode for overcurrent protection. When the peak inductor current reaches the current-limit threshold, the high-side MOSFET turns off and the low-side driver turns on until the next cycle while the overcurrent counter increments. If the overcurrent counter reaches 0, or the FBx pin voltage falls to 0.5 V after the soft start, the device enters hiccup mode. During this mode, the high-side MOSFET and low-side driver are both turned off. The device remains in this mode for seven soft start times and then attempts to restart from soft start. If the currentlimit fault is cleared, the device resumes normal operation; otherwise, it reenters hiccup mode. In some cases, the input voltage (PVIN) ramp rate is too slow or the output capacitor is too large to support the setting regulation voltage during the soft start causing the device to enter the hiccup mode. To avoid such cases, use a resistor divider at the ENx pin to program the input voltage UVLO or use a longer soft start time. VOLTAGE TAKING The has a tracking input, TKx, that allows the output voltage to track an external (master) voltage. It allows power sequencing applicable to FPGAs, DSPs, and ASIs, which may require a power sequence between the core and the I/O voltages. The internal error amplifier includes three positive inputs: the internal reference voltage, the soft start voltage, and the tracking input voltage. The error amplifier regulates the feedback voltage to the lowest of the three voltages. To track a master voltage, tie the TKx pin to a resistor divider from the master voltage as shown in Figure 43. TK_TOP TK_BOT V MASTE TKx SWx FBx TOP BOT V SLAVE Figure 43. Voltage Tracking A common application is coincident tracking, which is shown in Figure 44. oincident tracking limits the slave output voltage to be the same as the master voltage until it reaches regulation. For coincident tracking, set TK_TOP TOP and TK_BOT BOT. VOLTAGE V MASTE V SLAVE atiometric tracking is shown in Figure 45. The slave output is limited to a fraction of the master voltage. In this application, the slave and master voltages reach the final value at the same time. VOLTAGE TIME V MASTE V SLAVE Figure 45. atiometric Tracking The ratio of the slave output voltage to the master voltage is a function of the two dividers, as follows: V V SLAVE MASTE TOP BOT TK _ TOP TK _ BOT The final TKx pin voltage must be higher than 0.54 V. If the TK function is not used, connect the TKx pin to INTV. PAALLEL OPEATION supports a two phase parallel operation to provide a single output of 6 A. To configure the as a two phase single output. onnect the FB pin to INTV, thereby disabling the hannel error amplifier.. onnect OMP to OMP and connect EN to EN. 3. Use SS to set the soft start time and keep SS open. During parallel operation, the voltages of PVIN and PVIN should be the same. POWE GOOD The power good (PGOODx) pin is an active high, open drain output that indicates if the regulator output voltage is within regulation. High indicates that the voltage at an FBx pin (and, hence, the output voltage) is above 90% of the reference voltage. Low indicates that the voltage at an FBx pin (and, hence, the output voltage) is below 85% of the reference voltage. There is a 6-cycle deglitch time between FBx and PGOODx. OVEVOLTAGE POTETION The provides an overvoltage protection (OVP) feature to protect the system against the output shorting to a higher voltage supply or when a strong load transient occurs. If the feedback voltage increases to 0.7 V, the internal high-side MOSFET and low-side driver turn off until the voltage at the FBx pin reduces to 0.63 V, at which time the resumes normal operation TIME Figure 44. oincident Tracking ev. A Page 7 of 3

18 UNDEVOLTAGE LOKOUT The undervoltage lockout (UVLO) threshold is 4. V with 0.5 V hysteresis to prevent the device from power-on glitches. When the PVIN or PVIN voltage rises above 4. V, hannel or hannel is enabled and the soft start period initiates. When either PVIN or PVIN drops below 3.7 V, it turns off hannel or hannel, respectively. THEMAL SHUTDOWN In the event that the junction temperature exceeds 50, the thermal shutdown circuit turns off the regulator. A 5 hysteresis is included so that the does not recover from thermal shutdown until the on-chip temperature drops below 35. Upon recovery, soft start is initiated prior to normal operation. ev. A Page 8 of 3

19 APPLIATIONS INFOMATION ADIsimPower DESIGN TOOL The is supported by the ADIsimPower design tool set. ADIsimPower is a collection of tools that produce complete power designs optimized for a specific design goal. The tools enable the user to generate a full schematic and bill of materials, and calculate performance in minutes. ADIsimPower can optimize designs for cost, area, efficiency, and parts count while taking into consideration the operating conditions and limitations of the I and all real external components. For more information about ADIsimPower design tools, refer to The tool set is available from this website, and users can request an unpopulated board through the tool. INPUT APAITO SELETION The input decoupling capacitor attenuates high frequency noise on the input and acts as an energy reservoir. This capacitor should be a ceramic capacitor in the range of 0 µf to 47 µf and must be placed close to the PVINx pin. The loop composed of this input capacitor, high-side NFET, and low-side NFET must be kept as small as possible. The voltage rating of the input capacitor must be greater than the maximum input voltage. The rms current rating of the input capacitor should be larger than the following equation: I IN _ rms I D ( D) OUT OUTPUT VOLTAGE SETTING The output voltage of the can be set by an external resistive divider using the following equation: TOP VOUT 0.6 BOT To limit output voltage accuracy degradation due to FBx pin bias current (0. µa maximum) to less than 0.5% (maximum), ensure that BOT is less than 30 kω. Table 8 provides the recommended resistive divider for various output voltage options. Table 8. esistive Divider for Various Output Voltages V OUT (V) TOP, ±% (kω) BOT, ±% (kω) VOLTAGE ONVESION LIMITATIONS The minimum output voltage for a given input voltage and switching frequency is constrained by the minimum on time. The minimum on time of the is typically 30 ns. The minimum output voltage in M mode at a given input voltage and frequency can be calculated by using the following equation: V OUT_MIN t MIN_ON f SW ( DSON DSON ) I OUT_MIN t MIN_ON f SW ( DSON L ) I OUT_MIN where: V OUT_MIN is the minimum output voltage. t MIN_ON is the minimum on time. I OUT_MIN is the minimum output current. f SW is the switching frequency. DSON is the high-side MOSFET on resistance. DSON is the low-side MOSFET on resistance. L is the series resistance of output inductor. The maximum output voltage for a given input voltage and switching frequency is constrained by the minimum off time and the maximum duty cycle. The minimum off time is typically 50 ns and the maximum duty is typically 90% in the. The maximum output voltage that is limited by the minimum off time at a given input voltage and frequency can be calculated using the following equation: V OUT_MAX ( t MIN_OFF f SW ) ( DSON DSON ) I OUT_MAX ( t MIN_OFF f SW ) ( DSON L ) I OUT_MAX where: V OUT_MAX is the maximum output voltage. t MIN_OFF is the minimum off time. I OUT_MAX is the maximum output current. The maximum output voltage limited by the maximum duty cycle at a given input voltage can be calculated by using the following equation: V OUT_MAX D MAX where D MAX is the maximum duty. As the previous equations show, reducing the switching frequency alleviates the minimum on time and minimum off time limitation. UENT-LIMIT SETTING The has three selectable current-limit thresholds. Make sure that the selected current-limit value is larger than the peak current of the inductor, I PEAK. ev. A Page 9 of 3

20 INDUTO SELETION The inductor value is determined by the operating frequency, input voltage, output voltage, and inductor ripple current. Using a small inductor leads to a faster transient response but degrades efficiency due to larger inductor ripple current, whereas a large inductor value leads to smaller ripple current and better efficiency but results in a slower transient response. Thus, there is a trade-off between the transient response and efficiency. As a guideline, the inductor ripple current, ΔI L, is typically set to /3 of the maximum load current. The inductor value can be calculated using the following equation: ( VIN VOUT ) D L I f L where: is the input voltage. V OUT is the output voltage. ΔI L is the inductor ripple current. f SW is the switching frequency. D is the duty cycle. V D V OUT IN SW The uses adaptive slope compensation in the current loop to prevent subharmonic oscillations when the duty cycle is larger than 50%. The internal slope compensation limits the minimum inductor value. For a duty cycle that is larger than 50%, the minimum inductor value is determined by the following equation: V OUT ( D) f SW The inductor peak current is calculated using the following equation: IL IPEAK IOUT The saturation current of the inductor must be larger than the peak inductor current. For the ferrite core inductors with a quick saturation characteristic, the saturation current rating of the inductor should be higher than the current-limit threshold of the switch to prevent the inductor from getting into saturation. The rms current of the inductor can be calculated by the following equation: I L I MS IOUT Shielded ferrite core materials are recommended for low core loss and low EMI. Table 9. ecommended Inductors Vendor Part No. Value [µh] I SAT [A] I MS [A] D [mω] Sumida DH05NP-5N DH05NP-N DH05NP-33N DH05NP-47N DH05NP-68N oilcraft MSS048-5NL MSS048-NL MSS048-33NL MSS048-47NL MSS048-68NL Wurth Elektronik OUTPUT APAITO SELETION The output capacitor selection affects both the output voltage ripple and the loop dynamics of the regulator. For example, during load step transient on the output, when the load is suddenly increased, the output capacitor supplies the load until the control loop has a chance to ramp up the inductor current, which causes an undershoot of the output voltage. Use the following equation to calculate the output capacitance that is required to meet the voltage droop requirement: OUT _ UV KUV I STE L P ( VIN VOUT ) VOUT _ UV where: ΔI STEP is the load step. ΔV OUT_UV is the allowable undershoot on the output voltage. K UV is a factor, typically setting K UV. Another case is when a load is suddenly removed from the output and the energy stored in the inductor rushes into the output capacitor, which causes the output to overshoot. The output capacitance required to meet the overshoot requirement can be calculated using the following equation: K I L OV STEP OUT _ OV ( VOUT VOUT _ OV ) VOUT where: ΔV OUT_OV is the allowable overshoot on the output voltage. K OV is a factor, typically setting K OV. The output ripple is determined by the ES of the output capacitor and its capacitance value. Use the following equation to select a capacitor that can meet the output ripple requirements: I L OUT _ IPPLE 8 f V ES V I L SW OUT _ IPPLE OUT _ IPPLE ev. A Page 0 of 3

21 where: ΔV OUT_IPPLE is the allowable output voltage ripple. ES is the equivalent series resistance of the output capacitor. Select the largest output capacitance given by OUT_UV, OUT_OV, and OUT_IPPLE to meet both load transient and output ripple performance. The selected output capacitor voltage rating must be greater than the output voltage. The minimum rms current rating of the output capacitor is determined by the following equation: I OUT _ rms I L LOW-SIDE POWE DEVIE SELETION The has integrated low-side MOSFET drivers, which can drive the low-side N-channel MOSFETs (NFETs). The selection of the low-side N-channel MOSFET affects the dc-todc regulator performance. The selected MOSFET must meet the following requirements: Drain source voltage (V DS ) must be higher than.. Drain current (I D ) must be greater than the. I LIMIT_MAX, where I LIMIT_MAX is the selected maximum current-limit threshold. The low-side gate drive voltage is 5 V. Make sure that the selected MOSFET can be fully turned on at 5 V. Total gate charge (Qg at 5 V) must be less than 30 n. Lower Qg characteristics constitute higher efficiency. When the high-side MOSFET is turned off, the low-side MOSFET carries the inductor current. For low duty cycle applications, the low-side MOSFET carries the current for most of the period. To achieve higher efficiency, it is important to select a low on-resistance MOSFET. The power conduction loss for the low-side MOSFET can be calculated using the following equation: P FET_LOW I OUT DSON ( D) where DSON is the on resistance of the low-side MOSFET. Make sure that the MOSFET can handle the thermal dissipation due to the power loss. In some cases, efficiency is not critical for the system; therefore, the diode can be selected as the low-side power device. The average current of the diode can be calculated using the following equation: I DIODE (AVG) ( D) I OUT The reverse breakdown voltage rating of the diode must be greater than the input voltage with an appropriate margin to allow for ringing, which may be present at the SWx node. A Schottky diode is recommended because it has low forward voltage drop and fast switching speed. If a diode is used for the low-side device, the must enable the PFM mode by connecting the MODE pin to ground. Table 0. ecommended MOSFETs Vendor Part No. V DS I D DSON Qg Fairchild FDS V 0.7 A mω n Fairchild FDMS V 4 A 8 mω 8 n Fairchild FDS6898A 0 V 9.4 A 4 mω 6 n Vishay Si4804DY 30 V 7.9 A 7 mω 7 n Vishay SiA430DJ 0 V 0.8 A 8.5 mω 5.3 n AOS AON V 39 A 5 mω 7. n AOS AO4884L 40 V 0 A 6 mω 3.6 n POGAMMING UVLO INPUT The precision enable input can be used to program the UVLO threshold and hysteresis of the input voltage as shown in Figure 46. TOP_EN BOT_EN PVINx ENx µa 4µA.V EN MP Figure 46. Programming UVLO Input Use the following equation to calculate TOP_EN and BOT_EN :. V VIN _ ISING.V VIN _ FALLING TOP _ EN. V 5 μa. V μa BOT _ EN V IN _ ISING. V TOP _ EN TOP _ EN 5 μα. V where: _ISING is the rising threshold. _FALLING is the falling threshold. OMPENSATION OMPONENTS DESIGN For peak current-mode control, the power stage can be simplified as a voltage controlled current source supplying current to the output capacitor and load resistor. It is composed of one domain pole and a zero contributed by the output capacitor ES. The control-to-output transfer function is shown in the following equations: G vd V ( s) V f f z p OUT OMP ( s) A ( s) π ES VI π s π f s π f OUT ( ES ) OUT where: A VI 5 A/V is the load resistance. OUT is the output capacitance. ev. A Page of 3 z p

22 ES is the equivalent series resistance of the output capacitor. The uses a transconductance amplifier for the error amplifier to compensate the system. Figure 47 shows the simplified peak current-mode control small signal circuit. TOP BOT V OUT g m V OMP P A VI OUT ES V OUT Figure 47. Simplified Peak urrent-mode ontrol Small Signal ircuit The compensation components, and, contribute a zero, and the optional P and contribute an optional pole. The closed-loop transfer equation is as follows: s BOT g m TV ( s) Gvd( s) BOT TOP P P s s P The following design guideline shows how to select the compensation components,,, and P, for ceramic output capacitor applications.. Determine the cross frequency (f ). Generally, the f is between f SW / and f SW /6.. can be calculated using the following equation: π VOUT 0.6V g A m OUT VI f 3. Place the compensation zero at the domain pole (f P ). can be determined by ( ) ES OUT 4. P is optional. It can be used to cancel the zero caused by the ES of the output capacitor. P ES OUT The has a 0 pf capacitor internally at the OMPx pin; therefore, if P is smaller than 0 pf, no external capacitor is needed. ev. A Page of 3

23 DESIGN EXAMPLE This section explains design procedure and component selection as shown in Figure 50; Table provides a list of the required settings. Table. Dual Step-Down D-to-D egulator equirements Parameter Specification hannel Input Voltage.0 V ± 0% Output Voltage V OUT. V Output urrent I OUT 3 A Output Voltage ipple ΔV OUT_IPPLE mv Load Transient ±5%, 0.5 A to 3A, A/µs hannel Input Voltage.0 V ± 0% Output Voltage V OUT 3.3 V Output urrent I OUT 3 A Output Voltage ipple ΔV OUT_IPPLE 33 mv Load Transient ±5%, 0.5 A to 3 A, A/µs Switching Frequency f SW 500 khz OUTPUT VOLTAGE SETTING hoose a 0 kω top feedback resistor ( TOP ); calculate the bottom feedback resistor by using the following equation: BOT TOP V OUT To set the output voltage to. V, the resistor values are TOP 0 kω and BOT 0 kω. To set the output voltage to 3.3 V, the resistors values are TOP 0 kω and BOT. kω. UENT-LIMIT SETTING For 3 A output current operation, the typical peak current limit is 4.8 A. In this case, no ILIM is required. FEQUENY SETTING To set the switching frequency to 500 khz, use the following equation to calculate the resistor value, OS : OS ( kω) f 60,000 ( khz) SW Therefore, OS 00 kω. INDUTO SELETION The peak-to-peak inductor ripple current, ΔI L, is set to 30% of the maximum output current. Use the following equation to estimate the value of the inductor: L ( V V ) IN L OUT I f SW D For V OUT. V, Inductor L.4 µh, and for V OUT 3.3 V, Inductor L 5.3 µh. Select the standard inductor value of. µh and 4.7 µh for the. V and 3.3 V rails. alculate the peak-to-peak inductor ripple current as follows: I L ( V V ) IN L f OUT SW D For V OUT. V, ΔI L 0.98 A. For V OUT 3.3 V, ΔI L.0 A. Find the peak inductor current by using the following equation: I PEAK I OUT I L For the. V rail, the peak inductor current is 3.49 A, and for the 3.3 V rail, the peak inductor current is 3.5 A. The rms current through the inductor can be estimated by I MS I I L OUT The rms current of the inductor for both. V and 3.3 V is approximately 3.0 A. For the. V rail, select an inductor with a minimum rms current rating of 3.0 A and a minimum saturation current rating of 3.49 A. For the 3.3 V rail, select an inductor with a minimum rms current rating of 3.0 A and a minimum saturation current rating of 3.5 A. Based on these requirements, for the. V rail, select a. µh inductor, such as the Sumida DH05NP-N, with a D 7. mω; for the 3.3 V rail, select a 4.7 µh inductor, such as the Sumida DH05NP-47N, with a D.3 mω. OUTPUT APAITO SELETION The output capacitor is required to meet the output voltage ripple and load transient requirement. To meet the output voltage ripple requirement, use the following equation to calculate the ES and capacitance: OUT _ IPPLE ES V I L 8 f V L SW OUT _ IPPLE I OUT _ IPPLE For V OUT. V, OUT_IPPLE 0 µf and ES mω. For V OUT 3.3 V, OUT_IPPLE 7.7 µf and ES 3 mω. To meet the ±5% overshoot and undershoot requirement, use the following equation to calculate the capacitance: OUT _ OV OUT _ UV STEP ( V V ) V OUT K OV I OUT _ OV L KUV ISTEP L OUT ( VIN VOUT ) VOUT _ UV For estimation purposes, use K OV K UV. For V OUT. V, use OUT_OV 9 µf and OUT_UV µf. For V OUT 3.3 V, use OUT_OV 54 µf and OUT_UV 0 µf. ev. A Page 3 of 3

24 For the. V rail, the output capacitor ES needs to be smaller than mω, and the output capacitance needs to be larger than 9 µf. It is recommend that three pieces of 00 µf/x5/6.3 V ceramic capacitor be used, such as the GM3E60J07ME0 from Murata, with an ES mω. For the 3.3 V rail, the ES of the output capacitor must be smaller than 3 mω and the output capacitance must be larger than 54 µf. It is recommended that two pieces of 47 µf/x5/6.3 V ceramic capacitor be used, such as the Murata GM3E60J476ME0, with an ES mω. LOW-SIDE MOSFET SELETION A low DSON N-channel MOSFET is selected for high efficiency solutions. The MOSFET breakdown voltage needs to be greater than. V, and the drain current needs to be greater than. V I LIMIT. It is recommended that a 30 V, N-channel MOSFET be used, such as the FDS8880 from Fairchild. The DSON of the FDS8880 at a 4.5 V driver voltage is mω, and the total gate charge is n. OMPENSATION OMPONENTS For better load transient and stability performance, set the cross frequency, f, to f SW /0. In this case, f SW is running at 500 khz; therefore, the f is set to 50 khz. For the. V rail, the 00 µf ceramic output capacitor has a derated value of 64 µf. P π.v 3 64 μf 50kHz 80.4 kω 0.6 V 300 μs 5A/V ( 0.4Ω 0.00 Ω) 3 64μF 957 pf 80.4 kω 0.00 Ω 3 64μF.4 pf 80.4 kω hoose standard components, 8 kω and 000 pf. No P is needed. Figure 48 shows the. V rail bode plot at 3 A. The cross frequency is 49 khz and the phase margin is 59. MAGNITUDE (db) PHASE (Degrees) For the 3.3 V rail, the 47µF ceramic output capacitor has a derated value of 3 µf. P π 3.3V 3 μf 50 khz 73.7 kω 0.6V 300 μs 5A/V (. Ω 0.00 Ω) 3 μf 956 pf 73.7 kω 0.00 Ω 3 μf pf 73.7 kω hoose standard component values of 75 kω and 000 pf. No P is needed. Figure 49 shows the 3.3 V rail bode plot at 3 A. The cross frequency is 59 khz and phase margin is 6. MAGNITUDE (db) k 0k 00k M FEQUENY (Hz) Figure 49. Bode Plot for 3.3 V ail SOFT STAT TIME POGAMMING The soft start feature allows the output voltage to ramp up in a controlled manner, eliminating output voltage overshoot during soft start and limiting inrush current. The soft start time is set to 3 ms. ISS T 0.6 V SS SS 3.5 μa 3ms 7.5nF 0.6 V hoose a standard component value of SS SS nf. INPUT APAITO SELETION A minimum 0 µf ceramic capacitor is required, placed near the PVINx pin. In this application, one piece of 0 µf, X5, 5 V ceramic capacitor is recommended. PHASE (Degrees) k 0k 00k M FEQUENY (Hz) Figure 48. Bode Plot for. V ail ev. A Page 4 of 3

25 EXTENAL OMPONENTS EOMMENDATION Table. ecommended External omponents for Typical Applications with 3 A Output urrent f SW (khz) (V) V OUT (V) L (µh) OUT (µf) TOP (kω) BOT (kω) (kω) (pf) P (pf) µf: 6.3 V, Sanyo 6TPD330M; 00 µf: 6.3 V, X5, Murata GM3E60J07ME0; 47 µf: 6.3 V, X5, Murata GM3E60J476ME0. ev. A Page 5 of 3