MIPI 技术及物理层测试的挑战. 是德科技 (Keysight) 携手 MIPI 联盟和 Synopsys 共同推动 MIPI 技术发展. Page 1

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1 MIPI 技术及物理层测试的挑战 是德科技 (Keysight) 携手 MIPI 联盟和 Synopsys 共同推动 MIPI 技术发展 Page 1

2 内容安排 第一部 MIPI 联盟简介 中国成员 规范框架以及未来走向 第二部 Synopsys 的 MIPI 相关 IP 技术及其与 UFS/SSIC/M-PCIe 的互操作性 第三部 MIPI 物理层发展规划以及电气特征测试方案

3 MIPI 联盟 移动及相关产业的接口规范 演讲人 MIPI 联盟 - 总经理皮特. 莱弗金 Copyright 2013 MIPI Alliance. All rights reserved.

4 MIPI 概述 MIPI 联盟是致力于发展移动及相关产业接口规范的国际组织 MIPI 规范为移动手机及其他设备的运行提供基础的接口解决方案 现代的移动生态系统包括平板电脑 笔记本电脑 以及其他设备 MIPI 联盟成立于 2003 年, 目前在世界范围内有 275 家企业成员 企业成员包括 : 手机设备制造商 外围设备制造商 软件提供商 半导体公司 应用程序处理器开发人员 知识产权提供商 测试和测试设备公司 相机 平板和笔记本电脑制造商 MIPI 有 14 个活跃的工作组 模拟控制接口 电池接口 相机 调试 展示 低延迟接口 LML 市场营销 实体 无线电频 前端 传感器 软件及其同类 测试工作组以及 UniPro 联盟已经推行了超过 45 项移动生态系统规范 MIPI 联盟的战略合作伙伴包括 : JEDEC, PCI-SIG, MEMS Industry Group, USB-IF, VESA Copyright 2014 MIPI Alliance. All rights reserved.

5 MIPI 联盟的 15 家中国 ( 包括香港 ) 的成员包括 还有 36 家来自台湾的公司没有列出 Copyright 2014 MIPI Alliance. All rights reserved.

6 我们将在上海举行年度会议 MIPI 联盟开放与演示日将于 10 月 9 日 (09:00 15:00) 在上海举行 向所有的非会员 会员 媒体和分析师免费开放 关于 MIPI 规范的演讲 ( 涉及物理层 传感器 SoundWire CSI 以及 DSI) 演示日将与开放日同期举行, 现场将演示各种 MIPI 产品 如果您对该活动感兴趣, 可通过以下网址在线注册 : Copyright 2014 MIPI Alliance. All rights reserved.

7 MIPI 系统图 Copyright 2014 MIPI Alliance. All rights reserved.

8 MIPI 规范架构包括 : 多媒体 数据 / 控制 跟踪调试 芯片间的通信 UFS - Storage DSI - Display CSI - Camera SLIMbus, SoundWire - Audio SPP - SneakPeek Protocol NIDnT - Narrow Interface for Debug & Trace TWP - Trace Wrapper Protocol STP - System Trace Protocol RFFE - RF Front End etrak - Envelope Tracking SPMI - Power Mgmt BIF - Battery UniPort-M (UniPro on M-PHY) LLI Low Latency Interface (on M-PHY) M-PCIe Mobile PCI Express (PCIe on M-PHY) SSIC SuperSpeed InterChip (USB3 on M-PHY) Copyright 2014 MIPI Alliance. All rights reserved.

9 关于 MIPI 实体规范的新闻稿将于 9 月 17 日发布 MIPI 联盟推出 MIPI C-PHY 与 D-PHY 的更新 新规范的发布将扩展 MIPI 联盟为移动及相关产业应用所提供物理层级规范的家族 今天 MIPI 推出新的 MIPI C-PHY 扩展了 MIPI 联合会的物理层级规范, 拓宽了生产商们的接口选择, 同时也为公司基于特定商业策略或技术要求的差异化产品设计, 提供了新的机遇 专为程序处理器连接相机和显示模块设计 更新了 1.2 版本的 D-PHY 以及 3,1 版本的 M-PHY 1.0 版本 MIPI C-PHY 1.2 版本的 D-PHY 以及 3,1 版本的 M-PHY 现在对 MIPI 联合会成员开放 Copyright 2014 MIPI Alliance. All rights reserved.

10 MIPI 联盟的未来 超越移动产业 移动产业影响社会中的一切 一切都变得更快 更小和更节能 MIPI 联盟将继续研发规范, 以充分利用移动设备技术的发展 Copyright 2014 MIPI Alliance. All rights reserved.

11 总结 在 2014~2015 这两年里, 中国将成为 MIPI 联盟的最新战略重点地区, 为更多想加入 MIPI 联盟的中国公司提供机会, 同时希望中国公司能够在 MIPI 未来发展方向上做出贡献 MIPI 联盟将于 10 月 9 日在上海举办首个中国开放和演示日 届时, 将对所有提前在线注册的 MIPI 会员和非会员, 媒体, 分析师以及相关企业 个人和业界专业人士免费开放 开放日将为 MIPI 的会员们提供一个公开交流的平台和机会, 并针对非会员和媒体设置了问答环节 我相信在未来,MIPI 联盟将会研发出更多先进的 更创新的标准和规范 Copyright 2014 MIPI Alliance. All rights reserved.

12 谢谢 如需了解更多关于 MIPI 联盟的常见问题以及会员申请等详情, 请按照以下方式联系 MIPI 联合会总经理皮特. 莱弗金先生 Peter Lefkin Managing Director Telephone: Copyright 2014 MIPI Alliance. All rights reserved.

13 内容安排 第一部 MIPI 联盟简介 中国成员 规范框架以及未来走向 第二部 Synopsys 的 MIPI 相关 IP 技术及其与 UFS/SSIC/M-PCIe 的互操作性 第三部 MIPI 物理层发展规划以及电气特征测试方案

14 Synopsys DesignWare MIPI IP Haopeng Liu September, 17,

15 DesignWare MIPI IP Connectivity IP Between Various ICs Applicatio n UFS Device SSIC \ M-PCIe Device UniPro UniPro M-PHY M-PHY M-PHY M-PHY M-PHY M-PHY SSIC \ M-PCIe Host UniPro UniPro Application UFS Host DSI Display CSI-2 SSIC / /M-PCIe Host Image Sensor M-PHY M-PHY M-PHY M-PHY SSIC / M-PCIe Device M-PHY 3G PHY M-PHY 3G PHY Companion IC SSIC M-PCIe Application Processor LLI LLI Baseband IC LLI DigRF v4 Master DigRF v4 DigRF v4 Slave 4G RF IC SSIC UFS M-PCIe DigRF 3G Master DigRF 3G DigRF 3G Slave Storage IC 2G/3G RF IC UniPort-M DSI Host CSI-2 Host ARA Module D-PHY D-PHY Current portfolio D-PHY D-PHY DSI Device CSI-2 Device

16 PPI Interface Block PPI Interface Block Optimized and Flexible D-PHY Supports 2.5G speeds, ½ the area and power D-PHY v1.2 specification 2.5Gbps/lane Power, Area and Performance Optimized Variety of configurations DSI Host, CSI2 Device CSI2 Host, DSI Device Different # of data lanes available Interoperable and Integrated with Synopsys CSI2 and DSI controllers Low risk and quick time to market Available in 16nm and 28nm Tx D-PHY DSI Host CSI2 Device Rx D-PHY CSI2 Host DSI Device D-PHY w/ PLL Rx D-PHY

17 DesignWare UFS v2.0 for Mobile Apps Future Proof, Interoperable Host and Device Solution Future Proof M-PHY, UFS IP UFS Software Drivers Linux, OS-less Source: Samsung presentation, JEDEC Mobile Forum May 2013 Power Modes Compact and Configurable UFS Host v2.00 Fully Verified, Gear3 UniPro v1.60 Fully Verified, Flexible Host and Device Customers Din C C Dout RMMI Prototyping System Deployed Silicon-Proven M-PHY HS-Gear3 B

18 Synopsys M-PHY Interoperable w/ UFS, SSIC, M-PCIe M-PCIe Controller and MIPI Gear3 M-PHY Compliant USB SSIC with M-PHY Interoperable with TWO different UFS devices

19 内容安排 第一部 MIPI 联盟简介 中国成员 规范框架以及未来走向 第二部 Synopsys 的 MIPI 相关 IP 技术及其与 UFS/SSIC/M-PCIe 的互操作性 第三部 MIPI 物理层发展规划以及电气特征测试方案

20 Page 20 MIPI 物理层测试的挑战 李凯

21 测试主题的内容安排 MIPI 物理层的发展 MIPI 物理层的电气特点物理层测试的挑战以及测试方案 发送端的测试 接收端的测试 回波损耗的测试总结

22 Keysight 的标准跟踪和应用项目计划 Our solutions are driven and supported by Agilent experts involved in international standards committees: Joint Electronic Devices Engineering Council (JEDEC) PCI Special Interest Group (PCI-SIG ) Video Electronics Standards Association (VESA) Serial ATA International Organization (SATA-IO) Serial Attached SCSI Committee (T10) USB-Implementers Forum (USB-IF) Mobile Industry Processor Interface (MIPI) Alliance Optical Communications And many others We re active in standard meetings, workshops, plugfests, and seminars. We get involved so you benefit with the right solutions when you need them

23 Keysight 的专家团队 - 我们理解您未来的需求 Rick Eads PCI-SIG Board Member Perry Keller JEDEC Board Member Thomas Dippon HDMI Forum Board Member Jim Choate USB-IF Compliance Committee USB 3.0 Electrical Test Spec WG Min-Jie Chong SATA PHY/LOGO, SAS T10, MIPI PHY/CTS Contributor Brian Fetz DisplayPort Phy CTS Editor VESA Board Member Keysight maintains engagement in the top high tech standards organizations

24 MIPI 的物理层 协议层以及承载的应用 Application Protocol Standard CSI-2 DSI-1 DigRF v3 DigRF v4 CSI-3 DSI-2 UniPro UFS LLI SSIC M-PCIe Physical Standard D-PHY C-PHY M-PHY

25 MIPI 物理层标准的最新变化 M-PHY Gear 4 Double the data rate of M-PHY Gear 3 (~5.8Gbps) Data rate will increase to ~11.6Gbps Variable M-PHY data rate Current fixed rate is inefficient and high overhead D-PHY 1.2 and 2.0 Increase data rate from 1.5Gbps up to 3.5Gbps Add RX deskew (burden at RX) Support up to 8 lanes per clock C-PHY (previously known as 3-Phase D-PHY) 3-wire signal architecture, vs. 2-wire differential used in D-PHY Increase the number of bits per symbol (~2.28 bit/symbol) Projected rate at 2.5GSym/s (effective data rate of ~5.7Gbps)

26 测试主题的内容安排 MIPI 物理层的发展 MIPI 物理层的电气特点物理层测试的挑战以及测试方案 发送端的测试 接收端的测试 回波损耗的测试总结

27 D-PHY 物理层的特点高速模式和低功耗模式 High speed mode, Differential signaling, 100 ohm termination, source synchronous with double data rate clocking Low power mode Unterminated, not differential, clock embedded within data

28 M-PHY 物理层的特点高速模式和低速模式 R T TXDP RXDP R T Z HI V LD RX R T R T Z HI TX TXDN RXDN Terminations High Speed NRZ (HS) and Lower Speed (LS) modes - Common LS mode: Pulse Width Modulation (PWM) PWM Scheme Always differential and 8b/10b coded High and low voltage swing operations Terminated (100 ohm) or not terminated operation

29 C-PHY 物理层的特点曾被称为 3 相 D-PHY 3-wire (trio A, B, C) signal represents a lane vs. 2-wire in D-PHY New encoding scheme to increase the number of bits per symbol (~2.28bit/symbol) Embedded clock recovered from each symbol transition Signal is transmitted single-ended but received using differential receivers Reuse LP mode defined in D-PHY D-PHY 10-wire signals C-PHY 9-wire signals (3-trios)

30 C-PHY 的信号特点高速信号的波形 Transmit: A, B and C Receive: A-B, B-C and C-A

31 C-PHY 的眼图和模板高速信号测试 Strong-1 Weak-1 0V threshold Weak-0 Strong-0 Clock is recovered from the earliest edge of a symbol transition. A delay circuit with negative hold time is used to sample data. Supposed to be more resistant to noise and jitter on the system. 3 1

32 C-PHY 测试中还有待解决的一些问题 What are the jitter and eye mask definitions? Availability of dynamic termination board required for TX test and calibration of the RX stress signal. What are the test patterns to use for test? How is error detection achieved since no 3-wire ED (error detector) is available? Implement error counter in DUT and provide side-band interface for error read-out What is the right figure of merit instead of BER for RX test?

33 内容安排 MIPI 物理层的发展 MIPI 物理层的电气特点物理层测试的挑战以及测试方案 发送端的测试 接收端的测试 回波损耗的测试总结

34 发送端测试的挑战 Test board design for chipset Dynamic terminations between operation modes Probe noise, response and loading Huge list of conformance test requirement Multilane testing with oscilloscope limited channels Removing test setup loss from measurement Correlating physical and protocol issues

35 适用于芯片 模组测试的测试板 Test Vehicle Board (TVB) TVB PHY Chip Page 35

36 不同工作模式下的动态端接 Reference Termination Board (RTB) TVB PHY Chip Reference Termination Board (RTB) terminates the signals dynamically according to the operation termination requirement. RTB SMA Probe D-PHY and C-PHY RTB, as well as fixed M-PHY load board are available. testing/mipi/fixtures.php

37 探头的噪声 频响和负载影响 InfiniiMax Probes Probes with low noise and loading (as low as 70 ff) are available. S-parameter stored in the probe amplifier. PrecisionProbe can be used for AC calibration. Flexible probe accessories: o Solder-in probe head o ZIF probe and tips o Socket head o Browser o 2.92mm/SMA head Example 25 GHz ZIF probe and tip P a

38 MIPI 信号的探测方法 D-PHY and C-PHY probing option: 1. Solder down on dynamic load (50-ohm and open) M-PHY probing options: 1. Solder down on 100-ohm differential load 2. Direct connection into scope 3. SMA probe head Notes: Direct DC connection is recommended if it doesn t impact transmitter performance by comparing results between DC (without cap) and AC (with cap) connections. If performance decreases, use SMA probe head.

39 M-PHY HS-G3 的信号测试对比测试条件 : 发送端没有预加重, 没有传输通道 Direct AC-coupled into scope front-end Direct DC-coupled into scope front-end InfiniiMax II 1169A SMA Probe InfiniiMax III N2800A SMA Probe

40 M-PHY HS-G3 的信号测试对比测试条件 : 发送端没有预加重, 经过 CH1 参考通道 Direct AC-coupled into scope front-end Direct DC-coupled into scope front-end InfiniiMax II 1169A SMA Probe InfiniiMax III N2800A SMA Probe

41 大量的一致性测试项目 Signal Group Test Parameters Signal Group Test Parameters Static Common Mode Voltage (Vcmtx) Thevenin Output High Voltage Level (VOH) HS Clock PHY High-Speed Clock Electrical Transmitter Characteristics Vcmtx Mismatch Differential Voltage (VOD) Differential Voltage Mismatch Single-Ended Output High Voltage (VOHHS) Common-Level Variations Above 450MHz (VCMTX(HF)) LP Clock / Data PHY LP TX Electrical Characteristics Thevenin Output Low Voltage Level (VOL) 30%-85% Post-EoT Rise Time (TREOT) 15%-85% Fall Time (TFLP) 15%-85% Rise Time (TRLP) Pulse Width of LP TX Exclusive-OR Clock (TLP-PULSE-TX) Common-Level Variations Between MHz (VCMTX(LF)) Period of L TX Exclusive-OR Clock (TLP-PER-TX) 20%-80% Rise Time (tr) Slew Rate Vs. CLoad HS Data PHY High-Speed Data Electrical Transmitter Characteristics 20%-80% Fall Time (tf) Static Common Mode Voltage (Vcmtx) Vcmtx Mismatch Differential Voltage (VOD) Differential Voltage Mismatch Single-Ended Output High Voltage (VOHHS) Common-Level Variations Above 450MHz (VCMTX(HF)) Common-Level Variations Between MHz (VCMTX(LF)) 20%-80% Rise Time (tr) 20%-80% Fall Time (tf) LP-HS Data Timing Global Operation for Data Signals LP-HS Clock Timing Global Operation for Clock TLPX LP Exit: DATA TX THS-PREPARE LP Exit: DATA TX THS-PREPARE+THS-ZERO HS Exit: DATA TX THS-TRAIL HS Exit: DATA TX TEOT HS Exit: DATA TX THS-EXIT LP Exit: CLK TX THS-EXIT LP Exit: CLK TX TLPX LP Exit: CLK TX TCLK-PREPARE LP Exit: CLK TX TCLK-PREPARE+TCLK-ZERO LP Exit: CLK TX TCLK-TRAIL HS Clock- Data Timing HS Data-Clock Timing HS Exit: LK TX TEOT HS Clock Instantaneous (UIinst) HS Clock Rising Edge Alignments to First Payload Bit Data-to-Clock Skew (TSKEW(TX))

42 D-PHY 物理层测试时间参数测试 MIN: 50ns MIN: 40ns+4*UI MAX: 85ns+6*UI MIN: 145ns+10*UI- T HS-Prepare 1GB/s: UI=1ns HS-PREPARE: MIN: 44ns MAX: 91ns HS-ZERO: MIN: 64ns = 145ns+10*1ns-91ns MAX: 35ns MAX: 105ns+n*12*UI MAX: 35ns+4*UI MIN: max{n*8*ui, 60ns+n*4*UI} MIN: 40ns MAX: 55ns+4*UI n=1 forward direction HS mode n=4 backward direction HS mode UI: 1GB/s = 1ns MIN: 100ns

43 M-PHY CTS v3.0r14 要求的高速信号的测试项目 HS-TX Tests Continuo HS-G1 HS-G2 HS-G3 Burst us LA SA RT NT f_offset Yes Yes Yes Yes Yes Yes No Yes No PSDCM Info No No Yes No Yes Yes Yes No PREPARE_Length Yes Yes Yes Yes No Yes Yes Yes No VCM Yes Yes Yes Yes No Yes Yes Yes No VDIF_DC Yes Yes Yes Yes No Yes Yes Yes No G1/G2 TEYE_TX, VDIF_AC Yes Yes No Yes Yes Yes Yes Yes No G3 TEYE_TX, VDIF_AC No No Yes Yes Yes Yes Yes Yes No TR_TF_HS Yes Yes Yes Yes No Yes Yes Yes No L2L_SKEW Yes Yes Yes Yes No Yes No Yes No SR_DIF[MAX] Yes No No Yes No Yes Yes Yes No SR_DIF[MIN] Yes No No Yes No Yes Yes Yes No SR_DIF Monotonicity Yes No No Yes No Yes Yes Yes No SR_DIF Resolution Yes No No Yes No Yes Yes Yes No TINTRA_SKEW Yes Yes Yes Yes Optional Yes Yes Yes No TPULSE Yes Yes Yes Yes No Yes Yes Yes No TJ Yes Yes Yes No Yes Yes Yes Yes No STTJ Yes Yes Yes Info Yes Yes Yes Yes No DJ Yes Yes Yes No Yes Yes Yes Yes No STDJ Yes Yes Yes Info Yes Yes Yes Yes No

44 M-PHY 眼图和抖动的测试 No de-emphasis in G1 and G2. G3 requires de-emphasis. Nominal 3.5dB de-emphasis for LA and SA swing Nominal 6dB de-emphasis for LA swing G4 requires CTLE and one-tap DFE at receiver. Different BER 1E-10 eye mask definition for G1, G2 and G3. G1 0.2UI opening between UI No channel 0.2UI eye opening at 0.5UI No channel G4 leverages G3 reference channels and also to include reference package model. Diamond mask at 0.5UI Embed CH1 SA and CH2 LA swing TJ, DJ, STTJ and STDJ are normative with continuous signal. DJ and STDJ are informative with burst using TIEpp method.

45 C-PHY 物理层的测试大量的时间参数测试 来源于 D-PHY 但又不太一样

46 C-PHY 上升 / 下降时间 眼图和抖动的测试 Rise/fall time measured between -58mV to 58mV thresholds on S-W transitions. W- W transitions are slowest, but S-W are critical to eye-opening. Eye mask defined at the receiver. Embed 6-port model IL/RL and CTLE, as well as Xtalk from adjacent channels. Jitter still undefined. Common point replaces common mode test.

47 自动的信号一致性测试软件 Configure the Device Under Test Select Tests. Automatically generate test report.

48 多通道测试 Limited oscilloscope channels prevent full automated testing of multilane MIPI interface. Overcome with switch matrix, which automates lane switching and test. Switch matrix calibration to remove loss and skew. 2x6 (1x6 differential) Switch Matrix Agilent U3020AS26 4 differential lanes configured DSA X-Series 16GHz Agilent Oscilloscope

49 消除测试电缆 探头损耗带来的影响 Frequency content with loss compensation applied (Blue) Computed insertion loss gain function based on measured S21 (Yellow) Original signal frequency content (green) 使用示波器和矢网的去嵌入功能 (InfiniiSim) 或者示波器的 TDT 修正功能 (PrecisionProbe)

50 物理层和协议层的联合调试在示波器里进行 MIPI 的协议解码 ( 举例 : UFS / UniPro) Simultaneous show UFS and UniPro packet decode on analog waveform. Shows whether the bits are correctly received with the CRC verification. Move back and forth between UFS and UniPro packets

51 通过 CRC 校验进行物理层和协议层的联合调试 Calm color shows the packets are received correctly with no error when the computed CRC matches CRC transmitted in the packet. Signal integrity and protocol are good. Bright color warns the packets are received incorrectly when the computed CRC and CRC transmitted in the packet do not match. This could be related to signal integrity or protocol issues. User can go in to debug the issues.

52 测试主题的内容安排 MIPI 物理层的发展 MIPI 物理层的电气特点物理层测试的挑战以及测试方案 发送端的测试 接收端的测试 回波损耗的测试总结

53 接收端的测试 Stressed Signal Stressed Signal Generator RJ+DJ+ISI Rx Loop Back Tx Chip Error Detector Jitter Cocktail RJ DJ ISI

54 接收端测试的挑战 Receiver stress signal generation - Various timing requirements - Complex jitter cocktail Programming designs into test modes - No standardization in the PHY spec - Method varies by the protocol Error detection with different protocols - No standardization - Specific method defined in protocol spec, not in PHY spec - Not mandatory (optional normative / recommendation) - Asymmetrical lane configuration

55 Internal Loopback or Error counter M-PHY 接收端测试的连接 产生压力信号并根据 CTS 要求进行校准 RT-Oscilloscope 580mm 45mm 100 Ohm Differential Probe 535mm BERT Pattern Generator w/ TTCs ISI Conformance Channel Replica Trace TP RX DUT ASIC Breakout Trace Test board with Replica Traces creating test point (TP) for calibration equivalent to the ASIC-input pins Ref Clk TX Custom Test Board

56 使用 M8020A 进行 M-PHY 接收端测试的连接 J-BERT M8020A RT-Oscilloscope N M- RX M-TX 100 Ohm Differential Probe loop back Err Ctr 1:1 match of CTS proposed set-up with actual Agilent J-BERT set-up ISI conformance channel relaized through N SATA ISI trace (2)

57 D-PHY 接收端测试的典型配置需要通过合路的方式同时产生 HS 和 LP 的信号 DUT 举例 : 支持 1 对时钟线和 2 对数据线的基于 的配置

58 产生 D-PHY 的压力信号的例子

59 C-PHY 接收测试设置 (One Trio) A C B D A B C Only 3 of 4 available channels needed to drive a C-PHX lane 4 th channel available for any aux signal D Two M8190A AWG modules + one M8192A sync module is needed to drive the four signals M8190A AWG is flexible enough to support C-PHY waveforms without external circuitry

60 1Gsym/s 的 C-PHY 信号 -LP 和 HS 状态的切换 Sequence of low power and hi speed signal separated (offset-shifted, left) and overlaid (same offset, right)

61 众多的的接收容限测试项目 CTS chapter Title AT HSmode LSmode (PWM) HS-RX Differential DC Input Voltage Amplitude Tolerance HS-RX Accumulated Differential Input Voltage Tolerance HS-RX Common Mode Input Voltage Tolerance HS-RX Differential Termination Enable Time HS-RX Differential Termination Disable Time HS-RX Lane-to-Lane Skew (TL2L-SKEW-HS-RX) HS-RX Receiver Jitter Tolerance HS-RX Frequency Offset Tolerance HS-RX PREPARE Length Capability Verification HS-RX Sync Length Capability Verification PWM-RX Differential DC Input Voltage Amplitude Tolerance PWM-RX Accumulated Differential Input Voltage Tolerance PWM-RX Common Mode Input Voltage Tolerance PWM-RX Differential Termination Enable Time PWM-RX Differential Termination Disable Time PWM-RX Lane-to-Lane Skew (TL2L-SKEW-PWM-RX) PWM-RX Receive Bit Duration Tolerance PWM-RX Receive Ratio, PWM-G1 and Above PWM-RX Receive Minor Duration in PWM-G0 -

62 N5990A 接收容限自动测试软件 Parameters of selected item Calibrations - HS, NRZ (RT) - LP, PWM (NT) RX tests - HS, NRZ (RT) - LP, PWM (NT)

63 把被测件设置成测试模式的方法 使用芯片厂商方法或通过总线协议 ( 带帧结构 ) M-PHY packet framing Page 63

64 M-PHY 的数据帧生成软件 支持 并行误码仪和 N4903B 串行误码仪

65 基于 M-PHY 协议的错误检查 Challenges with different protocols: - No standardization - Specific method defined in protocol spec, not in PHY spec - Not mandatory (optional normative / recommendation) - Asymmetrical lane configuration (e.g. 2x HS upstream / 1x LS downstream) Various error detection methods: - IBER (=Internal Bit Error Ratio) - PPI (=Parallel Processor Interface i.e. parallel data output) - Line Loopback (i.e. bit level loopback) - Logic Loopback (i.e. protocol layer loopback) - Visual display inspection (backup solution for display testing) Not all MIPI applications have settled on preferred test option

66 错误检查方法的选择 Use BERT ED for bit comparison and error counting when loopback is implemented Use BERT ED (for capture, upload, postprocess) or Oscillospe (w/ serial decode) - For reading counters provided by protocol - When testmode with built in TPV is provided Use external PC to read customer provided IBERReader DLL with counter results How can error counting be realized? Loopback Mode supported? no Error counter (TPV) implemented? yes Result transmitted via TX? no yes no yes Connect BERT ED for error counting Loopback is not always possible Read protocol s Packet- and ErrorPacket- Counter s (UniPro) not all MIPI links are symmetrical, i.e. mode and gear settings for the involved M-RX and M-TX are not commonly supported. applications (protocols) residing on M-PHY optimize their support for testing and therefore mandatory requirements for testing may not include a support for loopback mode Connect BERT-ED for capture, upload & post-processing (LLI) Use IBERReader DLL to communicate to computer Getting results of internal TPV either through a (low speed) M_TX or IBERReader DLL or (proprietary) programming interface of the DUT

67 不同应用中进行 M-PHY 接收端测试的方法 Test configuration DUT DigRF 4 UniPro LLI SSIC Single lane and multi lane test possible M- RX M-TX loop back In a multi-lane configuration all lanes must be tested simultaneously M- RX M-TX Err Ctr Test one lane at a time M- RX M-TX Err Ctr Test one lane at a time M- RX M-TX loop back Err Ctr Error Detection Method Loopback, options: BERT error detector can only be used if there is no re-timing DigRF 4 Exerciser Custom method, either internal error counter (IBER) or golden receiver Internal error counter (IBER): oscilloscope to capture counter readings Internal error counter (IBER): oscilloscope to capture counter readings Internal error counter (IBER) and Loopback (both needed for full test coverage) The internal error counter can be read either with BERT error detector or with oscilloscope Loopback requires J-BERT B SER mode Instrument recommendatio n ParBERT, J-BERT B (1 or 2 lanes) ParBERT, J-BERT B (1 or 2 lanes) ParBERT, J-BERT B J-BERT B

68 C-PHY 接收端测试方法的进展 Signal calibration still to be determined. Error counting always done with internal counter No loopback mode No need to have a C-PHY conformant ED No CTS available yet (work has not yet started) No automation SW available yet

69 测试主题的内容安排 MIPI 物理层的发展 MIPI 物理层的电气特点物理层测试的挑战以及测试方案 发送端的测试 接收端的测试 回波损耗的测试总结

70 回波损耗对信号的影响 A portion of the transmitted signal is reflected due to impedance mismatches. If the signal path is not impedance matched, reflections can cause eye closure. Tx t Rx Transmitter Termination Effects Transmitter Impedance NOT Matched Transmitter Impedance Matched

71 S 参数测和阻抗 回波损耗测试发送和接收设备的回波损耗要在上电状态下测试 t t The TX is required to transmit a repetitive pattern when characterizing its return loss.

72 用带 TDR 选件的 ENA 矢网进行回波损耗例子 Single-ended Impedance 1 Single-ended Impedance 2 Differential Return Loss Common-mode Return Loss VBA Macro automatically sets the limit lines, based on your input parameters. Differential Impedance TDR application helps trouble shooting with the simple and intuitive userinterface. All Measurements in One Screen

73 测试主题的内容安排 MIPI 物理层的发展 MIPI 物理层的电气特点物理层测试的挑战以及测试方案 发送端的测试 接收端的测试 回波损耗的测试总结

74 Keysight 公司 MIPI 测试的整体解决方案 Transmitter Characterization Receiver Characterization Impedance/Return Loss Validation Protocol Stimulus and Analysis DSAQ93204A Infiniium N4903B/M8020A JBERT E5071C ENA Option TDR U4421A D-PHY CSI-2 / DSI Analyzer and Exerciser U4431A M-PHY Analyzer (UFS, UniPro, CSI-3, SSIC, M-PCIe) U7238B D-PHY, U7249B M-PHY, N5467B C-PHY UDA M8190 AWG DCA 86100D Wideband sampling oscilloscope InfiniiMax Probes Switch matrix N5465A InfiniiSim N2809A PrecisionProbe 81250A ParBERT N5990A Automated characterization N1055A TDR/TDT Scope Protocol Decoder N8802A CSI-2 / DSI N8807A DigRF v4 N8808A UniPro N8818A UFS N8809A LLI N8819A SSIC N8820A CSI-3 N8824A RFFE 54754A TDR/TDT Industry s highest analog bandwidth, lowest noise floor/sensitivity, jitter measurement floor with unique cable/probe correction Highest precision jitter lab source with automated compliance software for accurate, efficient, and consistent measurement Precision impedance measurements and S-Parameter capability Fast upload and display, accurate capture, intuitive GUI and customizable hardware. Correlate physical and protocol layer.

75 总结 Mobile applications are driving the needs for higher performance and lower power usage. D-PHY is widely adopted. D-PHY extension and C-PHY are added to increase performance. M-PHY will be widely adopted by different applications, including standards outside of the MIPI ecosystem. Keysight is driving specification and testing dicussions within MIPI workgroups and the test houses, as well as other key standard ecosystems.

76 参考资料 MIPI total solution page Application note: Published white paper at Microwave Journals: Multilane MIPI Testing with MW Switches Switch calibration and correction application notes: How to Test a MIPI M-PHY High-Speed Receiver Using Microwave Switches When Testing High Speed Serial Digital Interfaces S-parameter Requirements for Oscilloscope De-embedding PrecisionProbe for Bandwidths up to 33 GHz Method of Implementation: Integrated switch matrix hardware: D-PHY Return Loss / Cable ENA measurements M-PHY Return Loss / Cable ENA measurements Agilent U3020AS26 BitifEye 2100 Series

77 谢谢参加!

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