Designing Chargers and Adapters with LinkSwitch -LP

Transcription

1 Designing Chargers and Adapters with LinkSwitch -LP

2 Seminar Agenda Introduction Power Integrations The Opportunity Introducing LinkSwitch-LP Features and Operation LinkSwitch-LP Performance Designing with LinkSwitch-LP LinkSwitch-LP Hints and Tips LinkSwitch-LP Design Examples Additional Features of LinkSwitch-LP LinkSwitch-LP Quick Design Checklist Slide# 2

3 Power Integrations Overview Leader in high voltage monolithic power conversion ICs > 1.6 billion devices shipped Revolutionary products Proven quality and delivery performance Pioneers in energy efficiency (EcoSmart ) Slide# 3

4 Global Applications Support Fully Equipped Applications Labs 55+ Application Engineers Worldwide Slide# 4

5 The Opportunity Companies that get CEC/Energy Star/CECP compliant power supplies to market quickly have a significant competitive advantage

6 Energy Efficiency Drives Redesign Energy efficiency has become a key design requirement Up to 60% of existing solutions don t meet new standards Harmonized EPS energy efficiency standards are here Power Integrations power conversion ICs enable compliance with all current and proposed standards See appendix A for details on energy efficiency standards Slide# 6

7 Existing Linears vs No-load Standards Slide# 7

8 Existing Linears vs Active-mode Standards 0.09 x Ln(P OUT ) } Slide# 8

9 High Efficiency at Light Load is Critical Active-mode efficiency is the average of P OUT at 25, 50, 75 and 100% load Consistent efficiency over load range is more valuable than high full load efficiency Control schemes that reduce frequency with load are optimal Power supplies 1 and 2 are rated at 5 W output power P OUT Slide# 9

10 Power Supply Output Characteristics PI has solutions for all VI characteristics VERY LOOSE CV/CC LOOSE CV/CC LOOSE CV ONLY TIGHT CV ONLY TIGHT CV / LOOSE CC TIGHT CV / TIGHT CC Slide# 10

11 PI Device Selection for Chargers/Adapters Slide# 11

12 LinkSwitch-LP Features and Operation

13 LinkSwitch-LP Pin Function Descriptions DRAIN (D) Pin: Power MOSFET drain and highvoltage startup BYPASS (BP) Pin: Connection point for 0.1 µf external bypass capacitor FEEDBACK (FB) Pin: Provides feedback to controller and a reference voltage for bias winding feedback SOURCE (S) Pin: Power MOSFET source and controller ground reference Slide# 13

14 LinkSwitch-LP Power Levels and Design Flexibility 1.9 W, 2.5 W or 3 W solutions can be made from one design Two standard transformers allow a V OUT range of 4 12 V Solutions that deliver up to 2.5 W can be Clampless Slide# 14

15 LinkSwitch-LP Device Family Features Easy-to-design, low parts count solutions Primary-side controller limits output current beyond the peak power point no current sense resistors required Fully fault protected thermal, short-circuit and open-loop Operates over universal input voltage range ( VAC) Slide# 15

16 LinkSwitch-LP System Cost Benefits Switching frequency jitter enables simple EMI filter and the inductor to be used as a Filterfuse Tight toleranced, low, current limit enables Clampless primary winding Internal, high-voltage, current source eliminates start-up circuitry Internal current sense circuit eliminates sense resistor Low-cost, transformer derived feedback Output voltage set by resistor divider and accurate FB pin ON/OFF control: no frequency compensation components required Optimized for lowest cost, loosely regulated, CV/CC applications Typical circuit diagram not a simplified schematic Slide# 16

17 Start-up: Charging BP Pin Capacitor BP pin capacitor is charged to 5.8 V from DRAIN via internal high voltage current source No external resistor string or start-up circuit required Slide# 17

18 Start-up: Drain Starts Switching When the BP pin reaches 5.8 V, the MOSFET starts switching Output voltage begins to rise As output voltage rises, no switching cycles are skipped and current into the FB pin rises 5.8 V Energy stored in BP pin capacitor powers the IC while the MOSFET is on. The current source recharges the BP pin capacitor while the MOSFET is off Slide# 18

19 LinkSwitch-LP Start-up Waveforms BP pin voltage Charging BP pin capacitor LinkSwitch-LP skipping switching cycles to keep output voltage in CV regulation Slide# 19

20 LinkSwitch-LP CV Operation ON/OFF control regulates V OUT from no-load to rated load Feedback signal sampled each clock cycle MOSFET current ramps to I LIMIT every enabled (ON) switching cycle Each ON cycle delivers a fixed (maximum) amount of energy When > 70 µa flows into FB pin, MOSFET switching is disabled (OFF) Effective switching frequency reduces proportionally with the load Fixed energy per cycle keeps no-load frequency & consumption low Slide# 20

21 LinkSwitch-LP CC and Auto-restart From peak power point to auto-restart, falling FB pin voltage causes oscillator frequency to drop, limiting output current and power 1.69 V 0.8 V At auto-restart, FB pin voltage drops below the V FB(AR) threshold, limiting output power to 12% of peak power Slide# 21

22 LinkSwitch-LP Auto-restart Waveforms When FB pin voltage < V FB(AR) for > 100 ms, auto-restart initiates and MOSFET switching is disabled for 800 ms then re-enabled for 100 ms Fault removed Auto-restart ends whenever FB pin voltage > V FB(AR) Auto-restart limits average output current 12% rated output Slide# 22

23 LinkSwitch-LP Performance

24 LinkSwitch-LP Output Characteristic VAC 265 VAC Output Voltage (V) Auto-Restart Output Current (A) Slide# 24

25 LinkSwitch-LP CV Mode vs Unregulated Linear 1.8 W unregulated linear output envelope ( VAC) 2 W LinkSwitch-LP output ( VAC) LinkSwitch-LP line regulation ( VAC): < ± 1% at rated output Unregulated linear line regulation ( VAC): +15/ 58% at rated output Linear does not meet rated output power (6 V, 300 ma) below 115 VAC Slide# 25

26 LinkSwitch-LP CC vs Unregulated Linear 9 Output Voltage (V) Rated output power 2 W LinkSwitch-LP 1.8 W Linear May be dangerous to the load Output Current (A) Auto-restart limits overload current, protecting both supply and load. Input power 400 mw at auto-restart Input power 28 W, protected by onetime thermal fuse Slide# 26

27 LinkSwitch-LP Output Ripple vs Unregulated Linear 848 mv pk-pk 144 mv pk-pk 200 mv, 2 ms/div Unregulated Linear, 6 V, 1.8 W adapter 115 VAC, Full Load 200 mv, 2 ms/div LinkSwitch-LP 6 V, 2 W adapter 115 VAC, Full Load Measured with resistive load at end of output cable Slide# 27

28 LinkSwitch-LP Active Mode Efficiency vs Unregulated Linear Linear transformer design does not meet CEC requirement Slide# 28

29 LinkSwitch-LP Conducted EMI Results dbµv 80 1 MHz 10 MHz LIMIT CHECK PASS 1 QP CLRWR 2 AV CLRWR 70 EN55022Q 60 EN55022A 50 SGL TDF khz 30 MHz Worst-case measurement on EP-85 No Y-capacitor used (adding improves unit-to-unit repeatability) Slide# 29

30 Designing with LinkSwitch-LP

31 LinkSwitch-LP Input Stage Selection Half-wave rectified Filterfuse option may still be cost effective >1 W Component value details provided in AN-39 Slide# 31

32 Filterfuse for Half-wave Rectification Only Fast Diode (t rr ~150 ns) Short circuit current AC IN Standard (slow) Diode L1 acts as a fuse if C1, D IN1 or D IN2 fail shorted L1 provides no protection if any diode fails shorted Input inductor functions both as an EMI filter and a fuse Only possible with half-wave rectification Field feedback: designs using Filterfuse have passed safety tests Slide# 32

33 Filterfuse Requires a Fast Diode 1N4007 & 1N x 1N4007 Increases EMI and variability at low frequencies Stops ringing caused by reverse current through inductor Second capacitor normally prevents this in standard π filter configuration Reduces measurement variation due to LISN characteristics Slide# 33

34 FilterFuse Inductor Selection Temperature rise ~20 C at 90 VAC Select inductor current rating near to the calculated input RMS current Reduces the amount of energy and current required to open circuit the inductor Verify that inductor temperature rise is acceptable at low-line Sleeve inductor with heatshrink tubing in manufacturing Tubing contains incandescent material at failure: required to meet safety Typical inductor specifications (often called radio frequency chokes) Epcos BC Series: 3300 µh, 62 ma, 59.5 Ω, part # B78148-S1335-J Slide# 34

35 LinkSwitch-LP Device Selection Select device based on output power and preferred core size Limiting flux density to 1500 Gauss will minimize audible noise Core power capability and audible noise both increase with flux density Slide# 35

36 Designing Clampless LinkSwitch-LP Solutions Primary capacitance and bias winding provide clamping Location of bias winding in winding order impacts effectiveness Slide# 36

37 LinkSwitch-LP Clampless Solutions 580 V PK Clampless design without bias winding V DS Increased leakage ringing without bias winding 265 VAC 550 V PK Clampless design with bias winding V DS 265 VAC Bias winding and C P clamp energy stored in leakage inductance Tight I LIMIT tolerance keeps peak drain voltage below 700 V (BV DSS rating of IC) Power limit of Clampless designs based on EMI results Slide# 37

38 LinkSwitch-LP Design Flexibility Output Voltage (V) Output Current (A) 7.5V 0.26A 90VAC 6V 0.21A 90VAC 4V 0.325A 90VAC 6V 0.33A 90VAC Only feedback resistor and/or LinkSwitch-LP device changed All other components were the same for all four designs Slide# 38

39 LinkSwitch-LP Standard Transformer Selection For designs <2 W, select 1 of 2 standard EE16 transformers Standard transformers include E-Shield for reduced EMI Full specifications in AN-39 Slide# 39

40 LinkSwitch-LP Standard Transformer Slide# 40

41 LinkSwitch-LP Standard Transformer Sources Standard transformers available from Falco Part #: E09077 Hical Part #: SIL6036 CWS Part #: CWS-T1-DAK85 Li Shin Part #: LSLA40342 Woo Jin Part #: SLP-2218P1 See website for contact information Custom transformer design instructions in AN-39 Design spreadsheet tool available in PI Xls (version 6.1.1) Can be used to design custom transformers for LinkSwitch-LP supplies Slide# 41

42 LinkSwitch-LP Output Diode Selection Sample Schottky and Ultrafast diodes for use in LinkSwitch-LP designs Diodes with lower reverse recovery times (t rr ) produce a steeper CC region Output diode DC current rating should be rated output current Slide# 42

43 LinkSwitch-LP Output Capacitor Selection Capacitor voltage rating must be > 1.25 x V O Capacitor ripple current rating > I RIPPLE (from PI Xls spreadsheet) Output capacitor I RIPPLE ratings are inversely proportional to temperature Example: A 105 C capacitor working at 85 C has an I RIPPLE factor of 1.7 Check manufacturer s datasheet for specific factors typical 2 W design typical 3 W design Slide# 43

44 Selecting Other Components Slow diode improves CC part of output VI characteristic Low cost 330 nf 50 V ceramic Low cost 0.1 µf 50 V ceramic Default values calculated in PI Xls design spreadsheet. R1 value may be adjusted to center output voltage Slide# 44

45 LinkSwitch-LP Design Tools Reference Design (Design Accelerator Kit) DAK-85: An operational, tested 2 W (EP-85) power supply A blank PCB and IC samples PI Expert Suite power supply design software LinkSwitch-LP datasheet Application Note AN-39 LinkSwitch-LP Design Guide Slide# 45

46 LinkSwitch-LP Hints and Tips

47 Limiting Open Loop Output Voltage 10.2 V OUT[PK] V IN : 265 VAC V OUT 2 V, 200 ms / div x 10 V, 0.5 mw Zener diode Auto-restart allows low cost 500 mw Zener for open loop protection Required in some specifications Auto-restart mode prevents Zener diode from overheating and failing If Zener used, pre-load resistor (R3) typically not required Slide# 47

48 Pre-load and Clamp Zener Selection Output Voltage (V) No pre-load 100 mw 265 VAC 10 V zener 101 mw 265 VAC 9.1 V zener 106 mw 265 VAC 575 ua / 16 k pre-load 107 mw 265 VAC 1 ma / 8 k pre-load 112 mw 265 VAC 2 ma / 4 k pre-load 120 mw 265 VAC ma / 2 k pre-load 141 mw 265 VAC (EP85) Output Current (A) Select pre-load for acceptable no-load voltage and input power Slide# 48

49 Bias Winding Placement and Regulation 9 (a) 8 7 Winding Order (a) 90 VAC Winding Order (a) 265 VAC Winding Order (b) 90 VAC Winding Order (b) 265 VAC Output Voltage (V) b a (b) Output Current (A) Placing bias winding away from primary improves regulation Slide# 49

50 Bias Winding Diode t RR Selection Output Voltage (V) Decreasing diode t RR D3: 1N4005, 90 VAC D3: 1N4005, 265 VAC D3: 1N4936, 90/265 VAC D3: UF4003, 90/265 VAC D3: 1N4148, 90/265 VAC Output Current (A) Slow recovery diodes (1N400x) give best CC regulation Reduces leakage inductance error in bias winding voltage Slide# 50

51 Feedback Resistor Value Selection 9 8 Best R2 value is 3 k 7 Output Voltage (V) R1/R2 values ½ EP-85 values R1/R2 values same as EP-85 R1/R2 values 2 x EP Output Current (A) High values for R1/R2 produce poorer CC regulation Low values for R1/R2 produce better CC regulation Low values for R1/R2 also increase no-load consumption Slide# 51

52 LinkSwitch-LP Layout Recommendations Keep drain trace short Maximize source area for good heatsinking Keep secondary away from IC DRAIN pin Place BP pin capacitor close to IC Keep output diode to output capacitor trace short Keep input stage away from IC DRAIN pin to minimize noise coupling Slide# 52

53 LinkSwitch-LP Design Examples

54 2 W Linear Replacement Using LNK564 Output Characteristic 8.5 V 5.5 V 900 ma Unregulated linear or approx CV/CC No-load consumption: < 0.15 W Average efficiency: > 60 % Component count: 14 No Y-capacitor (< 1µA leakage current) Slide# 54

55 1.3 W Linear Replacement Using LNK562 Same circuit as previous slide: only C1 and U1 where changed Output Characteristic 8.5 V 5.5 V 750 ma Unregulated linear or approx CV/CC No-load consumption: < 0.15 W Average efficiency: > 60 % Component count: 14 No Y-capacitor (< 1µA leakage current) Slide# 55

56 Typical LinkSwitch-LP Production Variation Minimum specified power point 100 randomly selected production units EP-85 Data taken at 25 C, at 85 VAC (blue traces) and 265 VAC (red traces) Shows that raising the nominal VO would better center the distribution Slide# 56

57 LinkSwitch-LP Output CV/CC Tolerances High-volume manufacturing tolerances < 15% V OUT tolerance at peak power point < 30% I OUT tolerance at peak power point* (dominated by transformer inductance tolerance) All component tolerances, including LinkSwitch-LP *with ±10% primary inductance tolerance Slide# 57

58 LinkSwitch-LP Variation with Temperature 9 Output voltage (V) ±2.5% 0 C, 90 VAC 0 C, 265 VAC 25 C, 90 VAC 25 C, 265 VAC 40 C, 90 VAC 40 C, 265 VAC Output Current (A) Typical single unit variation of 5% over line and temperature Measured at the peak power point on the EP-85 supply Slide# 58

59 Accurate CV with Optocoupler Optocoupler provides more accurate feedback in CV region Bias winding provides CC regulation through R1 and R2 Adjust the value of R1 to obtain optimum CC regulation Slide# 59

60 Accurate CV Output Variation Output Voltage (V) R1 = 60.4 K (nom.) 85 VAC R1 = 60.4 K (nom.) 265 VAC R1 = 65.1K (+7.8%) 85 VAC R1 = 65.1K (+7.8%) 265 VAC R1 = 56.1K (-7.1%) 85 VAC R1 = 56.1K (-7.1%) 265 VAC Output Current (A) R1 values approximate variations of resistor and FB pin tolerance Slide# 60

61 Additional Features Of PI Devices Built in features help you create a better, lower cost design

62 ON/OFF Control Benefits Overall ± 7% V o tolerance with (± 2%) Zener feedback (saves cost) Feedback current (I FB ) independent of changes in Zener bias point Zener voltage change ( V Z ) is negligibly small with ON/OFF control Typical PWM controllers have >1 ma I FB, so V Z affects accuracy I Z I BIAS I FB I Z = I FB + I BIAS Slide# 62

63 Wide Creepage Distances Extended package and pcb creepage distances ensure adequate high voltage spacing for high humidity and high pollution environments Industry standard 8 pin package with pin 6 removed Four SOURCE-pin configuration maximizes conductive heat-sinking Compare to TO-92 type package < 0.9 mm package creepage Slide# 63

64 Hysteretic Thermal Shutdown Fully specified and accurate under all fault conditions Accurate threshold specification 142 C (± 5%) Hysteresis (75 C) allows auto-restart when temperature has reduced Linears have a one-time thermal fuse (safety) that cannot be reset Discrete switcher circuits require extra components that do not directly sense switch temperature, and usually require AC power cycling to reset Slide# 64

65 PI Device Key Design Advantages Safety and reliability protects supply, load and end user Thermal Shutdown prevents overheating from all causes, including overload Tight I LIMIT and F SW tolerances limit power delivery in overload conditions Wide IC package creepage reduces likelihood of arcing related failures Lowest cost solutions Lowest component count keeps BOM and manufacturing costs low Simple and rugged circuits shorten design and qualification cycle times Manufacturability and performance consistency result in high production yields Very wide input voltage operation: <85 VAC to >300 VAC EPS standards require compliance at 115 and 230 VAC for VAC input Difficult for discrete designs to comply at both voltages Universal input operation enables a single design to be used worldwide, which results in significant logistics cost savings Scalability working designs are easily modified for new applications Slide# 65

66 PI Device Quick Design Checklist

67 Quick Design Checklist Maximum (peak) drain voltage V DS should not exceed 650 V at VINMAX and peak (overload) power. A 50 V margin to the 700 V BV DSS rating gives margin for design variation, especially in Clampless designs Maximum (peak) drain current Observe drain current waveforms for signs of transformer saturation At maximum ambient temperature, VIMAX and peak (overload) power Peak drain current must remain below the specified absolute maximum specifications, under all operating conditions Leading Edge Blanking Observe the leading-edge current spike on the drain current waveform and verify that it is below I LIMIT(MIN) at the end of the t LEB(MIN) Pulsed Negative Drain Current Observe drain current waveforms and verify that the peak of any negative drain current is within the maximum limit specified in the datasheet Slide# 67

68 Clampless Design Drain Voltage Example 265 VAC 265 VAC 580 V PK 680 V PK 100 V/div 100 V/div Acceptable Design Margin Insufficient Design Margin Peak drain voltage should not exceed 650 V Provides 50 V of margin to 700 V BV DSS for unit-to-unit variation Slide# 68

69 Pulsed Negative Drain Current Datasheet Maximum Clampless, 130 V OR, 70 VAC V OR 2 µs / DIV Drain voltage clamped to source V DS 100 V / DIV V DC Negative drain current 10 ma, 0.5 µs / DIV I DS 50 ma / DIV Drain voltage may ring below the source in Clampless designs Occurs if V OR > minimum DC bus voltage (VMIN) Verify that negative drain current is below datasheet maximum Measure at lowest specified operating voltage and highest output voltage Slide# 69

70 Leading Edge Blanking Example (LNK362) 50 ma, 2 µs/div t LEB(MIN) 170 ns I D at 265 VAC I LIM(MIN) 130 ma Datasheet specifies minimum blanking time (t LEB ) Drain current well below current limit after t LEB(MIN) Slide# 70

71 External Power Supply (EPS) Energy Efficiency Standards Appendix A

72 The Problem of Energy Waste Energy waste is a major concern around the world Fossil fuel energy sources are finite Fossil fuel consumption side effects: pollution, green-house gases Energy costs are increasing, while alternative energy sources are not mature enough to provide relief The growing demand for personal electronics has dramatically increased the number of External Power Supplies (EPS) How much energy do EPS actually consume each year? Slide# 72

73 The Magnitude of Energy Waste Estimated EPS sold annually: Estimated EPS currently in use: >1 billion units >10 billion units % of EPS that are inefficient linears: ~ 45% Yearly EPS energy waste in the US: Cost of annual US EPS waste : B kw-hours billion dollars Although EPS waste is only 1-2% of annual US energy consumption, it equals the output of 26 average sized power plants! Slide# 73

74 Regulations Emerge to Reduce Energy Waste Slide# 74

75 CALIFORNIA CODE OF REGULATIONS, TITLE 20, SECTIONS Note: Active-mode efficiency is the average of the 25%, 50%, 75%, and 100% load points In 2008, the minimum active-mode efficiency for EPS > 51 watts will be 0.85, and the maximum no-load consumption for all EPS < 250 watts will be 0.5 watts Slide# 75

76 Additional Energy Efficiency Programs US 1W Standby Executive Order Japan Top Runner Program Korea Energy Saving Office Equipment & Home Electronics Program Germany Blue Angel US Ecos Consulting 80-Plus Program European Group for Energy Efficient Appliances EU Directive EC (EuP Directive) Slide# 76

77 Meeting Worldwide Requirements PI solutions enable conformance to ALL worldwide energy efficiency standards including standards with tighter no-load consumption limits European Union Code of Conduct requires < 300 mw Some Japanese and European OEMs require < 150 mw Other Japanese OEMs require < 50 mw Slide# 77

78 Stay Informed with PI s Green Room The PI Green Room contains information and links to the latest worldwide standards View regulations and standards for your design: By agency (ENERGY STAR, CEC, CECP, AGO, etc.) By application (external adapter/charger, TV, DVD player, etc.) By region (China, Asia, Europe, US, etc.) Slide# 78

79 Links to Key Documents Current version of the CEC Appliance Efficiency Regulations US EPA ENERGY STAR power supply efficiency specification pplies US EPA test method for calculating the efficiency of single voltage external AC-DC and AC-AC power supplies power_supplies/epsupplyeffic_testmethod_0804.pdf EU Code of Conduct external power supply efficiency web page %20Power%20Supplies.htm Slide# 79