A 10 MHz GaNFET Based Isolated High Step-Down DC-DC Converter: Design and Magnetics Investigation

Transcription

1 Downloaded fom obi.du.dk on: Ap 7, 219 A 1 MHz GaNFET Based Isolaed High Sep-Down DC-DC Convee: Design and Magneics Invesigaion Thummala, Pasanh; Yelavehi, Doai Babu; Zane, Regan Andew; Ouyang, Ziwei; Andesen, Michael A. E. Published in: IEEE Link o aicle, DOI: 1.119/TIA Publicaion dae: 219 Documen Vesion Pee eviewed vesion Link back o DTU Obi Ciaion (APA): Thummala, P., Yelavehi, D. B., Zane, R. A., Ouyang, Z., & Andesen, M. A. E. (Acceped/In pess). A 1 MHz GaNFET Based Isolaed High Sep-Down DC-DC Convee: Design and Magneics Invesigaion. IEEE, PP(99). hps://doi.og/1.119/tia Geneal ighs Copyigh and moal ighs fo he publicaions made accessible in he public poal ae eained by he auhos and/o ohe copyigh ownes and i is a condiion of accessing publicaions ha uses ecognise and abide by he legal equiemens associaed wih hese ighs. Uses may download and pin one copy of any publicaion fom he public poal fo he pupose of pivae sudy o eseach. You may no fuhe disibue he maeial o use i fo any pofi-making aciviy o commecial gain You may feely disibue he URL idenifying he publicaion in he public poal If you believe ha his documen beaches copyigh please conac us poviding deails, and we will emove access o he wok immediaely and invesigae you claim.

2 A 1 MHz GaNFET Based Isolaed High Sep-Down DC-DC Convee: Design and Magneics Invesigaion Pasanh Thummala, Membe, IEEE $*, Doai Babu Yelavehi, Suden Membe, IEEE #, Regan Zane, Senio Membe, IEEE #, Ziwei Ouyang, Senio Membe, IEEE *, and Michael A. E. Andesen, Membe, IEEE * $ Flux A/S, Indusivangen 5, 455 Asnaes, Denmak, * Eleconics Goup, Depamen of Elecical Engineeing, Technical Univesiy of Denmak, 28 Kongens Lyngby, Denmak # Uah Powe Eleconics Laboaoy, Depamen of Elecical and Compue Engineeing, Uah Sae Univesiy, Logan, Uah USA pasanh.iikgp@gmail.com, doai.yelavehi@usu.edu Absac This pape pesens design of an isolaed high-sep-down DC-DC convee based on a class-de powe sage, opeaing a a 1 MHz swiching fequency using enhancemen mode Gallium Niide (GaN) ansisos. The convee opeaing pinciples ae discussed, and he powe sage design aed fo 2 W is pesened fo a sepdown fom 2-3 V o -28 V. Commecially available magneic maeials wee exploed and he highfequency (HF) esonan induco and ansfome designs using a low-loss Fai-Rie ype 67 maeial ae pesened. Finie elemen simulaions have been pefomed o esimae he paamees of magneics a 1 MHz. Expeimenal esuls ae pesened a 12 W, 254 V o 22 V and 5 W, 254 V o 14 V on a laboaoy pooype opeaing a 1 MHz. A 2 W he expeimenal pooype achieved an efficiency of 85.2%. Keywods DC-DC convesion, Gallium Niide, High fequency, Resonan convesion, Sof swiching, Class-DE, Finie-elemen modeling I. INTRODUCTION The moivaion o opeae a high swiching fequency is no jus o educe he size of passive componens bu also o povide vey fas dynamic load esponse. Mos RF communicaion sysems use powe amplifies (PA) o conve low-powe signals ino lage powe RF signals fo diving he anenna of a specific ansmie. The majoiy of PA designs uilize swiched-mode pulsewidh-modulaing (PWM) convees as he powe souce o opeae RF amplifies. Envelope acking PAs use dynamically changing supply volage o achieve high efficiency fo he PA ove he full powe ange. To achieve successful envelope acking, he powe supply mus be capable of swiching a fequencies geae han 5 MHz, as mos moden RF wavefoms obseve a bandwidh of 1 o 5 MHz [1], [2]. The envelope acking powe supply consideed in his pape has o opeae wih an inpu volage ange of 2 V o 3 V a 1 MHz swiching fequency. Seveal designs a 1 MHz swiching ae epoed in lieaue fo diffeen applicaions. A 1-MHz GaN 16 o 34-V boos convee wih above 9% efficiency is pesened in [3]. A 94% efficien 1-MHz, 1 W buck-boos ype DC- DC convee is sudied in [4]. A 1 MHz, V o.65-2 V, 2 A muliphase buck convee is implemened in [5]. A 1-MHz, 12 V o 5 V, 5 W buck convee is invesigaed in [6]. All of hese designs ae a low opeaing volage (few ens of vols). Tadiional had swiching swiched-mode powe supply (SMPS) opologies ae exemely lossy a such high fequencies. This has led o he developmen of esonan sof-swiching convees. Wih he emegence of Gallium Niide (GaN) based powe swiches, powe eleconic convees end o be even fase, smalle and moe efficien [7]. Resonan convees ae ofen designed in wo pas; an invee conveing he DC inpu volage o an AC cuen and a ecifie conveing he AC cuen o a DC oupu volage. The wo pas ae designed individually, bu he design of he invee depends on he inpu impedance of he ecifie [8], [9]. The mos common opologies fo he invee pa ae based on class E, which could eihe be a class E, a class EF2 (φ2), a esonan SEPIC o a esonan boos convee. The choice of he opology is based on he complexiy and losses associaed wih a high-side gae dive fo opeaion in he HF ange. A class E deived invee imposes significan volage sess acoss he MOSFET. The volage sess fo he class E, he esonan SEPIC and esonan boos is 3.6 imes he inpu volage wih a duy cycle of 5%, and fo he class EF2 his sess is educed o appoximaely imes. The semiconduco swiches in he class DE invee ae diecly conneced o he inpu and he volage acoss hem is limied o he inpu volage. The class DE invee [1]-[12] has wo ohe gea advanages ove he ohe opologies. Fisly, i only equies a single induco. Secondly, due o he lowe peak volage acoss he MOSFET, he soed enegy is appoximaely en imes lowe, compaed o afoemenioned opologies. Bu he need fo high side gae dive inceases he complexiy.

3 Avoiding high di/d and dv/d can help o educe EMI a he souce. Sof-swiching esonan opologies usually have lowe EMI han had-swiching convees. The ime domain chaaceisics of apezoidal and S-shaped swiching ansiions ae epoed in [13]. The S-shaped ansiions seen in he swich node volages (Fig. 4) have lowe high-fequency hamonic conen. The slew ae of he volage ansiion is elaively low (compaed o he high swiching fequency used hee) due o slow swiching ansiion and lage dead-ime used on he high-volage bidge GaNFETs. The dead-ime used hee is 32% of he peiod which is significanly lage compaed o convenional design appoaches. This lage dead-ime also educes he enegy equied in he esonan ank fo dischaging he oupu capaciance C oss of he GaNFETs. This pape pesens a GaN-based and magneic coe-based 1 MHz isolaed DC-DC convee using a Class-DE esonan sof-swiching powe sage [14]. Secion II descibes he convee opeaion, design and simulaion esuls. Secion III discusses he choice of 1 MHz magneics, and he design of induco and ansfome using Fai-Rie 67 maeial. Secion IV povides he expeimenal esuls, and Secion V discusses he powe loss disibuion, followed by he conclusions in Secion VI. II. RESONANT CONVERTER ANALYSIS AND DESIGN A. Convee analysis A class-de based isolaed DC-DC convee is depiced in Fig. 1. The main inpu powe sage consiss of swiches S 1 and S 2. Compaed o he convenional Class- DE amplifies, addiional swiches S 3 and S 4 ae conneced in paallel wih he ecifie diodes D 3 and D 4, o achieve synchonous ecificaion and also fo acive ecificaion o conol he oupu volage and powe. The convee achieves ZVS, zeo volage deivaive swiching (ZVDS), and ZCS a he un-on insan. In his convee, he effecive impedance of he seconday ecifie is used fo designing he seies esonan ank componens C and L. A ansfome wih a uns aio n is used fo poviding isolaion as well as sepping down he inpu volage. The powe is ansfeed fom inpu o oupu due o he esonance beween he esonan ank elemens C and L. Hence, he cuen flowing hough he esonan ank is almos sinusoidal in shape. Based on he fundamenal hamonic appoximaion (FHA), he acequivalen cicui of he poposed Class-DE DC-DC convee is shown in Fig. 2. V in S 1 C in S 2 V A i S 1 S 2 65V GaNFETs C L n:1 C 1 i m i sec L m V VS C ou P S 3 S 4 D 3 D 4 C 2 S 3 S 4 4V GaNFETs D 3 D 4 6 V, 1 A Schoky diode V ou Fig. 1. Schemaic of he Class-DE based isolaed synchonous DC-DC convee. Z 1 C L F V V F A Lm Rac Z 2 Fig. 2. AC equivalen cicui of he esonan ank based on FHA. The design equaions of he poposed isolaed class-de opology ae given below. The AC equivalen load esisance (inpu esisance of he ecifie) is calculaed as [1] R ac 2 2Rn L RLC oss,sec P. (1) whee 2, R L is he load esisance, n is he fsw ansfome uns aio, f sw is he swiching fequency, and C oss,sec is he oupu capaciance of he seconday GaNFETs S 3 and S 4. The RMS swich-node volage on invee side wih espec o negaive ail is given by (assuming apezoidal wavefom) [12] V Dpi 1 V, (2) 3 A, RMS in Similaly, he RMS swich-node volage on ecifie side wih espec o negaive ail, and efeed o pimay side is given by Dsec 1 VP, RMS Vou n, (3) 3 whee D pi and D sec ae he duy cycles of pimay and seconday GaNFETs, especively. V GS, 1 V GS, 2 V GS, 3 V GS, 4 V S 2 i sec V S 4 DTP ni pk Dsec D pi PS Vin T s ni pk DTS DTP V ou T s D sec D pi PS DTS DTP ni pk Dsec Fig. 3. Seady-sae PS DTS wavefoms DTP of he poposed esonan DC-DC convee. The seies componen Z 1 (in Fig. 2) of he esonan cicui pefoms muliple funcions: I povides dc blocking, and also foms an impedance divide ha conols he AC D pi Vin

4 powe deliveed o he esisive load. Z 1 is calculaed using he simila concep povided in [15] wih an assumpion ha he AC powe is deliveed o he load only a he fundamenal of he swiching fequency. The impedances Z 1 and Z 2 ae given by Z V A, RMS 1 Z2 1 V P, RMS LR m ac Z2 L R m ac 2, (4). (5) whee L m is he pimay magneizing inducance of he ansfome. The esonan ank inducance L fo a given ank capaciance C is calculaed as [16] CZ11 L. (6) 2 C The qualiy faco Q of he esonan ank is given by 1 L Q. (7) R C ac Based on he FHA, he fundamenal componens of he inpu and oupu volages of he esonan ank (by appoximaing he apezoidal swich-node wavefoms o squae wave signals) ae given by F V VA Dpi in = 1 cos 2 sin F nv VP D ou = 1 cos 2 sin, (8) sec. (9) The volage gain of he esonan ank is given as follows: F VP nvou Z2 M = = = F V V Z Z A in 1 2, (1) The esonan ank gain M in ems of all cicui vaiables is given by [17] M = k. (11) k 2 Q k fn fn fn whee k is he inducance faco, f is he esonan fequency, and f n is he nomalized fequency Lm 1 fsw k, f =, fn. L 2 LC f The seady sae wavefoms of he poposed DC-DC convee ae shown in Fig. 3. The gae dive wavefoms of he fou pimay and seconday GaNFETs, he volages acoss he GaNFETs S 2 and S 4, and he seconday esonan ank cuen ae clealy shown in Fig. 3. The swiching fequency of he convee is fixed a 1 MHz. The oupu powe of he convee is defined as [1], [18] P ou ni pk cos R RC L oss,sec 2 L. (12) The oupu cuen is given by he following expession The phase shif I o ni pk cos RC L is given by oss,sec PS DTS DTP. (13), (14) whee I pk is he peak value of pimay esonan ank cuen, PS is he phase-shif beween pimay GaNFET S 1 (o S 2) and seconday GaNFET S 3 (o S 4), is he phase coesponding o he dead-ime of he DTS seconday side, DTP is he phase coesponding o he dead-ime of he pimay side, and is he phase-shif of he esonan cuen. The oupu powe and volage can be conolled by vaying he phase-shif angle beween he pimay and seconday GaNFETs. B. Powe sage design The powe sage design of a 2-3 V inpu and - 28 V oupu DC-DC convee swiching a 1 MHz fequency is no ha saigh-fowad due o seveal design vaiables and high fequency of opeaion. Hence, an ieaive appoach is followed o design he poposed isolaed sep-down convee. The fis sep in he design pocess is o selec he ansfome uns aio n. As he uns aio n inceases, he ciculaing enegy educes and he ZVS of pimay GaNFETs is los. Howeve, he convee achieves sofswiching wih a lowe uns aio a he expense of high ciculaing enegy. A uns aio of n=2.5 is seleced o ensue boh ZVS of he pimay GaNFETs as well as low ciculaing enegy of he esonan ank. Due o he high inpu volage and low oupu volage equiemens, on he pimay and seconday sides, 65 V GaNFETs (GS6652B) fom GaN Sysems and 4 V GaNFETs (EPC214C) fom EPC ae chosen, especively. The duy cycles of pimay and seconday GaNFETs ae chosen as D pi=18% and D sec =4%, o ensue enough dead-ime fo sof-swiching he pimay and seconday GaNFETs. Fom equaions (4)-(6), i is clea ha he esonan ank inducance L is a funcion of he pimay magneizing inducance L m. Tha means if one vaiable is fixed, he ohe can be calculaed. Afe invesigaing suiable magneics fo opeaing a 1 MHz, an EIQ-13 coe wih Fai-ie 67 maeial is seleced fo ansfome wih a magneizing inducance of L m=2.2 µh. The calculaed L value fom equaion (6) fo C =1 nf is L =2.35 µh. An EEQ-2 coe (using Fai-ie 67 maeial) wih 5 uns is chosen fo he induco, which has in an inducance of L =2.7 µh. The deails of magneics will be discussed in Secion III. The design of PS

5 he convee a 1 MHz fo 3 V inpu and 28 V oupu a 2 W is summaized in Table I. TABLE I: POWER STAGE DESIGN Vaiable Value n 2.5 R ac 46 Ω L m 2.2 µh Z Ω Z Ω C 1 nf L Calculaion 2.35 µh Pacical 2.7 µh Q Calculaion 1.5 Pacical 1.13 An LTSpice simulaion of he Class-DE convee is pefomed using he GaNFET models fom he manufacues. The simulaion esuls showing key wavefoms ae povided in Fig. 4. The un-on and unoff dive volages fo he pimay GaNFETs fom GaN Sysems and he seconday GaNFETs fom EPC ae 6 V and -2 V, and 5 V and -2 V, especively. 2) The eacive powe is consideably lage compaed o he acive powe sen o he load. Hence volampee (VA) aing of he ansfome is lowe compaed o he VA pocessed by he ank. 3) Since, he ansfome size is small, is L m will also be small fo an efficien ansfome design. Values of k<1 can have a sizable effec on he gain as seen in Fig. 6. 4) In he design pocess k is no a design paamee, and i is no dependen on L m fo esonan opeaion. Achieving high values of k will lead o efficien ansfome designs a his high fequency of opeaion. 5) The qualiy faco Q does no affec he gain o opeaing poin of he sysem significanly a high f n as can be seen in Fig. 5. A ange of qualiy faco Q is possible fo he design. Howeve, o limi he volage sess on he esonan capacio C o a easonable value a single capacio can be used, a Q close o 1 is chosen. 4mA 24mA 8mA -8mA -24mA -4mA 1.2A.6A.A -.6A -1.2A 24V 12V V -12V -24V 172V 15V Magneizing I(Lm) cuen (im) Resonan ank I(L) cuen (i) Resonan induco V(Vank,Vp) volage (VL) Resonan V(D2,Vank) capacio volage (VC) Fig. 5. Volage gain vs. Loaded qualiy faco vs. Nomalized swiching fequency fo k = V 3V Seconday-side low-side GaNFET V(vsw4) dain-o-souce volage (VS4) 14V -3V 33V Pimay-side low-side GaNFET V(d2) dain-o-souce volage (VS2) 15V -3V V Oupu V(vou1) volage (Vou) V 28.44V ns 2ns 4ns 6ns 8ns 1ns 12ns 14ns 16ns 18ns 2ns Fig. 4. LTSpice simulaion esuls fo V in=3 V a D pi=18% and D sec=4%. The oupu powe P ou=2 W. Powe sage design paamees given in Table I ae used in he simulaion. The volage gain of he esonan ank M is ploed in Fig. 5 wih espec o he nomalized fequency f n and he qualiy faco Q fo a given k. Similaly, he volage gain of he esonan ank M is ploed wih espec o he nomalized fequency f n and k, fo a given qualiy faco Q, as shown in he Fig. 6. Fo he convee design specificaions descibed above, k =.82, f =3 MHz, and f n =3.33. C. Design choices 1) The convee is opeaing well above he esonance fequency wih f n=3.33. Choosing a lage f n povides a lage sep-down while giving enough lagging cuen o achieve ZVS of he pimay GaNFET wihin he dead-ime seleced. Fig. 6. Volage gain vs. Consan k vs. Nomalized swiching fequency fo Q =1.13. The vaiaions of oupu volage and oupu powe wih espec o he phase-shif ae povided in Figs. 7(a), PS 8(a) and 7(b), 8(b) especively fo vaious inpu volages. The LTSpice simulaed, calculaed and expeimenal V ou and P ou ae compaed in Fig. 7(a), 7(b) fo V in=254 V. The maximum oupu volage and oupu powe fo boh V in =3 V, 254 V and 2 V occus a a phase-shif of 54 (15 ns) as shown in Figs. 7 and 8. Fo 3 V inpu volage, he oupu volage (fom 28 V o V) and oupu powe (fom 2 W o W) can be conolled by changing he phase-shif fom 82 o 18. Beween his PS opeaing phase ange, he induco cuen will have enough enegy fo sof-swiching. Hence, opeaion above peak powe phase-shif (54 hee fo V in =254 V) is used o conol oupu powe.

6 (a) (b) Fig. 7. (a). The vaiaion of oupu volage; (b) oupu powe wih espec o he phase-shif PS fo V in =254 V, R L =4 Ω. (a) swiching fequency of he convee, he absolue value of capaciance and inducance can be educed bu he acual size educion a vey high fequencies depends on he allowable loss powe densiy. Appopiae coe maeial and winding sucue have o be seleced fo hese high fequencies o educe he loss and ealize he achievable miniauizaion. Emeging hin-film magneic maeials ae a good choice fo fequencies geae han 1 MHz. These maeials ae ypically alloys wih Fe, Co and Ni. Bu hese ae no commecially available a economical coss [19], [2]. Anohe limiaion is he conduco echnology. Usually Liz wie is he choice fo high-fequency powe applicaions, howeve fo fequencies highe han 1 MHz, he equied sand diamee is aound 4 µm which can be expensive and difficul o handle. Fo hese opeaing fequencies consideed hee, foil winding sucue can be simple and effecive soluion because hey have highe packing faco, bee hemal pefomance compaed o Liz wie, and ae moe cos effecive. Thee is limied daa available on he design of high fequency (HF) and vey high fequency (VHF) powe magneics. Powe magneics have high flux dive. Fo mos of he maeials, lage signal loss daa ae no available a above a few MHz. Among he commecially available maeials, Ni-Zn feies and meal-powde maeials, which ae developed fo RF applicaions, have vey high esisiviy and ae suiable fo he pesen applicaion. The pefomance faco fo hese RF maeials in ange of 1 MHz o 1 MHz ae epoed in [21] based on he mehod poposed in [22]. Pefomance faco is he poduc of ampliude of AC flux densiy (B ac) and fequency (f) and is a measue of powe handling capabiliy pe uni volume fo a given coe loss densiy and is a elevan pefomance meic when coe loss is he majo design consain (usually ue fo ansfomes and esonan inducos), neglecing AC winding loss. Among he above epoed maeials, Feoxcube 4F1 [23] and Fai-Rie 67 [24] maeial wee available in plana sucues and es wee available in ods and ooidal shapes mean fo RF applicaions. The 67 maeial also has he highes pefomance faco a 1 MHz [2]. (b) Fig. 8. (a). The vaiaion of oupu volage; (b) oupu powe wih espec o he phase-shif PS fo V in =3 V and 2 V, R L =4 Ω. III. DESIGN AND FEM SIMULATIONS OF MAGNETICS A. Induco and Tansfome designs Wih he emegence of GaN and SiC devices, hee has been a significan advancemen in semiconduco device swiching speed, bu magneics has become a pimay limiaion consaining miniauizaion. By inceasing he Fig. 9. 4F1 and 67 maeial coe loss densiy compaison a 1 MHz fo diffeen opeaing empeaues. Fo boh Feoxcube 4F1 and Fai-Rie 67 maeials, coe loss densiy a 1 MHz fo empeaues 25 C and 1 C (sinusoidal flux assumed) is ploed in Fig. 9 fom he aw daa povided by he manufacues. The coe loss densiy of 67 maeial is 39 mw/cm 3 a 1 MHz fo

7 B ac of 1 mt and is nealy a hid of wha i is fo 4F1 maeial. Because of he elaively high hemal coefficien of he 4F1, i is no a good opion fo fabicaing a esonan induco wih low ai-gap designs. Fo he iniial pooype, 67 maeial was chosen as he coe opion fo he above easons. Howeve, a dawback of he 67 maeial is ha when i is exposed o B ac of geae han 2 mt he maeial popeies ievesibly change and have highe losses han he iniial chaaceisics. Pemeabiliy of boh he maeial a 25 C and 1 C is given in Table II. The PCB windings fo induco and ansfome pooypes ae shown in Fig. 1. The induco and ansfome designs ae summaized in Tables III and IV, especively. A 4-laye PCB (hickness=1.575 mm) wih 1 oz. coppe hickness is used fo pacical implemenaion of he powe cicui. To mainain he ease of manufacuing and also high epeaabiliy, muli-layeed PCBs ae used o ealize he magneic winding sucues, 6-laye PCB fo he induco and 8-laye PCB fo he ansfome. Fo he induco, he coppe hickness in all layes is 35 µm, and he 3 d and 4 h layes ae paallel conneced. This is done o achieve even numbe of layes fo PCB. Since no ai-gap was used in he coe fo induco, he field inensiy is symmeical acoss he middle un, so paalleling he middle un ensues equal cuen shaing beween he paalleled layes. In he ansfome, he 5 pimay uns ae placed in he fis 5 layes, he 6 h laye in he PCB is kep empy, and he 2 seconday uns ae placed in 7 h and 8 h layes, especively. Poviding an empy 6 h laye no only inceases he isolaion beween he pimay and seconday windings, bu i also minimizes he inewinding capaciance. In Tables III and IV, he measued AC esisance values ae used o calculae he AC winding loss. Based on he one-dimensional field appoximaion [25], analyical calculaions ae pefomed o esimae he AC esisance in he plana PCB windings. This analysis helped o choose an iniial opimal hickness fo he PCB windings. Howeve, a moe deailed FEM analysis is equied fo opeaion a 1 MHz o impove he design due o he impoance of paasiic effecs fom aspecs such as PCB aces and vias. TABLE II: 4F1 AND 67 PERMEABILITY WITH TEMPERATURE Maeial T=25 C T=1 C 4F TABLE III: INDUCTOR DESIGN SUMMARY Paamee Value Inducance 2.8 µh Coe EEQ-2, 67 maeial, Volume=2.1 cm 3, Aea=.6 cm 2 Oveall coe heigh 12.7 mm Effecive coe lengh 3.33 cm Tuns, Ai-gap 5 uns, No Ai-gap Coe 2 W.68 W (@B ac= W.46 W (@B ac=9.3 mt) Coppe 2 W.13 W (fo I ms= W.9 W (fo I ms=.683 A) AC 1 MHz 19 mω Coppe hickness 35 µm (in all layes) PCB 6 laye (layes 3 and 4 ae paalleled) Toal PCB hickness=1.75 mm PCB hickness beween layes {1-2, 3-4, and 5-6}.254 mm PCB hickness beween layes {2-3 and 4-5}.38 mm TABLE IV: TRANSFORMER DESIGN SUMMARY Paamee Value Tansfomaion aio n 2.5 Pimay magneizing inducance 2.18 µh Coe EIQ-13, 67 maeial, Volume=.28 cm 3, Aea =.2 cm 2 Oveall coe heigh 3.95 mm Effecive coe lengh 1.39 cm Tuns Non-ineleaved: PPPPPSS 5 uns pimay, 2 uns seconday Coe 2 W.55 W (@ B ac= W.38 W (@ B ac=7.3 mt) Coppe 2 W.265 W (fo I ms= W.18 W (fo I ms=.683 A) AC esisance efeed o 1 MHz 385 mω Coppe hickness 35 µm (in op and boom layes) 17.5 µm (in all middle layes) PCB 8 layes, laye 6 is no used Toal PCB hickness=2 mm PCB hickness beween layes {1-2, 3-4, 5-6, and 7-8}.254 mm PCB hickness beween layes {2-3, 4-5, and 6-7}.257 mm B. FEM simulaions Maxwell 3D simulaions have been pefomed o esimae he AC esisance and leakage inducance of magneics a 1 MHz. The finie elemen modelling (FEM) simulaion esuls of he ansfome cuen densiy and flux densiy a 1 MHz ae shown in Figs. 11(a) and 11(b). The skin deph of coppe a 1 MHz is 2.6 µm. A fine mesh based on inside lengh selecion is used o simulae he eddy cuen effecs in he winding. In he pimay and seconday windings, he laye o laye connecions ae made hough he vias wih an oue diamee of.45 mm and he diamee of he via hole is.2 mm. In he ansfome 3D simulaion model, he vias ae placed beween 2 layes (laye-o-laye). Fig. 1. A phoo of induco and ansfome PCB winding pooypes.

8 acoss he shoed pimay and seconday windings. A compaison of he simulaed and measued paamees of he ansfome is povided in Table V. The simulaed and measued ansfome paamees show a close mach, wih he lages eo in he AC esisance. Measued values a esonance (a) Impedance ( ) Phase (Degees) A: Impedance (b) Fig. 11. Plos fom he 3D Maxwell simulaions of he EIQ-13 ansfome (a) Cuen densiy a 1 MHz; (b) Magneic flux densiy a 1 MHz. Seconday winding is shoed o obain he AC esisance and leakage inducance. Design of he magneics has been a majo pa of he convee design. The coe maeial selecion and PCB windings sucue ae pa of he design challenges ha enabled he opeaion of he convee a high swiching fequency of 1 MHz. The paamees of he ansfome ae measued using he Agilen 4294A Impedance Analyze. The measuemen esuls ae shown in Figs Leakage inducance of ansfome (uh) AC esisance of ansfome (m ) A: Leakage Inducance Refeence values Measued values a 1 MHz B: AC esisance Fequency (MHz) Fig. 12. Measued AC esisance and leakage inducance of he EIQ-13 ansfome using Agilen 4294A analyze. Fom Fig. 13, he esonance fequency of he ansfome is 48.5 MHz, and he pimay magneizing inducance of he ansfome a 1 MHz is 2.18 µh as shown in Fig. 14, which esuls in a pimay ansfome self-capaciance of 4.95 pf. The measued inewinding capaciance of he ansfome as shown in Fig. 15 is 8.99 pf a 1 MHz. I is obained by shoing he pimay and seconday windings, and measuing he capaciance B: Phase Fequency (MHz) Fig. 13. Measued pimay impedance of he EIQ-13 ansfome. Pimay magneizing inducance of ansfome (uh) Pimay esisance wih seconday open (m ) B: Resisance wih seconday open Refeence values A: Magneizing inducance Measued values a 1 MHz Fequency (MHz) Fig. 14. Measued pimay magneizing inducance of he EIQ-13 ansfome. Seies esisance ( ) Inewinding capaciance (pf) Refeence values Measued values a 1 MHz A: Inewinding capaciance B: Seies esisance of capacio Fequency (MHz) Fig. 15. Measued inewinding capaciance of he EIQ-13 ansfome beween pimay and seconday windings.

9 TABLE V: COMPARISON OF SIMULATED AND MEASURED TRANSFORMER PARAMETERS AT 1 MHZ Vaiable Simulaion Measuemen Pimay magneizing inducance 2.17 µh 2.18 µh AC esisance 3 mω 385 mω Leakage inducance 188 nh 194 nh DC esisance 4 mω 45 mω The FEA simulaion esuls of he induco cuen densiy and flux densiy a 1 MHz ae shown in Figs. 16(a), 16(b) and 16(c), especively. As shown in Fig. 16(b), he cuen is pushed owads he edges of he winding. In he induco 3D simulaion model, he vias pass hough all layes (op-laye o boom-laye). The measued paamees and impedance of he induco using he Impedance Analyze ae shown in Fig. 17 and 18. (a) Inducance of esonan induco (uh) AC esisance (m ) Refeence values Measued values a 1 MHz A: Inducance B: AC esisance Fequency (MHz) Fig. 17. Measued AC esisance and inducance of he EEQ-2 induco. Impedance ( ) Phase (Degees) Measued values a esonance A: Impedance B: Phase (b) Fequency (MHz) Fig. 18. Measued impedance of he EEQ-2 induco. (c) Fig. 16. Plos fom he 3D simulaions of he EEQ-2 induco (a) Cuen densiy a 1 MHz; (a) Cuen densiy op view a 1 MHz; (c) Magneic flux densiy a 1 MHz. The inducance and esisance paamees shown in Fig. 17 ae given by he Impedance Analyze fo an equivalen cicui of seies conneced induco and esiso. A seies esisance of mω is measued a 1 MHz. Analyically esimaed seies esisance of he induco a 1 MHz is only 117 mω and FEM simulaions esimae 131 mω. This lage eo in he measued value is expeced due o he paasiic capaciance of he winding. Fom he impedance plo in Fig. 18, i can be seen ha he esonan fequency is 32.7 MHz. Since he esonan fequency is close o he measuemen fequency of 1 MHz, he effec of paasiic capaciance can be negleced. The winding capaciance is esimaed o be 9 pf fom he esonan fequency. This

10 capaciance ceaes a significan change in he magniude and phase of he cuen measued by he Impedance Analyze which leads o lage eo in he measued AC esisance. The measued AC esisance is coeced and esimaed o be aound 19 mω afe compensaing fo he winding capaciance. A compaison of he simulaed and measued inducance, DC and AC esisances of he induco is povided in Table VI. Again, a close mach is achieved wih he lages eo in he AC esisance. The eo in AC esisance fo boh ansfome and inducance migh be due o he oleances in PCB laye and via coppe hickness. The coppe plaing hickness of via is usually no a paamee ha can be specified. PCB manufacues usually guaanee a minimum plaing hickness and fo he cuen PCBs 18 µm was guaaneed by he manufacue. TABLE VI: COMPARISON OF SIMULATED AND MEASURED INDUCTOR PARAMETERS AT 1 MHZ R g,off=3.3 Ω ae used o coune Mille effec on pimay side. A Viex-5 FPGA developmen boad is used o geneae he equied 1 MHz diving signals on boh pimay and seconday sides. 65 V GaN 4 V GaN FET FET Tansfome 9 mm Induco Seconday boad Pimay boad Fig. 19. An expeimenal pooype of he Class-DE based convee. The 1 MHz swiching powe sage is oulined in yellow. The es of he PCB has connecos o he FPGA boad, digial isolaos, es poins and auxiliay supplies fo gae dives. 4 mm Vaiable Simulaion Measuemen Inducance 2.89 µh 2.69 µh AC esisance 131 mω 19 mω DC esisance 37.5 mω 4 mω IV. EXPERIMENTAL RESULTS An expeimenal pooype of he Class-DE based convee is shown in Fig. 19. The esonan convee is opeaed along a naow opimized ajecoy o guaanee ZVS and ZCS. The inducance and noise coupling in gae dive loop ae vey ciical fo opeaion of convee a 1 MHz and a high inpu volages. Fo he pacical implemenaion, pimay 65 V, 22 mω GS6652B GaNFETs wih low oupu capaciance (17 pf) and gae chage (1.7 nc) ae used. Fo synchonous ecificaion, 4 V, 6 mω EPC214C GaNFETs (C oss=15 pf, Q g =2 nc) ae used in he seconday side. A HF diode PMEG61CEH is used fo D 3 and D 4. The expeimenal esuls ae povided in Figs. 2, 21 and 22. The pimay swich-node volage, gae-dive signal fo GaNFET S 2, and he oupu volage fo phase-shifs 9 and 126 ae shown in Figs. 2 and 22, especively. The oupu powes in Figs. 2 and 22 ae 12 W and 5 W, especively. High-fequency esonan capacios fom ATC ae used fo C, C 1 and C 2. A 1 V, 1 nf capacio (1C12JW) is used fo C [26]. A 1 V, 684 nf capacio (9C684MP) is used fo C 1 and C 2 [27]. A digial isolao ADuM21N wih common mode ansien immuniy (CMTI) 1 V/µs is used fo isolaion. Due o non-availabiliy of commecially available half-bidge gae dives fo 3 V inpu and 1 MHz opeaion, and o quickly evaluae he powe sage design, a baey poweed isolaed low-side gae dive LM5114 [28] is used fo diving each GaNFET. All gae-dives fo swiches S 1-S 4 have been designed wih a negaive-bias supply o peven false un-on. A negaive bias of -2 V is used fo boh pimay side/gan sysem devices and seconday side/epc devices. Negaive bias volage in swich S 2 can be seen fom Fig. 2. Independen un-on and un-off gae dive esisos R g,on=2 Ω and Fig. 2. Expeimenal wavefoms fo V in=254 V, Phase-shif =25 ns (9 ), D pi=18%. CH1: Gae-o-souce signal of S 2 PS [5 V/div]; CH2: Dain-o-souce wavefom of S 2 [5 V/div]; CH3: Oupu volage acoss 4 Ω load [12.5 V/div]. Fig. 21. Expeimenal wavefoms fo V in=254 V, Phase-shif =25 ns (9 ), D pi=18%. CH1: Resonan ank cuen [2 A/div] PS (dak blue); CH2: Resonan ank volage [5 V/div] (ligh blue). Fig. 22. Expeimenal wavefoms fo V in=254 V, Phase-shif =35 ns (126 ), D pi=18%. CH1: Gae-o-souce signal of S 2 PS [5 V/div]; CH2: Dain-o-souce wavefom of S 2 [5 V/div]; CH3: Oupu volage acoss 4 Ω load [12.5 V/div].

11 A. Loss-beakdown V. POWER LOSS BREAKDOWN The oal loss beakdown fo he poposed DC-DC convee fo V in=3 V, a aed powe is shown in Fig. 23. The measued efficiency of he pooype convee is povided in Fig. 24. The induco and ansfome losses include boh winding loss and coe loss. The diving loss is he oal gae dive loss fo boh pimay and seconday GaNFETs. The GaNFET device losses include he oal fowad and evese conducion losses, and swiching loss due o all pimay and seconday GaNFETs. This device loss is vey low when all he GaNFETs ae sof-swiching. In ohe wods when he dead-ime is opimum (fo boh pimay and seconday) he oal device loss will be vey low. The loss due o he powe consumpion in he auxiliay powe supply is esimaed o be 1 W, he loss due o he ESR of he capacios, and PCB aces ae consideed as addiional conducion losses. The oal powe loss is 3.46 W. The calculaed efficiency of he convee a an oupu powe of 2.2 W is 85.38%. Opimizing he magneics and auxiliay powe supply (fo poweing he gae dives) designs could fuhe incease he efficiency of he convee. Inegaing he ansfome and induco ino a single magneic sucue will educe he oveall size of he magneics. Winding esisance can be educed by paalleling muliple layes in plana PCB windings. The powe sage and magneics designs could be fuhe invesigaed and opimized by changing he inducance consan-k descibed in Secion II, howeve i is ou of scope of his pape. B. Conol of he HF DC-DC convee Envelop acking capabiliy helps o educe hea and powe consumpion of he powe amplifie (PA). Pecise conol is no a equiemen fo his applicaion [29], [3]. The PA is linea (Class A o Class AB fo insance) and has vey high bandwidh. The envelope acking convee can be slowe and less accuae because he only equiemen is o supply he PA wih a volage highe han he envelope o avoid he sauaion of he oupu sage of he PA. Bu he bandwidh equied (close o 1 MHz) is sill vey high fo a swiching convee. To achieve his high bandwidh a feed-fowad conol can be implemened. The PA load can be effecively epesened by a esiso. Fo a given PA, he phase-shifs PS can be pe-calculaed and soed in a look-up able ove he oupu volage ange. The ecommended conol block diagam is illusaed in Fig. 25. This suggesed conol has no been validaed as a pa of his pape. V in Envelope Refeence C in V in Look-up Table DC-DC Convee PS R Load PA RF oupu Fig. 25. Recommended conol block diagam. Fig. 23. Toal loss beakdown fo a 3 V o 28 V sep-down fo an oupu powe P ou=2.2 W a 1 MHz swiching fequency. Fig. 24. Measued efficiency as a funcion of oupu powe. VI. CONCLUSIONS In his pape, a high-fequency, high-sep down isolaed DC-DC convee equipped wih he GaN devices is analyzed and designed. The poposed esonan design shapes wavefoms o opimize magneics and achieve high efficiency wih high powe densiy. A low- EMI is expeced due o S-shaped ansiion of he swichnode volage, and due o he smooh and sinusoidal high fequency esonan ank cuen wavefom. Moeove, he following soluions help in minimizing he adiaed EMI in HF DC-DC convees: by minimizing he powe supply pah fo high fequencies, by designing he PCB o minimize he loop aeas, by selecing he coec HF capacios, and by adding an elecomagneic shielding. The induco and ansfome ae designed using commecially available magneic maeials o minimize he physical size and coe and coppe losses when opeaing a a swiching fequency of 1 MHz. The coe maeial Fai-Rie 67 was chosen fom many of he commecially available magneic maeials because of is bee pefomance facos and is availabiliy in lowpofile plana sucues. Maxwell 3D simulaions wee pefomed o esimae he paamees of he induco and ansfome o aid he design pocess. A phase shif angle beween he pimay and seconday GaNFETs was used

12 o egulae he oupu volage and powe of he DC-DC convee. Phase-shif angle ange beween peak powe angle and 18 is used o ensue ha hee is enough eacive enegy o sof-swich a low loads. A 2 W, 3 V o 28 V laboaoy pooype opeaing a 1 MHz convee achieved an efficiency of 85.2%. REFERENCES [1] Y. Zhang, J. Sydom, M. de Rooij and D. Maksimović, Envelope acking GaN powe supply fo 4G cell phone base saions, 216 IEEE Applied Powe Eleconics Confeence and Exposiion (APEC), Long Beach, CA, 216, pp [2] EPC whie pape, 217. [Online]: hp://epcco.com/epc/poals//epc/documens/papes/egan%2fets%2f o%2envelope%2tacking%2applicaions.pdf [3] F. Gamand, M. D. Li and C. Gaquiee, A 1-MHz GaN HEMT DC/DC Boos Convee fo Powe Amplifie Applicaions, IEEE Tansacions on Cicuis and Sysems II: Expess Biefs, vol. 59, no. 11, pp , Nov [4] K. Kuse, M. Elbo and Z. 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Available: hp:// [28] Gae-dive: hp:// [29] J. Jeong, D. F. Kimball, Wideband Envelope-acking Powe Amplifie wih Reduced Bandwidh Powe Supply Wavefom, IEEE Tans. Micowave Theoy & Tech. Symposium, pp , June 29. [3] O. Gacía, M. Vasić, P. Alou, J. Á. Olive and J. A. Cobos, An Oveview of Fas DC DC Convees fo Envelope Amplifie in RF Tansmies, IEEE Tansacions on Powe Eleconics, vol. 28, no. 1, pp , Oc Pasanh Thummala (S 11 M 15) eceived he M.Tech. degee in elecical engineeing fom Indian Insiue of Technology Khaagpu, Khaagpu, India, and Ph.D. degee in powe eleconics fom Technical Univesiy of Denmak (DTU), Kongens Lyngby, Denmak, in 21 and 215, especively. He was a visiing Ph.D. suden a Coloado Powe Eleconics Cene, CoPEC, Univesiy of Coloado, Boulde, CO, USA, fom Sepembe 213 o Januay 214. He woked as a Posdocoal Reseache: a he Elecical Machines and Dives Laboaoy, Naional Univesiy of Singapoe, Singapoe fom June 215 o June 216, a Uah Powe Eleconics Lab, Uah Sae Univesiy, Uah, USA fom June 216 o May 217, a he Eleconics Goup, Technical Univesiy of Denmak fom July 217 o June 218, especively. Cuenly, he is woking as a Design and Developmen Enginee in Flux A/S, Asnæs, Denmak fom Augus 218. His key eseach ineess include high fequency and vey high fequency DC-DC, DC-AC and AC-DC convees, high-volage (HV) capacio chaging and dischaging applicaions, magneics design fo Defense and Space applicaions, high fequency plana and inegaed magneics, and wieless powe ansfe. He eceived he bes suden pape awad a he IEEE ECCE USA Confeence, Denve, CO, USA, in 213. He has seved as a session chai in IPEC-ECCE Asia 218 confeence a Niigaa, Japan. He has published ove 2 echnical papes in IEEE jounals and confeences, and is a fequen eviewe of IEEE jounals.

13 Doai Babu Yelavehi (S 17) eceived he B.E. degee in elecical and eleconics engineeing fom Jawahalal Nehu Technological Univesiy, Hydeabad, India in 211, and he M.Tech. degee in elecical engineeing fom IIT Kanpu, Kanpu, India, in 213. Fom 214 o 216, he woked on powe convee opologies fo uiliy applicaions as a Reseach Enginee a Naional Univesiy of Singapoe (NUS), Singapoe. Pio o joining NUS, he was an Enginee wih he Aeonauical Developmen Agency, Bangaloe, India. He is cuenly woking owads he Ph.D. degee in Elecical and Compue Engineeing fom Uah Sae Univesiy. His eseach ineess include opology and conol of powe convees fo uiliy and elecic vehicle applicaions. Regan Zane (SM 7) eceived he Ph.D. degee in elecical engineeing fom he Univesiy of Coloado, Boulde, in He is cuenly a Full Pofesso wih he David G. and Diann L. San Endowed Pofessoship in he Depamen of Elecical and Compue Engineeing and Dieco of he Cene fo Susainable Elecified Tanspoaion (SELECT) a Uah Sae Univesiy in Logan, UT. Pio o joining USU, he was a faculy membe a he Univesiy of Coloado-Boulde, Coloado Powe Eleconics Cene, CoPEC, 21 o 212, and eseach enginee a GE Global Reseach Cene, Niskayuna, NY, He has ecen and ongoing eseach pogams in powe eleconics fo elecic vehicle chaging infasucue, including exeme fas chaging and saic and dynamic wieless chaging, baey managemen sysems, dc micogids, and gid ied and gid ineacive convees, and gid inegaion of enegy soage and enewable enegy. D. Zane eceived he NSF Caee Awad in 24, he 25 IEEE Micowave Bes Pape Pize, he 27 and 29 IEEE Powe Eleconics Sociey Tansacions Pize Lee Awads and he 28 IEEE Powe Eleconics Sociey Richad M. Bass Ousanding Young Powe Eleconics Enginee Awad. He eceived he 26 Inveno of he Yea, 26 Povos Faculy Achievemen, 28 John and Mecedes Peebles Innovaion in Teaching, and he 211 Holland Teaching Awads fom he Univesiy of Coloado. He has co-auhoed ove 175 pee-eviewed publicaions and he exbook Digial Conol of High- Fequency Swiched-Mode Powe Convees. Ziwei Ouyang (S 7, M 11, SM 17) eceived his PhD degee fom Technical Univesiy of Denmak (DTU) in 211. Fom 211 o 213, he was a posdoc eseache a DTU. Fom 213 o 216, he was appoined as an assisan pofesso a he same depamen. Since fom Apil 216, he is an associae pofesso a DTU. His eseach aeas focus on high-fequency plana magneics modeling and inegaion, high-densiy high-efficiency powe convees, PV baey enegy soage sysem, and wieless chaging ec. He is IEEE senio membe. He has ove 6 high impac IEEE jounal and confeence publicaions, co-auho on a book chape on Magneics fo he Handbook of Powe Eleconics and cuenly he is he holde of 8 inenaional paens. He was a ecipien of Young Enginee Awad a PCIM-Asia 214, and eceived Bes Ph.D. Disseaion of he Yea Awad 212 in Technical Univesiy of Denmak. He eceived seveal Bes Pape Awads in IEEE sponsoed inenaional confeences. He has been invied o give lecues in many univesiies, enepises and educaional seminas and wokshops aound he wold including USA, Euope and China. He has seved as session chai in some IEEE sponsoed confeences and associaed edio fo IEEE Jounal of Emeging and Seleced Topics in Powe Eleconics. Michael A. E. Andesen (M 88) eceived he M.Sc.E.E. and Ph.D. degees in powe eleconics fom he Technical Univesiy of Denmak, Kongens Lyngby, Denmak, in 1987 and 199, especively. He is cuenly a Pofesso of powe eleconics a he Technical Univesiy of Denmak, whee since 29, he has been he Depuy Head of he Depamen of Elecical Engineeing. He is he auho o coauho of moe han 3 publicaions. His eseach ineess include swich-mode powe supplies, piezoelecic ansfomes, powe faco coecion, and swich-mode audio powe amplifies.