Pulse Radar with Field-Programmable Gate Array Range Compression for Real Time Displacement and Vibration Monitoring

Transcription

1 sensors Article Pulse Rdr with Field-Progrmmble Gte Arry Rnge Compression for Rel Time Displcement nd Vibrtion Monitoring Mihi-Liviu Tudose 1, *, Andrei Anghel 1, Remus Ccovenu 1 nd Mihi Dtcu 1,2 1 Reserch Centre for Sptil Informtion CEOSpceTech, University Politehnic Buchrest, Buchrest , Romni; ndrei.nghel@munde.pub.ro (A.A.); remus.ccovenu@upb.ro (R.C.); mihi.dtcu@dlr.de (M.D.) 2 Germn Aerospce Centre, Remote Sensing Technology Institute, Weßling 82234, Germny * Correspondence: mihi_tudose89@yhoo.com; Tel.: Received: 22 November 2018; Accepted: 18 December 2018; Published: 27 December 2018 Abstrct: This pper ims to present bsic functionlity rdr pltform for rel time monitoring displcement nd vibrtion. rel time cpbilities mke rdr pltform useful when live monitoring trgets is required. system is bsed on RF nlog front-end USRP, nd rnge compression (time-domin cross-correltion) is implemented on FPGA included in USRP. Furr processing is performed on host computer to plot rel time rnge priles, displcements, vibrtion frequencies spectr nd spectrogrms (wterfll plots) for long term monitoring. system is currently in experimentl form nd present pper ims to prove its functionlity. precision this system is estimted (using 3σ pproximtion) t 0.6 mm for displcement mesurements nd 1.8 mm for vibrtion mplitude mesurements. Keywords: pulse rdr; rel time; displcement; vibrtion; FPGA; USRP; cross-correltion 1. Introduction While re is gret vriety methods for vibrtion monitoring remote trgets, most m require sensor to be mounted on desired prt, which my prove inconvenient in severl pplictions. non-contct vibrtion monitoring methods re usully bsed on rdr nd lser, but ltter suffers from tmospheric influence nd requires certin degree trget reflectivity in opticl domin. Ground-bsed rdrs re being used frequently in present dys to mesure trget displcements, especilly for structurl monitoring. By mens Doppler effect or by mens interferometry, rdrs nd lso sonrs cn lso be used in non-contct vibrtion monitoring. In field sonr, trget motion nlysis hs lso been performed using probbilistic techniques, bsed on mplitude informtion trget [1]. method increses ccurcy estimtion nd observbility trget. It is ment for nrrowbnd pssive sonr trcking system. A study bout usge trget-relted informtion with purpose determining trjectory observing pltform ws published [2]. It is useful if informtion trnsmitted by pltform is intercepted. Vibrtion monitoring is useful especilly for medicl purposes (ptient breth nd hertbet monitoring, detection life-signs) [3,4], civil engineering, structurl helth monitoring (bridges nd dms monitoring) [5,6] nd industril engineering (monitoring mchine prts vibrtions) [7,8]. A oreticl study ws written [9] bout pulse rdr counterprt, FMCW rdr, in order to evlute its performnces in context vibrtion mesurement. uthors stte tht it cn chieve Sensors 2019, 19, 82; doi: /s

2 Sensors 2019, 19, sub-hertz oreticl ccurcy vibrtion frequency mesurement nd micrometer ccurcy for mechnicl oscilltion mplitude mesurement. In [10], study bout effects ntenn rdition pttern in context vibrtion monitoring using rdr ws published. Most mentioned systems fer informtion bout displcements nd vibrtion fter cquisition dt nd post-processing. In contrst, system presented in this pper contins implementtion FPGA bsebnd prt for signl processing in pulse rdr system, with rel time rnge compression. Rnge compression is process generting rnge prile using trnsmitted nd received signls. Reference [11] describes signl processing prts required for rel time vibrtion monitoring trgets, using n FMCW rdr system. informtion bout displcement or vibrtion is extrcted from interferometric phse bet signl. uthors provide test results regrding mesurements t low vibrtion frequencies nd t very short rnge (1.45 m). results presented in this pper cover higher vibrtion frequencies on trgets plced t longer rnges. In reference [12], SAR processor for single-bit coded signls is presented. It includes time-domin rnge nd zimuth compression prts. This SAR processor ws designed for C-bnd irborne pulse rdr clled E-SAR. It is implemented in FPGA, due to low power nd low re consumption. single bit rchitecture llows fundmentl simplifiction, but still serves purpose rnge compression, similr to our own system. A more recent dt processor [13] ws designed for precipittion rdr on-bord dt processing. As in our cse, trnsmitted wveform is chirped impulse. pltform performs rnge compression by mtched filtering, using finite impulse response filter, implemented in FPGA. mentioned filter hs number 256 tps nd uses most FPGA resources by performing number 20 billion opertions per second. Since filter hs fixed coefficients, rnge compression is lwys performed between received signl nd reference signl. In this configurtion, rdr system is required to be phse coherent from one trnsmitted pulse to nor. In contrst, our implementtion uses reference signl which is smpled replic trnsmitted signl. refore, it requires phse coherence only for one pulse repetition period. Anor design UAV-borne SAR processor is described in [14], which is ment for nturl hzrd detection. solution is bsed on combining dedicted preprocessor with n FPGA. Tsks re divided between two, where preprocessor executes irregulr computtions nd FPGA performs repetitious computtions. Rnge compression is lso performed on FPGA. previous three presented systems feture integrted FPGA pulse compression nd re ment, respectively, for SAR irborne imging, precipittion monitoring nd nturl hzrd detection. system described in this pper is ment for displcement nd vibrtion monitoring. Section 2 this pper presents principle pulse rdr displcement mesurement using interferometry. An overview description displcement nd vibrtion mesurement system is found in Section 3. Section 4 this pper describes FPGA hrdwre design implementtion rdr s trnsmit nd receive bsebnd modules. Rnge compression through cross-correltion implementtion on FPGA is described in Section 5. functions performed by host computer re presented in Section 6. In-field experimentl results re shown in Section 7, while conclusions cn be found in Section 8. Nottions: t del : rdr-to-trget round trip dely, c: speed light, R 0 : rdr-to-trget fixed rnge component, R(t): rdr-to-trget vrible rnge component, τ: chirp durtion, α: chirp ngulr rte, f 0 : crrier frequency, ϕ 0 : initil phse, δϕ: phse shift, K: number simultneous multiplictions, N: length input sequence, δr: rnge bin width, σ displ : displcement stndrd devition, λ: wvelength, SNR: Signl-to-Noise Rtio. 2. Principle Pulse Rdr Displcement Monitoring geometry displcement mesurement system is presented in Figure 1.

3 Sensors Sensors 2019, 2018, 19, 18, 82x FOR PEER REVIEW Figure 1. Displcement mesurement geometry. Trget is plced t fixed rnge R0. trget s Figure 1. Displcement mesurement geometry. Trget is plced t fixed rnge R 0. trget s displcement or vibrtion is described by ΔR(t). ΔR(t) is much smller thn R0. displcement or vibrtion is described by R(t). R(t) is much smller thn R 0. round-trip dely term tdel round-trip dely term t is dependent on rdr-to-trget rnge, with expression (1): del is dependent on rdr-to-trget rnge, with expression (1): 2 (1) t del = 2(R 0 + R(t)) (1) c where R0 is fixed rnge component, nd ΔR(t) is vrible rnge component, which describes where R 0 is fixed rnge component, nd R(t) is vrible rnge component, which describes displcement or vibrtion. displcement or vibrtion. rdr trnsmits linerly frequency modulted pulse ττ durtion, with time-domin expression: ( rect 1 t 2 exp j 2π" #$ s 2 % &' (2) TX (t) = rect τ 1 ) [ )] exp j (2π f 0 t + αt ϕ 0 (2) where rect(t) is rectngulr function (defined s 0 for t > 1/2, ½ for t=½, nd 1 for t <1/2), τ is where rect(t) is rectngulr function (defined s 0 for t > 1/2, chirp durtion, α is chirp ngulr rte, fo is crrier frequency 1 2 for t = nd 1 2, nd 1 for t < 1/2), τ φ0 is initil phse. is chirp durtion, α is chirp ngulr rte, f received signl is delyed by time durtion 0 is crrier frequency nd ϕ proportionl to signl 0 is initil phse. time flight tdel. received signl is delyed by time durtion proportionl to signl time flight t del. s rect 1 2 exp j 2π" # $ ( % 2 &' (3) t tdel s RX (t) = rect 1 ) [ ( exp j 2π f 0 (t t τ 2 del ) + α(t )] t del) 2 + ϕ 0 (3) 2 signls re trnsferred to bsebnd by frequency mixing with f0. rnge compressed signl is found by determining cross-correltion between signls re trnsferred to bsebnd by frequency mixing with f 0. bsebnd versions trnsmitted nd received signl. rnge compressed signl is found by determining cross-correltion between bsebnd versions trnsmitted nd received r 1 signl. ( & exp*j2π" + psf (4) r TX RX (t) = τ 1 t t ) del exp[j( 2π f 0 t where psf() is rnge point spred τ del )]psf(t t del ) (4) function ( utocorreltion function complex envelope) [15]. where psf() is rnge point spred function ( utocorreltion function complex Expnding previous reltion yields: envelope) [15]. Expnding previous reltion r t 1 yields: & psf exp j 4π" & (5) ( phse r TX RX (t) lst = τ term 1 t t ) ( del is importnt psf(t in displcement t τ del ) exp determintion. j 4π f ) 0(R 0 + R(t)) If phse shift δφcn (5) c be mesured in slow-time domin (from one pulse to nor), n: phse lst term is importnt in displcement determintion. If phse shift δϕ cn be mesured in slow-time domin (from one pulse.% (6) 4π" to nor), n: refore, vrible rnge component R(t) cn = be c determined δϕ by mesuring phse in (6) bin corresponding to trget in rnge prile. 4π f 0 refore, vrible rnge component cn be determined by mesuring phse in bin 3. System Overview corresponding to trget in rnge prile. rdr system in Figure 2 is implemented using n USRP-2954R pltform nd host computer. Universl Stwre Rdio Peripherl is flexible pltform, contining RF trnsmit nd receive modules, s welll s n FPGA used for digitl bsebnd signl processing. processing prt from host computer is performed with LbView. digitl bsebnd prt is executed within n FPGA, which is progrmmed with code compiled using LbView FPGA.

4 Sensors 2019, 19, System Overview rdr system in Figure 2 is implemented using n USRP-2954R pltform nd host computer. Universl Stwre Rdio Peripherl is flexible pltform, contining RF trnsmit nd receive modules, s well s n FPGA used for digitl bsebnd signl processing. processing prt Sensors from2018, 18, host x FOR computer PEER REVIEW is performed with LbView. digitl bsebnd prt is executed 4 16 within n FPGA, which is progrmmed with code compiled using LbView FPGA. system contins digitl trnsmit nd receive prts, s s well s s block tht tht computes rnge compression using cross-correltion. Prcticlly, im is is fst fst computtion rnge prile s s soon s s received signls smples hve been stored in in memory. system is is bsed on on split split processing signls, signls, which which occurs occurs both onboth FPGA, on s FPGA, well s s onwell host s on computer. host computer. processing required processing for rnge required compression for rnge (crosscompression correltion) is(cross hrdwre correltion) implemented is hrdwre on FPGA implemented for incresed on speed. FPGA Bsed for incresed on delivered speed. Bsed rngeon priles, delivered fst Fourier rnge trnsform priles, fst (FFT) Fourier for vibrtion trnsform spectrum (FFT) estimtion for vibrtion is performed spectrum by estimtion host computer. is performed This combined by host solution computer. fers rel This time combined trget displcement solution fers nd rel vibrtion time trget mesurements. displcement nd vibrtion mesurements. developed grphicl interfce llows user user to select to select trget trget bin bin interest interest nd nd monitor monitor seprtely it seprtely for displcement for displcement nd vibrtion nd vibrtion nlysis. While nlysis. single While bin cnsingle be monitored bin cn independently, be monitored independently, mgnitude nd phse mgnitude components nd phse entire components rnge prile re lwys entire vilble, rnge prile fering re glnce lwys vilble, trgetfering scene t ny glnce moment. trget scene t ny moment. trnsmitted signl pth is is connected to to input splitter, which divides it it between RX RX port port first first dughterbord nd nd trnsmit pth. pth. This This signl signl is used is used s s reference, reference, in order in order to determine to determine time time instnce instnce t which t which trnsmit trnsmit strts, strts, refore refore cncelling cncelling group group dely dely time time nlog nlog RF circuits. RF circuits. Since implementtion requires two two input signls in in order to to compute rnge prile, this this configurtion cn cn be be used used s s monosttic rdr, rdr, with with on-bord on-bord trnsmitter, trnsmitter, or s bisttic or s bisttic rdr with rdr with trnsmitter trnsmitter opportunity opportunity [15]. In [15]. bisttic In rdr bisttic configurtion, rdr configurtion, trnsmit prt trnsmit cn beprt disbled cn be nd disbled both nd RXboth chnnels RX cnchnnels be used: cn onebe forused: reference one for signl reference (directlysignl from (directly trnsmitter from opportunity) trnsmitter nd opportunity) second one nd for second reflected one signl for from reflected scene, signl lthough from creful scene, triggering lthough will creful be required triggering in this will cse. be required in this cse. Figure 2. Schemtic block entire rdr system, contining USRP-2954R. Figure 2.Schemtic block entire rdr system, contining USRP-2954R. 4. Pulse Rdr Bsebnd Implementtion on USRP Pltform 4. Pulse Rdr Bsebnd Implementtion on USRP Pltform This section contins description bsebnd prt this pulse rdr. block digrm in Figure This 3 section shows contins min components, description consisting bsebnd counters, prt this memories pulse rdr. nd specific block block digrm for computing in Figure cross 3 shows correltion, min which components, will be described consisting in more counters, detil memories in next nd section. specific block for computing cross correltion, which will be described in more detil in next section.

5 Sensors 2018, 18, x FOR PEER REVIEW 5 16 Sensors 2019, 19, Sensors 2018, 18, x FOR PEER REVIEW 5 16 Figure 3.Pulse rdr FPGA implementtion overview. Two different clock domins exist: system clock Figure 3. Pulse rdr FPGA implementtion overview. Two different clock domins exist: system clock nd smpling clock. system clock ws chosen bsed on implementtion timing constrints. nd Figure smpling 3.Pulse clock. rdr FPGA system implementtion clock ws chosen overview. bsed Two ondifferent implementtion clock domins timing exist: system constrints. clock two domins re linked by Strt trigger 2 signl nd by RX memory contents. nd two smpling domins clock. re linked system by clock Strt ws trigger chosen 2 bsed signl on nd by implementtion RX memory timing contents. constrints. two domins re linked by Strt trigger 2 signl nd by RX memory contents. A counter tht is incremented t ech smpling clock period (120MHz) is used in order to A counter tht is incremented t ech smpling clock period (120MHz) is used in order to generte A counter pulse tht repetition is incremented intervl t trigger ech smpling ( Strt trigger clock 1 period in Figure (120MHz) 3). is bits used composing order generte pulse repetition intervl trigger ( Strt trigger 1 in Figure 3). bits composing to generte ddress number pulse re repetition tied to intervl red only trigger memory ( Strt nd trigger to two 1 dditionl in Figure red/write 3). bits memories. composing All ddress number re tied to red only memory nd to two dditionl red/write memories. All ddress memories number contin re tied both memories contin both to I I nd red nd Qonly Q smples. smples. memory nd TX TXto red red two only only dditionl memory memoryred/write contins contins memories. smples smplesall chirp chirp memories signl. signl. contin both I nd Q smples. TX red only memory contins smples chirp Prcticlly, Prcticlly, signl. s counter increments vlue ddress loction, smples from TX s counter increments vlue ddress loction, smples from TX memory memory Prcticlly, re delivered re delivered s to counter to digitl digitl increments to nlog to nlog converter vlue converter (DAC) (DAC) ddress nd ndloction, smples smples from smples from from two two nlog nlog TX to memory to digitl digitlre converters converters delivered (ADCs) (ADCs) to re digitl re written written to nlog in ech in ech converter receive (DAC) receive memory nd memory smples loctions. loctions. from An An exmple exmple two nlog digrm to digrm digitl converters RX1 nd RX1 nd (ADCs) RX2 RX2 signls re signls written smples smples in ech (I smples) (I smples) receive cn be cn be observed memory observed in loctions. in Figure Figure 4. An 4. exmple digrm RX1 nd RX2 signls smples (I smples) cn be observed in Figure RX1 signl rel prt ADC ADC output output ADC ADC output output 10 4 RX1 signl rel prt Smples RX2 200 signl 250 rel prt Smples RX2 signl rel prt Smples Figure 4. I smples RX1 nd RX2 signls, with ir Smples corresponding time domin durtion, s received Figure 4. I smples RX1 nd RX2 signls, with ir corresponding time domin durtion, s by pltform when close trget is plced in front rdr. received by pltform when close trget is plced in front rdr. Figure 4. I smples RX1 nd RX2 signls, with ir corresponding time domin durtion, s received by pltform when close trget is plced in front rdr.

6 Sensors 2019, 19, Sensors 2018, 18, x FOR PEER REVIEW 6 16 As soon s simultneous process trnsmit nd receive finishes, nor counter strts As soon s simultneous process trnsmit nd receive finishes, nor counter strts incrementing ddress for Red section two RX memories t frequency referred to s incrementing ddress for Red section two RX memories t frequency referred to system clock. dt is delivered to block tht computes cross-correltion. s system clock. dt is delivered to block tht computes cross-correltion. smpling clock 120 MHz is imposed by USRP pltform. system clock 30 MHz smpling clock 120 MHz is imposed by USRP pltform. system clock 30 MHz ws chosen in order to stisfy timing constrints imposed by FPGA compile engine. ws chosen in order to stisfy timing constrints imposed by FPGA compile engine. 5. Bsebnd Rnge Compression 5. Bsebnd Rnge Compression In order to determine dely between bsebnd versions received signls from both chnnels, In order RX1 to nd determine RX2, cross-correltion dely between is computed bsebnd between versions two. Prcticlly, received signls discrete from time both domin chnnels, convolution RX1 nd between RX2, cross-correltion conjugted time-reversed is computed version between trnsmitted two. Prcticlly, signl (RX1) discrete nd time received domin signl convolution (RX2) is performed. between conjugted forementioned time-reversed opertion version is identicl to trnsmitted cross-correltion signl (RX1) opertion nd (7). received signl (RX2) is performed. forementioned opertion is identicl to cross-correltion opertion (7). s RX1 (n) s RX2 (n) srx1 ( n) s RX2(n) (7) s / n s $ n s / n s $ n (7) where is cross-correltion opertor nd * is convolution opertor. where definition is cross-correltion convolution opertor dpted nd * for is convolution involved signls opertor. is (8): definition convolution dpted for involved signls is (8): s / 6 K srx1 ( n) s RX2(n) = n s srx1 (k) s $ n 4 s / 5 s $ RX2(n n 5 k) (8) k=1 78/ where K is number multiplictions which cn be computed simultneously. bsebnd rnge compression opertion is performed by computing cross correltion between version trnsmitted signl (RX1) nd nd received signl signl from from scene scene (RX2). (RX2). A simplified A block block digrm digrm cross-correltion implementtion is presented is presented in Figure in Figure cross-correltion block block works works t tsystem system clock clock frequency frequency (30 MHz). (30 MHz). Figure 5. Cross-correltion block digrm, s s well well s s relted relted blocks blocks tht tht operte operte in in system system clock clock domin. domin. contents contents RX1 memory RX1 memory re dumped re dumped in corresponding corresponding buffer. n, buffer. n, contents contents second memory second memory re dumped re dumped in Bufferin 2. Buffer two 2. buffers two re buffers ctully re shift ctully registers shift composed registers composed cscded FFs cscded (flip-flops). FFs (flip-flops). multiplictions multiplictions nd prtil results nd prtil summtion results resummtion performed ech re performed clock period. ech clock mgnitude period. ndmgnitude phse nd obtined phse rnge obtined prile re rnge sentprile to re hostsent computer to host using computer FIFOs. using FIFOs. most most resource-demnding resource-demnding prt prt cross-correltor cross-correltor implementtion implementtion re re multipliers. multipliers. se se multipliers multipliers re re implemented implemented using using DSP48 DSP48 slices. slices. Combintionl Combintionl multipliers multipliers cn cn lso lso be be implemented, implemented, but but with with high high hrdwre hrdwre resource resource requirements, requirements, which which cn prove cn prove inefficient inefficient for for design. design. A number A number 1540 DSP slices DSP48 re vilble slices on re on-bord vilble FPGA. on Since on-bord multiplictions FPGA. Since required multiplictions re in complexdomin, required re in number complexdomin, 3 DSP48 cells number re required 3 DSP48 for complex cells re multipliction. required for complex refore, multipliction. K ws chosen refore, t 448, in order K ws to chosen keep t few 448, spre in order cells to for keep rest few spre design. cells for rest design. size both RX1 nd RX2 memories hs to be chosen, considering rdr system prmeters (trnsmit size time durtion, both RX1 mximum nd RX2 memories detectble hs rnge), to be s chosen, well s considering FPGA resource rdr utiliztion system prmeters constrints. (trnsmit time length durtion, RX1 mximum signl detectble ws chosen rnge), equl s to well number s FPGA resource simultneous utiliztion multiplictions constrints. (K = 448) length in order to simplify RX1 signl implementtion. ws chosen equl to length number RX2 simultneous memory is multiplictions chosen t (K Since = 448) in smpling order to frequency simplify is 120 implementtion. Msps, nd ddress length loction RX2 is incremented memory is every chosen smpling t Since smpling frequency is 120 Msps, nd ddress loction is incremented every smpling

7 Sensors 2019, 19, period, receive window durtion is µs. Echoes from trgets situted s fr s 3.9 km cn be received in this time window durtion. Since 448 smples both RX1 nd RX2 signls re required simultneously (t ech clock cycle) for computtion cross-correltion, memories content must be dumped into structures clled buffers. buffers re prcticlly shift registers composed flip-flops, with 16-bit width. first opertion stge consists dumping contents ech RX1 memories into corresponding buffer, which is done by decrementing ddress counter. Smples shift in right direction every clock cycle, until entire content memory fills buffer. Once this dump is finished, buffer s implicit shifting is stopped using disble signl. imginry prt signl ( Q component) is negted before being written to buffer, in order to perform complex conjugte RX1. Both I nd Q components both signls re subject to men vlue subtrction, in order to correct DC fset introduced by nlog rdio front-ends. men vlue iscomputed on smples ech pulse repetition intervl (PRI). At first PRI, men is considered 0. After ll smples hve been dumped out memory, ir men vlue is computed. men vlue computtion is performed s rithmetic men, using proprietry LbView FPGA block. This men vlue is memorized nd is subtrcted from smples next PRI. It ws experimentlly observed tht men is very similr from one PRI to nor. After upper side buffer hs been completely filled, strt second counter is triggered. This counter increments ddresses RX2 memories, refore filling downside buffers with smples. After number 448 clock periods (equl to K, when first complete overlp RX1 nd RX2 smples tkes plce), down counter lso issues dt vlid signl, mening tht first smple computed cross-correltion is redy. Ech complex smple from first buffer is multiplied with its correspondent from second buffer, nd results se multiplictions re summed with dders in sme block, resulting one complex number per ech clock cycle. This opertion hppens t ech clock cycle, until RX2 memory ws completely swept through buffer. A pseudocode description se opertions cn be observed in Algorithm 1: Algorithm 1: Cross-Correltion Computtion Inputs: S_RX1, S_RX2 Output: XCORR 1 for n = 1 to ( ) do 2 BUFFER2 = flip(s_rx2(n to n + 447)) 3 for k = 0 to 447 do 4 XCORR[n] = XCORR[n] + conjugte(s_rx1[k])*buffer2[k] 5 end for 6 end for 7 return XCORR where Buffer2 is contents complex buffer corresponding to RX2 memory t present clock cycle, nd flip mens horizontl flipping vector ( first element becomes lst, second becomes lst but one, nd so on). opertions corresponding to inner for (lines 3, 4 nd 5) re computed in single system clock period. As soon s dt vlid signl goes high, smples re processed by next blocks, which compute mgnitude nd phse cross-correltion. mgnitude is obtined by summing squres rel nd imginry prts, n by computing squre root sum. A rectngulr to polr converter block is used to compute phse cross-correltion. Multiplictions nd summtions increse number bits result. number 448 multiplictions nd 447 summtions yield result with 42-bit width. After squre vlues computtion, bit width increses t 84 bits, nd summtion between results outputs n

8 Sensors 2019, 19, bit width. number bits is truncted to 64 nd smples result re sent to host PC usingsensors two2018, FIFOs. 18, x FOR PEER totlreview FPGA resource utiliztion cn be found in Appendix A cross-correltionimplementtion cn be performed directly in time domin, or in frequency domin cross-correltionimplementtion by multiplying computed cn be performed FFTs directly inputin signls time nd domin, n trnsforming bck frequency ( to time domin domin by multiplying using IFFT. For computed time-domin FFTs pproch, input signls computtionl nd n trnsforming complexity bck is O N 2) to time domin using IFFT. For time-domin pproch, computtionl complexity is, while for single FFT block computtionl complexity is O(N log 2 N), where N is ΟN $, while for single FFT block computtionl complexity is ΟN log $ N, where N is length length input input sequence. sequence. For For frequency frequency domin domin pproch, re re re two FFT blocks, one IFFT block, IFFT complex block, complex conjugtion conjugtion block nd block multipliction nd multipliction block. block. computtionl complexity time domin time pproch domin pproch is pproximtely is pproximtely 17 times17 higher times thn higher tht thn tht frequency frequency domin domin pproch. pproch. Lbview FPGA contins intellectul-property blocks for FFT implementtion, which llow for low Lbview degree FPGA customizbility contins intellectul-property order to djustblocks ltency for FFT versus implementtion, resource usge. which llow Although for low degree customizbility in order to djust ltency versus resource usge. Although usge se blocks is more computtionlly efficient, y fer long response time (ltency). usge se blocks is more computtionlly efficient, y fer long response time (ltency). Prlleliztion se blocks is possible, but not s convenient to implement s time domin Prlleliztion se blocks is possible, but not s convenient to implement s time domin version cross-correltion. version cross-correltion. Even Even if if time time domin domin implementtion is is more morecomputtionlly complex complex nd nd more more resource-demnding, it ws it chosen ws chosen becuse becuse it cnit esily cn be esily prllelized be prllelized nd obtins nd fster obtins computtion fster time. computtion Fst computtion time. Fst time computtion is key design time is prmeter key design prmeter this system. this system. Figure Figure 6 shows 6 shows timing digrm events during single PRI. PRI. trnsmit trnsmit nd receive nd receive opertions opertions strt strt simultneously. As soon As s soon s receive receive time finishes, time finishes, cross correltion cross correltion computtion strts. computtion cross-correltion strts. cross-correltion is computed inis computed µs. in μs. Figure Figure 6. Timing 6. Timing digrm digrm opertions performed during PRI. PRI. smpling smpling clock clock period period is is denoted denoted Tsmp_clk nd nd system clock period is denoted Tsys_clk. system system clock clock period period is four is four times times greter greter thn thn smpling clock period. time vilble for for dt dt trnsfer from from FPGA FPGA to host to host nd dditionl nd dditionl host host processing is is time left fter end cross-correltion computtion until until next next PRI. PRI. rnge rnge prile prile dt dt hs hs size size 350 kbits, nd ndis is trnsferred from from FPGA FPGA to tohost host computer in 110 μs, ccording to specifictions PCI-Express interfce. computer in 110 µs, ccording to specifictions PCI-Express interfce. time left until next PRI is used for computtions performed on host, which will time left until next PRI is used for computtions performed on host, which will be be described in next chpter. described in next chpter. rnge resolution cell cn be determined using stndrd formul. Since chirp bndwidth rngeis resolution 40MHz, cell rnge cnresolution be determined cell is 3.75m. usingin order stndrd to determine formul. mesurement Since chirp bndwidth rnge, is rectngulr 40 MHz, metl rnge trget resolution is considered, cell with is 3.75 size m. In26 order cm 30cm, to determine which yields n mesurement RCS rnge, 1.55m rectngulr 2 [16]. metl bndwidth trget is considered, receiver is with 160MHz size nd 26required cm 30signl cm, which to noise yields rtio n is RCS dB, m 2 in [16]. order to perform bndwidth displcement receiver mesurements is 160with MHz nd certin stndrd required devition, signl to s it noise will be rtio is

9 Sensors 2018, 18, x FOR PEER REVIEW 9 16 Sensors 2019, 19, described in section 7. rdr eqution is used in order to determine mesurement rnge t vlue 92m. 10dB, in order to perform displcement mesurements with certin stndrd devition, s it will be A summry prmeters implemented system is found in Tble 1. described in section 7. rdr eqution is used in order to determine mesurement rnge t Tble 1 vlue 92 m. Prmeters implemented rdr system A summry prmeters implemented system is found in Tble 1. Crrier frequency GHz Trnsmitted power Tble 1. Prmeters implemented rdr 30 dbm system. Chirp bndwidth 40 MHz Rdr System Prmeters Rnge resolution cell 3.75m Mximum detectble trget Crrier rnge frequency 92m GHz Trnsmitted power 30 dbm Trnsmit pulse durtion Chirp bndwidth 3.73μs 40 MHz Receive window durtion Rnge resolution cell 26.13μs 3.75 m Cross-correltion computtion Mximum detectble time trget rnge μs 92 m Trnsmit pulse durtion 3.73 µs Pulse Repetition Intervl 10ms Receive window durtion µs Tble 1. Prmeters Cross-correltion implemented computtion rdr system time µs Pulse Repetition Intervl 10 ms 6. Host Side Interfce 6. Host Side Interfce host computer sets periodicity trigger signl for trnsmitting chirp nd receives host smples computer sets rnge periodicity prile (mgnitude triggernd signl phse) for trnsmitting from FPGA. chirp An nd exmple receives signls smples obtined fter rnge prile FPGA (mgnitude processing nd nd phse) displyed from on FPGA. host An exmple computer cn signls be observed obtined fter in Figure FPGA 7. processing nd displyed on host computer cn be observed in Figure 7. Additionl signl processing is isperformed on on host hostpc, PC, using using LbView LbView environment. A Abin binfrom from prile prileis isselected, corresponding to to monitored trget. A trget bin is rnge correspondence round-trip dely time equl to to smpling period TTs. s. smpling frequency equls 120Msps. refore, rnge bin width is:.> δr = 2? 2 T 1.25 m ( S = 1.25 m (9) 9) Both rel nd imginry prt from chosen bin re recorded for specified number runs. Bothdisplcement rel nd is computed imginryusing prt from eqution chosen (6), with binf0=5.755 re recorded GHz. for specified number runs. is computed using Eqution (6), with f 0 = GHz. Figure 7. Resulted signls from FPGA rnge compression, bsed on RX1 nd RX2 signls plotted in Figure 7. Resulted signls from FPGA rnge compression, bsed on RX1 nd RX2 signls plotted Figure 4, s displyed on host interfce. pek in first plot indictes dely between in Figure 4, s displyed on host interfce. pek in first plot indictes dely between two signls. two signls.

10 Sensors 2018, 18, x FOR PEER REVIEW Sensors 2019, 19, Since rdr is cpble fst signl processing nd results disply, complex dt in bin Since interest rdr from is ech cpble fst generted signl processing rnge priles nd results cn be disply, used to smple complex dt mechnicl in bin motion interest from trget. ech By memorizing generted rnge vritions priles cn in be used bin to smple interest t ech mechnicl rdr pulse, motion two relevnt trget. plots By memorizing re obtined: one vritions with in displcement bin interest t ech trget rdr versus pulse, pulse two relevnt number, plots nd re nor obtined: one with one withfrequency displcement spectrum describing trget versus trget s pulsemotion. number, nd nor one with frequency A full spectrum pck selectble describing size is trget s recorded, motion. contining dt in rnge bin interest. size A full pck pcket equls selectble size number is recorded, processed contining rdr pulses. dt in Once rnge pck bin is interest. completed, size FFT is performed pcket equls upon number dt, in order processed to determine rdr pulses. vibrtion Once frequency pck is completed, spectrum. FFT is performed horizontl upon xis cn be dt, scled in order in frequency to determine vibrtion vibrtion or in velocity. frequency Ech spectrum. FFT result is horizontl plced in xis wterfll cn be scled type plot in in frequency order to observe vibrtion history or in velocity. frequency Ech FFT spectrum result is plced from in vibrting wterfll trget. type plot in order to observe history frequency spectrum from vibrting trget. 7. Vlidtion nd Experimentl Results 7. Vlidtion proposed nd Experimentl system cn Results be used for both displcement nd vibrtion monitoring. Two identicl proposed ntenns system (model cn MA-WA58-1X, be used for both mnufctured displcement by nd Mrs vibrtion Antenns, monitoring. Chicgo, TwoIL, identicl USA) ntenns mounted (model on sme MA-WA58-1X, pole were e used mnufctured for trnsmit by nd Mrs receive, Antenns, oriented Chicgo, in direction IL, USA) mounted trget. on sme pole were used for trnsmit nd receive, oriented in direction trget Outdoor Displcement Mesurement 7.1. Outdoor Displcement Mesurement A corner reflector ws mounted s trget nd is moved using liner motion system. liner A motion corner reflector system fetures ws mounted high s precision trget nd rotry is moved position using encoder, liner plced motionon system. shft liner motion electric system motor. fetures This sensor high imposes precision rotry liner position step size encoder, precision. plced Two on series shft sme electric scenrio motor. This were sensor performed, imposes t rdr liner to step trget size distnce precision. 7.5m Two series nd 30 m, t sme SNR scenrio vlues were 50 db performed, nd 26 db t respectively. rdr to trget A series distnce contins 7.5 m 20 nd steps, 30 m, moving t SNR vlues trget bck 50 db nd forth 26 db between respectively. two Adiscrete series contins positions 20 spced steps, 50 moving mm prt. trget bck nd forth between two discrete positions spced 50 mm prt. In order to to determine precision for for displcement mesurements, user cn user red cn red reltive chnge reltive in chnge position in position trget from trget one from step one to step next to one next in one grphicl in grphicl interfce. interfce. men vlues men vlues displcement displcement over 128 over pulses 128 re pulses recorded re fter recorded ech step. fter ech differences step. differences displcement mesurement displcement between mesurement successive between pulses successive re smll pulses nd re rndom smll nture. nd rndom Averging nture. is used Averging order to is mitigte used in order this effect. to mitigte phse this effect. unwrpping phse ws unwrpping performed mnully. ws performed errors mnully. mesurements errors cn mesurements be observed in cn Figure be observed 8. stndrd in Figure devition 8. stndrd errors devition recorded for errors thisrecorded cse 0.16 for mm this t cse most. is 0.16 mm t most. Figure 8. Displcement mesurement errors t 7.5 m nd t 30 m rnge. Note slightly lrger error for 30 m rnge. An dditionl mesurement set for displcement mesurement t trget rnge 30 m ws performed, but in different mnner: trget ws moved with 5 mm step in sme direction, for number 30 steps. displcement vlues were unwrpped mnully nd results re presented in Figure 9. Currently, re is no utomtic phse unwrpping procedure, s described in [17]. stndrd devition error is 0.16 mm.

11 Sensors 2019, 19, Sensors 2018, 18, x FOR PEER REVIEW Figure Displcement mesurement errors errors t 30 t m 30m rnge m rnge for 30for consecutive 30 consecutive steps insteps sme in direction, sme with direction, stepwith size step 5 mm. size 5mm. 5 A MATLAB simultion ws performed in order to to determine stndrd devition displcement mesurement t t different different signl-to-noise signl-to-noise rtio rtio vlues. vlues. A trnsmitted A trnsmitted nd nd received received chirp signl chirp signl re generted. re generted. Noise Noise ws dded ws dded on on received received chirp chirp signl, signl, in order in order to obtin to obtin ech ech desired desired SNR SNR vlues, vlues, mesured mesured on on rnge rnge prile. prile. scenrio scenrio ws repeted ws repeted for for number number 1000 reliztions reliztions. displcement displcement computed is computed using using phse phse in in rnge rnge prile prile bin bin interest, interest, with reltion with reltion (6). (6). simulted simulted results results cn becn observed be observed in Figure in Figure Additionlly, in order to to check results simultion, n nlyticl expression stndrd devition with respect to to SNR is is plotted. According to to [18], expression is is s s follows: σσ displ = λ displ = λ 1 E 4π (10) FGH I 4π J 1 ( 2 2 KL SNR SNR (10) nlyticl vlues re in good greement with simulted ones. As previously described, experimentl mesurements were performed t t two two rdr-to-trget rnges, which yield yield SNR SNR vlues vlues 50 50dB nd nd 26 26dB. dt dt points points re re lso lso plotted plotted on on chrt chrt Figure Figure 10, with 10, vlues with vlues close to close those to those or trces. or trces Simulted oreticl Experimentl Figure 10. Stndrd devition displcement mesurement versus signl-to-noise rtio, in simulted, oreticl nd experimentl cses Rel Rel Time Time Trget Trget Vibrtion Vibrtion Spectrum Spectrum Monitoring Monitoring SNR (db) rdr rdr sensor sensor is is cpble cpble monitoring monitoring motion motion chosen chosen trget trget nd nd trnsforming trnsforming it into it vibrtion into vibrtion spectrum. spectrum. In order In order to test to this test bility, this bility, vibrting vibrting trget trget ws built. ws built.

12 Sensors 2018, 18, x FOR PEER REVIEW Rel Time Trget Vibrtion Spectrum Monitoring rdr sensor is cpble monitoring motion chosen trget nd trnsforming it into Sensors vibrtion 2019, 19, 82 spectrum. In order to test this bility, vibrting trget ws built vibrting trget consists n udio speker, which hs n FR4 reinforced plte tied to its membrne. vibrting size trget consists rectngulr nreflecting udio speker, plte is which 26 cm hs 30cm. n FR4 reinforced speker plte is driven tied to by its generl-purpose membrne. size udio mplifier, rectngulr whose reflecting input is plte connected is 26 cm to 30 sinusoidl cm. speker signl genertor. is driven by For sensing generl-purpose mplitude udio mplifier, induced whose vibrtion, input is connected mechnicl to sinusoidl sensor consisting signl genertor. potentiometer For sensing ws mplitude included in induced fixture, vibrtion, with wiper mechnicl tied to sensor vibrting consisting plte. potentiometer A drwing ws included entire vibrting in fixture, trget with fixture, wiper including tied to mechnicl vibrting plte. sensor A cn drwing be observed entire in Figure vibrting 11. trget fixture, including mechnicl sensor cn be observed in Figure 11. () (b) Figure 11. () Vibrting trget mechnicl fixture drwing. An udio speker is used s vibrting Figure element, 11.() withvibrting metllic trget pltemechnicl mounted on fixture dust drwing. cp. AAn liner udio potentiometer speker is used is used s tovibrting sense element, vibrtionwith mplitude. metllic (b) plte Photogrphy mounted on ssembled dust cp. mechnicl A liner potentiometer fixture mounted is used on to tripod. sense vibrtion mplitude. (b) Photogrphy ssembled mechnicl fixture mounted on tripod. vibrting trget ws plced t distnce pproximtely 3 m from rdr. A sinusoidl signl vibrting 12 Hz frequency trget ws ws plced pplied t distnce to inputs pproximtely speker. 3 m from results rdr. A sinusoidl vibrtion signl monitoring 12 cn Hz be frequency seen in Figure ws pplied 12. FFTto is performed inputs bsed speker. on dt cptured results from vibrtion length monitoring 256 pulses. cn be observed seen in hrmonics Figure 12. re FFT presumed is performed to bebsed mechnicl on dt origin. cptured from length 256 pulses. vibrtion observed frequency hrmonics mesurement re presumed ccurcy to be is directly mechnicl reltedorigin. to ccurcy pulse repetition frequency, which is highly dependent on internl clock ccurcy USRP pltform. pulse repetition frequency is set by counter in FPGA, which increments its vlue once every smple clock period. smpling clock is derived from internl USRP clock, whose ccurcy cn be incresed using GPS disciplined oscilltor. resolution FFT spectrum is inversely proportionl to number rdr pulses used in computtion vibrtion spectrum. number rdr pulses used for computtion vibrtion spectrum is djustble. FFT length equls number pulses used for clcultion.

13 Sensors 2019, 2018, 19, 18, 82 x FOR PEER REVIEW Figure 12. Vibrtion monitoring on vibrting trget, set t 12 Hz frequency. Dt from 256 rdr pulses ws used for computtion this spectrum. fundmentl component t 12 Hz is most powerful, followed by wek hrmonics t 24 Hz nd 36 Hz Indoor vibrtion Vibrtionfrequency Mesurement mesurement ccurcy is directly relted to ccurcy pulse repetition In order frequency, to test which precision highly described dependent system on t vibrtion internl clock mplitude ccurcy mesurement, USRP pltform. sme vibrting pulse trget repetition s described frequency in is previous set by prgrph counter in wsfpga, plcedwhich t close increments rnge (3 m) its to vlue once rdrevery sensor. smple clock period. smpling clock is derived from internl USRP clock, whose ccurcy Vibrtions cn be incresed frequencies using GPS rnge disciplined 5 to 50oscilltor. Hz were pplied by speker to metl plte, in 5 Hz step resolution increments. FFT mplitude spectrum is inversely sinusoidl proportionl signl tto input number rdr speker pulses wsused kept in constnt computtion throughout entire vibrtion frequency spectrum. rnge, butnumber mechnicl rdr oscilltions pulses used did for not yield computtion constnt mplitude vibrtion vluesspectrum due to is mechnicl djustble. system FFT itself. length equls number pulses used for clcultion. system mesures rel time pek-to-pek vlue displcement recorded for trget bin, in sme mnner s described in first subprgrph this section Indoor comprison Vibrtion Mesurement between pek-to-pek vibrtion mplitudes mesured by potentiometer nd In order onesto mesured test precision by rdr cndescribed observed system in t Figure vibrtion 13. At mplitude low vibrtion mesurement, frequencies, sme re vibrting re differences trget between s described pek-to-pek in previous mplitudes prgrph recorded ws plced by t close two sensors rnge (3 m) upto to 2 rdr mm. sensor. cuse se errors my lso be relted to mechnicl oscilltion modes which pper longvibrtions FR4 plte, frequencies which yield in different rnge vibrtion 5 to 50 mplitudes Hz were pplied in center by speker plte to (where metl plte, mesuring 5 Hz sensor step increments. is locted) thn on mplitude its edges. Since sinusoidl trget signl is locted ininput sme rnge speker bin, ws n kept verge constnt vluethroughout se mplitudes entire is ctully frequency mesured. rnge, but mechnicl oscilltions did not yield constnt mplitude stndrd devition vlues due to error mechnicl betweensystem vibrtion itself. pek-to-pek mplitude mesured using system two methods mesures is 0.6 mm. rel time pek-to-pek vlue displcement recorded for trget bin, in sme mnner s described in first subprgrph this section. comprison between pek-to-pek vibrtion mplitudes mesured by potentiometer nd ones mesured by rdr cn be observed in Figure 13. At low vibrtion frequencies, re re differences between pek-to-pek mplitudes recorded by two sensors up to 2 mm. cuse se errors my lso be relted to mechnicl oscilltion modes which pper long FR4 plte, which yield different vibrtion mplitudes in center plte (where mesuring sensor is locted) thn on its edges. Since trget is locted in sme rnge bin, n verge vlue se mplitudes is ctully mesured.

14 Sensors 2018, 18, x FOR PEER REVIEW Sensors 2018, 18, FOR PEER REVIEW stndrd devition error between vibrtion pek-to-pek mplitude mesured Sensors 2019, stndrd 19, 82 devition error between vibrtion pek-to-pek mplitude mesured using two methods is 0.6 mm using two methods is 0.6 mm. Figure 13. Indoor vibrtion mplitude mesurement results, for frequency rnge from 5 Hz to 50 Hz Figure 13. Indoor vibrtion mplitude mesurement results, for frequency rnge from Hz to 50 Hz (hlf PRF rdr, in order to prevent lising). indoor trget ws plced t rnge 3 m. (hlf PRF rdr, in order to prevent lising). indoor trget ws plced t rnge 3 m Outdoor Outdoor Vibrtion Vibrtion Mesurement Mesurement sme sme mesurement mesurement setup setup ws ws repeted repeted in in n n outdoor outdoor scene, scene, with with distnce distnce between between rdr rdr nd nd vibrting vibrting trget trget pproximtely pproximtely m. m. vibrtion vibrtion mplitudes mplitudes mesured mesured by by mechnicl mechnicl sensor sensor were were recorded recorded gin. gin. pek-to-pek pek-to-pek vibrtion vibrtion mplitude mplitude vlues vlues mesured mesured by by potentiometer potentiometer nd nd rdr rdr cn cn be be observed observed in in Figure Figure stndrd stndrd devition devition error error between between vibrtion vibrtion pek pek to to pek pek mplitude mplitude mesured mesured using using two two methods methods is is mm, mm, similr similr to to one one obtined obtined in in indoor indoor mesurement mesurement set. set. Figure 14. Outdoor vibrtion mplitude mesurement results, for frequency rnge from 5 Hz to 50 Figure 14. Outdoor vibrtion mplitude mesurement results, for frequency rnge from 5 Hz to 50 Hz. rdr to trget rnge ws pproximtely 10 m. Hz. rdr to trget rnge ws pproximtely 10 m. cuses cuses errors errors for for both both indoor indoor nd nd outdoor outdoor mesurements mesurements re re probbly probbly spurious spurious cuses errors for both indoor nd outdoor mesurements re probbly spurious chnges chnges nd nd instbility instbility vibrting vibrting trget trget mechnicl mechnicl fixture. fixture. chnges nd instbility vibrting trget mechnicl fixture. 8. Conclusions 8. Conclusions 8. Conclusions A rdr sensor with cpbility monitoring rel time displcement nd vibrtion remote rdr sensor with cpbility monitoring rel time displcement nd vibrtion remote trgets A rdr ws presented sensor with in thiscpbility pper. FPGA monitoring bsebnd rel time prtdisplcement nd host computer nd vibrtion signl processing remote trgets ws presented in this pper. FPGA bsebnd prt nd host computer signl processing trgets prts were ws implemented presented in nd this tested pper. on indoor/outdoor FPGA bsebnd rel-world prt nd scenrios. host computer signl processing prts were implemented nd tested on indoor/outdoor rel-world scenrios. prts were min implemented fetures nd thistested rdron reindoor/outdoor rel time rnge compression rel-world scenrios. nd disply rnge priles min fetures this rdr re rel time rnge compression nd disply rnge t fst PRFmin rtes fetures (100 Hz). It this lsordr cpble re rel vibrtion time rnge spectrum compression monitoring nd (updisply to 50 Hz) on desired rnge priles t fst PRF rtes (100 Hz). It is lso cpble vibrtion spectrum monitoring (up to 50 Hz) priles trget. Since t fst it is PRF noncontct rtes (100 Hz). method It is lso displcement cpble nd vibrtion vibrtion spectrum monitoring monitoring for remote (up to trgets, 50 Hz) it on desired trget. Since it is noncontct method displcement nd vibrtion monitoring for on cn successfully desired trget. be used Since whenever it is noncontct rel time disply method dt displcement necessry. nd vibrtion monitoring for remote trgets, it cn successfully be used whenever rel time disply dt is necessry. remote trgets, present it pper cn successfully proves thtbe used system whenever is functionl rel time in its disply experimentl dt is stte. necessry. experiments performed cover specific scenrios. In order to fully chrcterize instrument, more experiments re required in order to determine its sensitivity, resolution nd mesurement rnge.

15 Sensors 2019, 19, displcement nd vibrtion results fered by rdr were compred to ones mesured with nor sensor nd showed good greement. precision this rdr system is estimted (using 3σ pproximtion) t 0.6 mm for displcement mesurements nd 1.8 mm for vibrtion mplitude mesurements. Or systems ment for displcement mesurements hve been described in reserch ppers. For exmple, n interferometric SAR experiment [18] with stellite-borne rdr hs shown precision 0.75 mm ( stndrd devition displcement errors) for signl to clutter rtio pproximtely 12 db. Commercil rel perture rdr systems such s FASTGBSAR-R [19] fer n ccurcy 0.01 mm, s stted by mnufcturer. In future, spectrl estimtion techniques (Cpon, MUSIC [20]) could be used insted FFT on host processing prt. Author Contributions: Conceptuliztion, M.-L.T.; Dt curtion, A.A.; Investigtion, M.-L.T.; Methodology, R.C.; Project dministrtion, M.D.; Resources, M.D.; Supervision, A.A., R.C. nd M.D.; Vlidtion, A.A.; Writing originl drft, M.-L.T.; Writing review & editing, A.A., R.C. nd M.D. Funding: This reserch received no externl funding. Conflicts Interest: uthors declre no conflict interest. Abbrevitions following bbrevitions re used in this mnuscript: USRP FPGA FMCW SAR UAV PRF PRI SNR Universl Stwre Rdr Peripherl Field-Progrmmble Gte Arry Frequency-Modultion Continuous Wve Syntic Aperture Rdr, Unmnned Aeril Vehicle Pulse Repetition Frequency Pulse Repetition Intervl Signl to Noise Rtio Appendix A Kintex 7 XC7K4107 FPGA resource utiliztion is s follows: 76.9% totl slices, 11.9% slice registers, 66.3% slice LUTs, 65.8% block RAMs nd 100% DSP48 cells. References 1. Kirubrjn, T.; Br-Shlom, Y. Low observble trget motion nlysis using mplitude informtion. IEEE Trns. Aerosp. Electron. Syst. 1996, 32, [CrossRef] 2. Ciuonzo, D.; Willett, P.K.; Br-Shlom, Y. Trcking trcker from its pssive sonr ML-PDA estimtes. IEEE Trns. Aerosp. Electron. Syst. 2014, 50, [CrossRef] 3. Vinci, G.; Lindner, S.; Brbon, F.; Mnn, S.; Hmnn, M.; Dud, A.; Weigel, R.; Koelpin, A. Six-Port Rdr Sensor for Remote Respirtion Rte nd Hertbet Vitl-Sign Monitoring. IEEE Trns. Microwve ory Tech. 2013, 61, [CrossRef] 4. Bugev, A.S.; Vsil ev, I.A.; Ivshov, S.I.; Chpurskii, V.V. Rdr Methods Detection Humn Brething nd Hertbet. J. Commun. Technol. Electronic 2006, 51, [CrossRef] 5. Gentile, C. Vibrtion mesurement by rdr techniques. In Proceedings 8th Interntionl Conference on Structurl Dynmics, EURODYN, Leuven, Belgium, 4 6 July Moll, J.; Bechtel, K.; Hils, B.; Krozer, V. Mechnicl Vibrtion Sensing for Structurl Helth Monitoring Using Millimeter-Wve Doppler Rdr Sensor. In Proceedings Europen Workshop on Structurl Helth Monitoring, Nntes, Frnce, 8 11 July Vinci, G.; Linz, S.; Mnn, S.; Lindner, S.; Brbon, F.; Weigel, R.; Koelpin, A. A Six-Port Rdr System for Precise Distnce Mesurements nd Vibrtion Monitoring in Industril Environments. In Proceedings Sensors nd Mesuring Systems 2014; 17. ITG/GMA Symposium, Nuremberg, Germny, 3 4 June 2014.

16 Sensors 2019, 19, Rffo, A.; Costnzo, S.; Di Mss, G. Stwre Defined Doppler Rdr s Contctless Multipurpose Microwve Sensor for Vibrtions Monitoring. Sensors 2017, 17, 115. [CrossRef] [PubMed] 9. Ding, L.; Ali, M.; Ptole, S.; Dbk, A. Vibrtion Prmeter Estimtion Using FMCW Rdr. In Proceedings IEEE Interntionl Conference on Acoustics, Speech nd Signl Processing (ICASSP), Shnghi, Chin, Mrch Nieh, C.M.; Hung, T.Y.; Lin, J. Antenn Rdition Pttern Effects on Short-Rnge Vibrtion-Detection Rdr System. In Proceedings 2014 Interntionl Symposium on Antenns nd Propgtion Conference Proceedings, Kohsiung, Tiwn, 2 5 December Xiong, Y.; Peng, Z.; Xing, G.; Zhng, W.; Meng, G. Accurte nd Robust Displcement Mesurement for FMCW Rdr Vibrtion Monitoring. IEEE Sens. J. 2018, 18, [CrossRef] 12. Cppuccino, G.; Cocorullo, G.; Corsonello, P.; Schirinzi, G. Design nd demonstrtion rel time processor for one-bit coded SAR signls. IEE Proc.-Rdr Sonr Nvig. 1996, 143, [CrossRef] 13. Fischmn, M.; Berkun, A.; Chun, W.; Im, E.; Andrk, R. An Onbord Processor nd Adptive Scnning Controller for Second-Genertion Precipittion Rdr. IEEE Trns. Geosci. Remote Sens. 2005, 43, [CrossRef] 14. Lou, Y.; Clrk, D.; Mrks, P.; Muellerschoen, R.J.; Wng, C.C. Onbord Rdr Processor Development for Rpid Response to Nturl Hzrds. IEEE J. Sel. Top. Appl. Erth Obs. Remote Sens. 2016, 9, [CrossRef] 15. Anghel, A.; Ccovenu, R.; Moldovn, A.S.; Popescu, A.A.; Dtcu, M. Simplified Bisttic SAR Imging with Fixed Receiver nd Terr SAR-X s Trnsmitter Opportunity-First Results. In Proceedings IEEE Interntionl Geoscience nd Remote Sensing Symposium (IGARSS), Beijing, Chin, July Mhfz, B.R. Rdr Systems Anlysis nd Design Using MATLAB; Chpmn nd Hll: New York City, NY, USA, June Dudczyk, J.; Kwlec, A. Optimizing minimum cost flow lgorithm for phse unwrpping process in SAR rdr. Bull. Pol. Acd. Sci. Tech. Sci. 2014, 62, [CrossRef] 18. Ferretti, A.; Svio, G.; Brzghi, R.; Borghi, A.; Muszzi, S.; Novli, F.; Prti, C.; Rocc, F. Submillimeter ccurcy InSAR time series: Experimentl vlidtion. IEEE Trns. Geosci. Remote Sens. 2007, 45, [CrossRef] 19. FASTGBSAR-R, Metsensing Rdr Solutions. Avilble online: MetSensing-FstGBSAR-R.pdf (ccessed on 13 December 2018). 20. Ciuonzo, D.; Romno, G.; Solimene, R. Performnce nlysis time-reversl MUSIC. IEEE Trns. Signl Process. 2015, 63, [CrossRef] 2018 by uthors. Licensee MDPI, Bsel, Switzerlnd. This rticle is n open ccess rticle distributed under terms nd conditions Cretive Commons Attribution (CC BY) license (