An Integrated Three-port DC/DC Converter for High- Voltage Bus Based Photovoltaic Systems

Transcription

1 An Inegraed Three-por DC/DC Converer for High- Volage Bus Based Phoovolaic Sysems Junyun Deng, Suden Member, IEEE, Haoyu Wang, Member, IEEE, and Ming Shang School of Informaion Science and Technology ShanghaiTech Universiy, Shanghai, China Absrac In high-volage bus based phoovolaic sysems, a power elecronic inerface is required o manage he power flow in beween he PV panel, baery, and he high-volage dc bus. In his paper, a novel hree-por dc/dc opology is proposed for his applicaion. Pulse widh and phase shif offer wo degrees of freedom o effecively regulae he power flows. On he primary side, he inpu curren ripple is reduced due o he inerleaved srucure. This avoids he usage of he bulky elecrolyic capacior on he PV erminal. On he secondary side, a volage sixfolder recifier is employed o boos he sep-up raio. This reduces he urns number on he secondary-side of he ransformer. Moreover, he volage sresses of secondary-side MOSFETs and diodes are reduced o one-hird of he oupu volage. Zero-volage swiching and zero-curren swiching are realized among all power MOSFETs and diodes respecively and in an exended range. A 500 W converer prooype, linking a 40 V-60 V baery pack, a 20 V- 30 V PV panel, and a 760 V dc bus, is designed and esed o verify he proof-of-concep. Boh he circui funcionaliy and heoreical analysis are validaed by he experimenal resuls. Index Terms high-volage bus, phase-shif modulaion (PSM), pulse-widh modulaion (PWM), hree-por converer, zero-volage swiching (ZVS). I. INTODUCTION In phoovolaic (PV) based microgrid sysems, high-volage (760 V) dc bus wih half-bridge micro-inverer is considered as an aracive soluion [1]. This is because he half-bridge srucure is feaured wih reduced componens coun, enhanced power densiy, and improved reliabiliy [2]. Besides, due o he power mismach beween he PV generaor and he load, a baery pack is required o serve as he energy buffer. Therefore, in he fron sage, a hree-por converer (TPC) is necessary o manage he power flow in beween he PV panel, baery pack, and he high-volage bus. The diagram of such a microgrid sysem is illusraed in Fig. 1. To realize he TPC, he convenional mehod is o use muliple discree converers [3], [4]. This jeopardizes he power densiy and conversion efficiency. Moreover, differen conrol sraegies such as maximum power poin racking (MPPT), baery charging/discharging and load regulaion need o be addressed separaely. To improve, he concep of inegraed TPC has been proposed. Inegraed soluion is feaured wih: 1) reused circui componens, 2) reduced power conversion sages, and 3) cenralized conrol sraegy. Due o hose advanages, inegraed TPC opologies and he corresponding conrol sraegies have araced wide research aenion in recen years. Inegraed TPC opologies can be classified ino hree < 30 V Three-por Converer Baery DC Bus 760 V Half Bridge Inverer 50 Hz 220 V Local Load AC Grid Fig. 1. The srucure of hree-por 760V dc bus based PV microgrid. caegories: non-isolaed TPCs, hree-por isolaed TPCs, and wo-por isolaed TPCs. By inegraing coupled inducors ino Boos or Buck-Boos opologies, muliple non-isolaed TPCs are derived in [5] [8]. The high volage gain wih moderae duy cycle can be achieved. However, non-isolaed TPC is usually no considered due o he galvanic isolaion requiremen in high-volage bus applicaions. Alernaively, some hree-por isolaed TPCs are proposed in [9] [12]. Those converers are usually based on half-bridge, boos-half-bridge or full-bridge srucures. A hree-winding ransformer is employed o realize muli-direcional power flow. The ransformer urns raio can be easily cusomized o accommodae differen volage levels. However, he swich coun is large, which leads o increased manufacuring cos and conducion loss. Furhermore, he design of he magneic componen is complicaed. Compared wih hree-por isolaed soluion, wo-por isolaed TPC is more aracive. I offers galvanic isolaion beween he high and low volage sides, and can easily accommodae differen volage levels. Furhermore, i is feaured wih reduced swich coun and simpler ransformer design. By inegraing he boos converer ino he phase-shiffull-bridge (PSFB) converer, a group of ZVS TPCs is proposed in [13] [15]. However, here are some inrinsic disadvanages inheried from PSFB opology [16]: 1) high conducion loss in he freewheeling sage, 2) consrained ZVS range on he primary side MOSFETs, 3) duy cycle loss due o he exisance of oupu filer inducor, and 4) volage spike and reverse recovery issues on he recificaion diodes due o he clamping effec of he oupu capacior. Furhermore, he curren ripple on he PV panel is large. Large curren ripple is harmful for he PV panel lifeime. In [17], inerleaving echnique is inroduced o he primary side and helps o reduce he curren ripple. However, in disconinuous conducion mode (DCM), he curren sress and conducion loss are large, and a Boos inegraed wih ZVS LLC opology is proposed in [18]. I adops pulse-widh and pulse-frequency hybrid regulaion scheme and his conrol scheme is difficul o implemen. I is worhy menioning ha mos of he sae-of-he-ar wo /18/$ IEEE 5948

2 i D3 D V ba V pv i L1 i L2 i D1 vgs v gs dead β v gs1 v gs4 v gs2 v gs3 Fig. 2. Schemaic of he proposed hree-por opology. v gs v gs6 v gs5 por isolaed TPCs adop half/full bridge recificaion sage on he oupu side. Therefore, o realize a high sep-up raio, a ransformer wih large secondary-side urns number is required. This degrades he sysem power densiy. In addiion, he volage sresses of he secondary-side swiches equal he oupu volage or wice of he oupu volage. This brings challenges o he opimal selecion of semiconducors in high-volage applicaions. In [19], [20], he volage quardrupler recifier is adoped in high-volage bus based PV sysems. This recifier owns he benefis of moderae secondary-side urns number and low volage sresses on he high-volage side. However, he curren ripples of he PV panel are large. In addiion, he volage regulaion is based on singular pulse-frequency or phase-shif modulaion. Thus, i is infeasible o deploy hose opologies ino he hree-por applicaions. In his paper, a novel wo-por isolaed inegraed TPC is proposed. The proposed opology is derived from inerleaved Boos opology and acive volage sixfolder recifier. The phase shif on he acive recifier brings anoher modulaion scheme, which accommodaes he conrol of hree-por power flows. This makes i a good candidae for high-volage bus based PV sysems. In comparison wih he prior ars, i demonsraes following advanages:1) PV panel curren ripple is reduced remarkably; 2) ZVS and ZCS ranges are effecively exended; 3) a high sep-up raio is realized wih a moderae ransformer secondary-side urns number; 4) he volage sresses on he secondary-side semiconducors are reduced. II. OPEATION PINCIPLES A. Topology Descripion Fig. 2 shows he schemaic of he proposed TPC. The primary-side circui is he parallel of wo synchronized recified boos unis, including wo inducors ( and ) and four power MOSFETs -. The driving signals for and ( and ) are complemenary wih cerain deadband. The wo parallel phase legs are driven in an inerleaved manner wih 180 phase shif. The duy cycle of s gae signal is defined as D. The power flow beween he PV panel and he baery can be regulaed by D. The ransformer urns raios is defined as. On he secondary side, and are driven complemenarily wih fixed 0.5 duy cycle. Cerain phase shif (β) beween he swich paerns of S1 and is enforced o regulae he power delivered o he load. The phase shif raio is defined as D ph = β/π. Based on he range of D and β, he seady-sae operaion can be classified ino four saes. The operaion sae wih D < 0.5 and β > 0 is adoped in his work. This main sae is discussed and analyzed in deail. v cd i D i S i D i L i D2 i D4 i L1 i S5 i D1 i D3 i L In his sae, here are 14 operaion modes in one swiching period. Considering he circui symmery, only 7 operaion modes in a half swiching period are presened. and are sufficienly large o keep he i L1 and i L2 is coninuous. The secondary-side capaciances are sufficienly large wih ignorable volage ripple. According o he principles of he secondary-side recifiers, he relaionship beween he ampliudes of V cd and can be expressed as, V = V 6 (1) cd The key waveforms are ploed in Fig. 3 and he corresponding equivalen circuis are presened in Fig. 4. Mode I: [ 0, 1). Before 0,,4,5 are ON and he secondaryside diodes,4 conduc. The inducor curren < 0. and are energized by he PV panel. A 0, is urned off. flows from he source o drain of. release power o he baery and while coninues o be energized. During he deadband, he negaive curren discharges he oupu capacior () of,2. Mode II: [ 1, 2). A 1, is urned on wih ZVS naurally. A he end of his mode, and are urned off naurally wihou reverse-recovery losses. begins o only flow hrough and coninues o decrease. Mode III: [ 2, 3). During his mode, is charged while o i S6 Fig. 3. Converer seady sae waveforms. 5949

3 Vba (a) n v cd /2 v cd V p V s ω ω Vba Vba Vba Vba Vba Vba (b) (c) (d) (e) (f) (g) Fig. 4. Converer equivalen circuis. (a) Mode I, 0 < 1. (b) Mode II, 1 < 2. (c) Mode III, 2 < 3. (d) Mode IV, 3 < 4. (e) Mode V, 4 < 5. (f) Mode VI, 5 < 6. (g) Mode VII, 6 < is discharged. coninues o release power. Mode III ends when crosses zero. Mode IV: [ 3, 4). A 3, becomes posiive and increases linearly. i S5 becomes posiive. This means i S5 only flows channel. A 4, is urned off; he body diode of,, and begin o conduc. Mode V: [ 4, 5). During his mode, i S6 is sill negaive. This means he ZVS for he secondary-side MOSFETs occurs naurally wihou any deadband. decreases linearly. A he end of his mode, is urned off. Mode VI: [ 5, 6). This mode is similar o Mode I. During his shor inerval, of 2 is discharged o zero. This creaes a ZVS condiion for. A 5, is energized by he PV panel. Mode VII: [ 6, 7). A 6, channel conducs wih zero volage. A he end of his mode, is urned off and he body diode of conducs. III. CICUIT MODELING AND ANALYSIS A. Circui Modeling and Oupu Power Analysis The proposed opology can be simplified ino an equivalen circui, as shown in Fig. 5 (a). The ypical waveforms of and v cd are demonsraed in Fig. 5 (b). According o he Fourier analysis, and v cd can be expressed as, Where 4Vba α vab = cosi sin( iω0) i= 1,3,5,... iπ 2 2Vo vcd = sin ( ω0 β α 2) 3 π i i i= 1,3,5,... ( D) π ( D< ) ( D ) π ( D> ) 20.5, 0.5 α = 2 0.5, 0.5 The oupu power wih D < 0.5 can be derived as, B, i i= 1,3,5,... (a) Fig. 5. The model of he proposed converer. (a) he equivalen circui, (b) volage waveforms. { } ( ) ( ) Po = P cos i 0.5 D π sin iβ D π (4) where β + (0.5 - D)π < π, and P B,i is he normalized power. P O ba Bi, 3 3 3i π f0llk (2) (3) = 4nV V (5) In order o simplify he analysis, only he fundamenal componen is considered. The corresponding resul is ploed in (b)

4 Normalized Po Fig. 6. As indicaed, he oupu power curve is symmerical o D = 0.5; β and 2Dπ - β correspond o he same P o. Thus, here are wo symmeric phase-shif regulaion ranges [0, Dπ) and [Dπ, Dπ + 0.5π). In [0, Dπ), P o increases wih he increase of phase shif angle. While in [Dπ, Dπ + 0.5π), P o decreases wih he increase of phase shif angle. B. Volage Gain The primary side is essenially an inerleaved boos converer. Thus, he relaionship beween and Vba is derived as, V D=0.6(0.4) D=0.7(0.3) ba D= Phase shif raio D ph Fig. 6. Curves of oupu power varied versus phase shif raio under differen duy cycles. = (6) D When he gae signals of he secondary-side MOSFETs are removed, he MOFSETs funcions as diodes. The corresponding β equals zero and he secondary side becomes a volage muliplier. Thus, Vo = 6nVba (7) The corresponding volage gain is, 6n G = Vo / VPV = (8) D The gain curves versus D =1-D wih differen ransformer urns raios are ploed in Fig. 7. A high volage gain is achieved in passive volage muliplier converer, even when he ransformer urns raio and he duy cycle are moderae. Furhermore, when he gaes signals of he secondary-side MOSFETs are enabled, he phase shif conrol works. Due o he addiion of a conrol freedom, he volage gain regulaion range is changed from a single curve o wo-dimensional region. Compared wih passive volage muliplier converer, he regulaion flexibiliy of volage gain is enhanced. Therefore, a high sep-up raio can be achieved in he proposed opologies. C. Sof Swiching 1) Secondary-side Swiches To ensure ZVS, of MOSFET should be fully discharged before he channel conducs. As shown in Fig. 3, a negaive curren exiss before he gae signal is applied. This indicaes a clear ZVS. Meanwhile, he secondary-side diodes urn-off di/d is consrained by. This indicaes a robus ZCS urn-off of he diodes. Hence, he reverse recovery issues can be effecively miigaed. Volage gain G ) Primary-side MOSFETs As demonsraed in Fig. 8, he ZVS condiion of he primary-side MOSFETs can be expressed as, S1 : i( S1) n( S1) > Imin S : i ( ) ni ( ) < I S : i ( ) + ni ( ) > I S : i ( ) + ni ( ) < I 2 L1 S2 Llk S2 min 3 L2 S3 Llk S3 min 4 L2 S4 Llk S4 min where s1~ s4 are he urn-on ime of ~, respecively. In he energy sorage perspecive, he minimum curren o charge and discharge of wo complemenary MOSFETs is defined as, I min n=1.5 n=1 2 2 Coss Vba lk n=0.5 Duy cycle prime D Fig. 7. Curves of volage gain varied versus D under differen urns raios. Baery i L1 Baery Fig. 8. ZVS condiions for primary-side swiches. (9) = (10) L According o he basic principles of boos converer, i L1 and i L2 are derived as, Ppv VPV ( S1) = ( S3) = + ( 1 D) TS 0 2 2L Ppv VPV i( S2) = ( S4) = ( 1 D) TS 0 2 2L (11) According o he seady-sae analysis of he primary-side circui, i Lk is expressed as ( S1) = ( ) = ( 0) < 0 ( ) = ( ) = ( 6) > 0 (12) i L I should be noed ha he ZVS condiions for and ( and ) are he same. According o Eq. (9-12) and Fig. 8, he

5 TABLE I COMPAISON OF COMPONENT VOLTAGE STESSES Secondary-side ecifier MOSFETS & diodes Capaciors Half-wave recifier 2Vo Vo Full-wave recifier 2Vo Vo ZVS v gs1 (25V/div) v ds1 (125V/div) Full-bridge recifier Vo Vo Volage quadrupler recifier Vo/2 Vo/2, Vo/4 This work Vo/3 Vo/2,Vo/4,Vo/6 i pv (2A/div) v gs2 (25V/div) ZVS v ds2 (100V/div) (a) 2 μs/div i L2 (2A/div) i L1 (2A/div) v gs5 (25V/div) ZVS v ds5 (250V/div) 4 μs/div Fig. 9. The seady sae curren waveforms of he primary side. Fig. 10. The seady-sae key waveforms. (100V/div) v cd (250V/div) (20A/div) 1 μs/div ZVS condiion for he proposed converer is raher differen from he radiional PSFB converer. This is mainly due o he exisence of and. and exend he ZVS range of he upper swiches ( and ), while narrows he ZVS range of he lower swiches ( and ). Therefore, ZVS of he lower swiches is more imporan. D. Volage Sress The volage raings of he secondary-side swiches and capaciors need o be analyzed o faciliae he selecion of componens. In he proposed converer, heir volage sresses are summarized and compared wih he convenional srucures in Table I. As shown, he volage sresses of he secondary-side swiches and capaciors are much smaller han he convenional ZCS (b) i D1 (5A/div) 2 μs/div Fig. 11. Sof-swiching waveforms. (a) MOSFETs S1,2. (b) MOSFET S5 and Diode D1. srucures. This makes he proposed converer more suiable for high-volage applicaions. IV. EXPEIMENTAL ESULTS To verify he effeciveness of he proposed converer, a 500W converer prooype is designed. The key parameers are as follows. V pv = 20 V-30 V, V ba = 40 V-60 V, = 760 V, ransformer s urns raio n = 2, = 30 μh, = = 25 μh and he swiching frequency f s = 100 khz. Fig. 9 shows he experimenal seady-sae waveforms of he inducor currens on he primary side. As demonsraed, he curren ripple on he PV erminal is significanly reduced. The seady-sae key waveforms are capured in Fig. 10. The experimenal resuls agree wih he analysis. The swiching waveforms of he proposed converer are capured in Fig. 11. As shown in Fig. 11(a), here is no overlap beween he rising edge of v gs and falling edge of v ds. This validaes he ZVS of he primary side MOSFETs S1,2. Similarly, Fig. 11(b) proofs ha ZVS is realized on he secondary-side MOSFETs S5 and he diode D1 is urned off wih low di/d wihou any reverse recovery. The sof-swiching resuls agree wih previous analysis. 5952

6 Efficiency Baery o Load PV o Baery PV o Load Oupu power [W] Fig. 12. Measured efficiency versus he oupu power. The conversion efficiency is evaluaed in hree differen power ransfer pahs (PV o baery, baery o load, and PV o load). The resuls are shown in Fig. 12. The efficiency daa is calibraed wih a high-precision power analyzer (PPA4530 from Newons4h Ld). As shown, in PV o baery pah, he measured peak efficiency is 97%. In baery o load pah, he measured peak efficiency is 95%. In PV o load, he measured peak efficiency is 94%. V. CONCLUSION This paper proposes a novel inegraed high sep-up hreepor dc/dc converer for PV based microgrid sysems. The proposed opology is regulaed by primary-side pulse-widh and secondary-side phase-shif. I is feaured wih high inegraion and high power densiy. Exended ZVS and ZCS can be achieved for all MOSFETs and diodes, respecively. This resuls in low swiching loss and high efficiency. Due o he volage sixfoler recifier srucure, he volage sresses of he secondary-side componens are remarkably reduced. In comparison wih prior ars, he curren ripple of he PV panel is reduced due o he inerleaving srucure. Those feaures make he proposed opology a good candidae for high-volage bus based PV sysems. Topology feaures, operaional principles, and circui characerisics are analyzed in deail in his paper. A 500 W converer prooype is designed and demonsraes good efficiency performance. The circui analyses are validaed in he experimenal resuls. obus dynamic performance validaes he conrol scheme and regulaing sraegy. ACKNOWLEDGMENT This work was suppored in par by he Naional Naural Science Foundaion of China under Gran , and in par by he Shanghai Sailing Program under Gran 16YF [5] Y. M. Chen, A. Q. Huang, and X. Yu, A high sep-up hree-por DC-DC converer for sand-alone PV/baery power sysems, IEEE Trans. Power Elecron., vol. 28, no. 11, pp , Nov [6]. Faraji and H. Farzanehfard, Sof-swiched Non-Isolaed High Sep-up Three-por DC-DC converer for Hybrid Energy Sysems, IEEE Trans. Power Elecron., vol. 8993, no. c, pp. 1 10, [7] L. J. Chien, C. C. Chen, J. F. Chen, and Y. P. Hsieh, Novel hree-por converer wih high-volage gain, IEEE Trans. Power Elecron., vol. 29, no. 9, pp , [8] M. Shang, and H. Wang, A ZVS inegraed single-inpu-dual-oupu converer for high sep-up applicaions, in Proc. IEEE Energy Conversion Congress and Exposiion, Milwaukee, WI, Sep [9] H. Tao, J. L. Duare, and M. A. M. Hendrix, Three-por riple-half-bridge bidirecional converer wih zero-volage swiching, IEEE Trans. Power Elecron., vol. 23, no. 2, pp , [10] C. Zhao, S. D. ound, and J. W. Kolar, An isolaed hree-por bidirecional dc-dc converer wih decoupled power flow managemen, IEEE Trans. Power Elecron., vol. 23, no. 5, pp , [11] L. Wang, Z. Wang, and H. Li, Asymmerical duy cycle conrol and decoupled power flow design of a hree-por bidirecional DC-DC converer for fuel cell vehicle applicaion, IEEE Trans. Power Elecron., vol. 27, no. 2, pp , [12] J. L. Duare, M. Hendrix, and M. G. Simoes, "Three-por bidirecional converer for hybrid fuel cell sysems," IEEE Trans. Power Elecron., vol. 22, no. 2, pp , Mar [13] H. Wu, P. Xu, H. Hu, Z. Zhou, and Y. Xing, Mulipor converers based on inegraion of full-bridge and bidirecional DC-DC opologies for renewable generaion sysems, IEEE Trans. Ind. Elecron., vol. 61, no. 2, pp , [14] W. Li, J. Xiao, Y. I. Zhao, and X. He, PWM plus phase angle shif (PPAS) conrol scheme for combined mulipor DC/DC converers, IEEE Trans. Power Elecron., vol. 27, no. 3, pp , Mar [15] W. Li, C. Xu, H. Luo, Y. Hu, X. He, and C. Xia, Decoupling-conrolled ripor composied DC/DC converer for muliple energy inerface, IEEE Trans. Ind. Elecron., vol. 62, no. 7, pp , Jul [16] H. Wang, M. Shang, and A. Khaligh, A PSFB-based inegraed PEV onboard charger wih exended ZVS range and zero duy cycle loss, IEEE Trans. Ind. Appl., vol. 53, no. 1, pp , [17] H. Wu, J. Zhang, X. Qin, T. Mu, and Y. Xing, Secondary-Side-egulaed Sof-Swiching Full-Bridge Three-Por Converer Based on Bridgeless Boos ecifier and Bidirecional Converer for Muliple Energy Inerface, IEEE Trans. Power Elecron., vol. 31, no. 7, pp , [18] X. Sun, Y. Shen, W. Li, and H. Wu, A PWM and PFM Hybrid Modulaed Three-Por Converer for a Sandalone PV/Baery Power Sysem, IEEE J. Emerg. Sel. Top. Power Elecron., vol. 3, no. 4, pp , [19] M. Shang and H. Wang, A Volage Quadrupler ecifier Based Pulse- Widh-Modulaed LLC Converer wih Wide Oupu ange, IEEE Trans. Ind. Appl., in press. DOI: /TIA [20] Y. Zhao, X. Xiang, W. Li, X. He, and C. Xia, Advanced symmerical volage quadrupler recifiers for high sep-up and high oupu-volage converers, IEEE Trans. Power Elecron., vol. 28, no. 4, pp , EFEENCES [1] W. Li and X. He, eview of Nonisolaed High-Sep-Up DC / DC Converers in Phoovolaic Grid Conneced Applicaions, IEEE Trans. Ind. Elecron., vol. 58, no. 4, pp , [2] M. Shang, H. Wang, and Q. Cao, econfigurable LLC opology wih squeezed frequency span for high-volage bus-based phoovolaic sysems, IEEE Trans. Power Elecron., vol. 33, no. 5, pp , [3] F. Nejabakhah and Y. W. Li, Overview of power managemen sraegies of hybrid ac/dc microgrid, IEEE Trans. Power Elecronics., vol. 30, no. 12, pp , 2015 [4] M. H. Nehrir e al., A review of hybrid renewable/alernaive energy sysems for elecric power generaion: Configuraions, conrol, and applicaions, IEEE Trans. Susain. Energy, vol. 2, no. 4, pp ,