EMBRACE DS5 presentation

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1 EMBRACE presentation Paris 4 th September 2006 ASTRON, The Netherlands

2 Acknowledgement The authors wish to acknowledge the enormous contribution of the whole EMBRACE team presently located at: ASTRON, Dwingeloo, NL OPAR and Nancay Team, FR INAF, Bologna, IT MPiFR, GE

3 Work Breakdown Structure

4 EMBRACE organisational Chart with Partners

5 Overview of the presentation Aims of EMBRACE System Level Overview Tile Architecture Progress with sub-systems design Costing Siting at WSRT & Nancay

6 Aims of EMBRACE To produce a low cost collector and a working Aperture Array Produce cost estimates Evaluate and compare its performance with Benchmark design

7 EMBRACE Requirements Specification Frequency range 500 MHz MHz. Polarisation Physical Collecting area Aperture Efficiency Electronic Scan Range T sys Element phase control accuracy Instantaneous bandwidth Dynamic range A/D Converter Number of independent FoV (RF beams) No of digital beams Single polarisation ~300 m 2 WSRT (100 m 2 Nançay) > 80% +-45 deg 1GHz (aim for 50K) 3 bit ( also time delays) 40 MHz (increased further with time delays) 60dB (effective # of bits) 2 8+

8 System level Overview

9 Tile Architecture

10 Antenna Antenna EMBRACE RF Architecture Antenna Antenna LNA LNA LNA LNA Coax Cable Coax Cable Coax Cable Coax Cable Buffer Amp 1:2 RF Power splitter 1:2 1:2 1:2 Buffer Amp 1: 2 RF Power splitter 1:2 1:2 1:2 Buffer Amp 1:2 RF Power splitter 1:2 1:2 1:2 Buffer Amp RF Power 1:2 splitter 1:2 1:2 1:2 Phase Shifter Phase Shifter Phase Shifter Phase Shifter RFIC 1 RF Power combiner 4:1 4:1 RFIC 1 RF Power combiner 4:1 4:1 RFIC 1 RF Power combiner 4:1 4:1 RFIC 1 RF Power combiner 4:1 4:1 Buffer Amp RFIC 2 RF Power combiner 4: 1 4: 1

11 Combining the whole tile

12 The block diagram ¼Tile Tile LNA HPF BFC (4:1) 4:1 AMP TTD 4:1 TTD BIAS TEE CABLE CABLE BIAS TEE AMP 4:1 CABLE RCU

13 Antenna concepts

14 Baseline design of the radiators Design Vivaldi with a stripline feed configuration Similar design to THEA safe approach

15 Verification of Simulation software

16 8 7 Simulated performance for Vivaldi with Stripline feed VSWR vs. Frequency φ = 0 & θ = 0 φ = 0 & θ = 30 Using PB - FDTD software 6 5 VSWR Frequency (GHz) x 10 9

17 Migration to Low cost and Dual polarisation Single sided Vivaldis and a microstrip feed Simple construction and low cost

18 Photographs for the Dual Polarisation

19 8 7 Simulated performance for Vivaldi with Microstripline feed VSWR vs. Frequency φ = 0 & θ = 0 φ = 0 & θ = 30 Using PB - FDTD software 6 5 VSWR Frequency (GHz) x 10 9

20 Aluminium plate antenna + 1mm solid aluminium plate + Rogers Substrate + connector + Substrate glued to Vivaldi + Connector glued to Vivaldi + Conductive Glue

21 Beam former chip development

22 RF Beam former chip architecture

23 Layout of the RF BF chip (ASTRON) Digital Controls Output amplifier LNA Polyphase Filter Buffer amplifiers Pads for probing Switches for combining

24 Beamformer Chip Digital Control: OK First stage amplifier: Low frequency OK slight oscillation problems. Polyphase network: OK Second stage amplifier: See first stage Levelshifter: OK Passgates: OK Output buffer: See first stage

25 Beamformer chip First run at IHP Verified functionality of modular blocks with testsetup Packaging of first chip in progress

26 Input 1 Input 2 3 bits > 3 db 3 bits > 3 db 3 bits > 3 db 3 bits > 3 db Beamformer chip (OPAR) Beam 1 3 bits bits bits bits 360 Combiner Output 1 Input Beam 1 Beam 2 LNA 3 bits > 3 db 3 bits > 3 db 3 bits bits Combiner Combiner Functional diagram for one input Output 1 Output 2 Input 3 Input 4 LNAS 3 bits > 3 db 3 bits > 3 db 3 bits > 3 db 3 bits > 3 db Beam 2 3 bits bits bits bits 360 Combiner Functional diagram of the chip Output 2 Silicon substrate Technology SiGe BiCMOS 0.25 µm Philips foundry: QUBIC4G Library 4 inputs and 2 outputs Phase control: bits Gain control: > 3 db 3 bits Digital serial control interface on the chip 50 ohms input and output impedance matching Operating frequency band: [ GHz]

27 Beamformer Layout Input 2 Input 1 Digital control Output mm Output 2 Current consumption Input ma 2.8 mm Input 3 Digital control Power supply 5 V Input 1 Power consumption BeamFormer 1.75 W Single-ended Input 2 Chip Input 3 Input 4 Isolated beam 1 and 2 Output 1 Output 2

28 Actual BF chip from OPAR Received mid-august: 52 packaged devices a few naked dies Test being carried out now

29 Preliminary Cost estimate from Philips For 7500 pieces 6 / device (electrically tested and packaged) includes dies manufacturing, packaging (LQFP48), electrical testing on wafer and in-package and fixed development cost of tools for electrical testing If we add fixed cost for the development of a full solution for RF testing on wafer and in-package: cost of a fully RF tested device: 20 Fixed costs not to be duplicated if more devices needed later on

30 Tile proto 1 impression

31 Closer look at the tile

32 First tile hardware

33 First Assembled Channel

34 Antenna mounted on quadrant board

35 Actual tile

36 Embrace siting at WSRT Embrace 300 M 2

37 Power and Data WSRT

38 WSRT

39 Another view of site

40 WATS test site

41 Nançay ay Site layout for EMBRACE

42 Concepts for the test sites

43 Concept 2

44 Station Concept 3

45 - Milestones Completion of system requirements: T0 + 6mo DONE Design review of first tile: T0 + 8mo DONE Delivery of first manufactured tile: T0 + 12mo ~DONE Next Deliverable: Completion of 10 tiles: T0 + 20mo -

46 Thank You

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