LMC555 CMOS LMC CMOS. 8-Pin SOIC, MSOP, and MDIP Packages. 8-Bump micro SMD. Top View (Bump side down) ds LMC555 CMOS LMC555. 3MHz 1.

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1 CMOS 555 CMOS (SOIC MSOP MDIP) micro SMD (8 micro SMD) LM LMCMOS TM CMOS ds V 1mW 3MHz 1.5V Converted to nat2000 DTD added title to the 2 avos on the first page Edited for 2001 Databook fixed page 1 and 2 fixed block and connection diagrams and ordering information fixed elec.table V TTL CMOS 10mA 50mA 8 MSOP 8 micro SMD CMOS 8-Pin SOIC, MSOP, and MDIP Packages 8-Bump micro SMD Top View Top View (Bump side down) LMCMOS TM National Semiconductor Corporation DS JP 1

2 Package Temperature Range Package Marking Transport Media NSC Drawing 8-LeadSmall Outline (SO) 8-Lead Mini Small Outline (MSOP) 8-Lead Molded Dip (MDIP) Industrial CM CM Rails CMX CM 2.5k Units Tape and Reel CMM ZC5 1k Units Tape and Reel CMMX ZC5 3.5k Units Tape and Reel CN CN Rails M08A MUA08A 8-Bump micro SMD CBP F1 250 Units Tape and Reel BPA08EFB CBPX F1 3k Units Tape and Reel micro SMD Demo Board CBPEVAL N/A N/A N/A N08E 2

3 (Note 2 3) V 15V V TRIG V RES V CTRL V THRESH 0.3V V S 0.3V V O V DIS I O I DIS MDIP (10 ) SOIC MSOP (60 ) (15 ) 15V 100 ma (Note 2 3) ( JA ) (Note 2) SO /W MSOP /W MDIP /W 8 micro SMD 220 /W 25 C MDIP mW SO-8 740mW MSOP-8 555mW 8 micro SMD 568mW Note: AN-450 (Note 1 2) T 25 RESET V S Symbol Parameter Conditions Min Typ Max Units (Limits) I S Supply Current V S 1.5V V S 5V V S 12V V CTRL Control Voltage V S 1.5V V S 5V V S 12V V DIS Discharge Saturation Voltage V S 1.5V, I DIS 1 ma V S 5V, I DIS 10 ma V OL Output Voltage (Low) V S 1.5V, I O 1 ma V S 5V, I O 8 ma V S 12V, I O 50 ma V OH Output Voltage (High) V TRIG Trigger Voltage V S 1.5V V S 12V V S 1.5V, I O 0.25 ma V S 5V, I O 2 ma V S 12V, I O 10 ma I TRIG Trigger Current V S 5V 10 pa V RES Reset Voltage V S 1.5V (Note 4) V S 12V I RES Reset Current V S 5V 10 pa I THRESH Threshold Current V S 5V 10 pa I DIS Discharge Leakage V S 12V 100 na t Timing Accuracy SW 2, 4 Closed V S 1.5V V S 5V V S 12V t/ V S Timing Shift with Supply V S 5V 1V 0.3 /V t/ T Timing Shift with Temperature V S 5V 40 T ppm/ f A Astable Frequency SW 1, 3 Closed, V S 12V khz f MAX Maximum Frequency Max. Freq. Test Circuit, V S 5V 3.0 MHz t R, t F Output Rise and Fall Times Max. Freq. Test Circuit V S 5V, C L 10 pf 15 ns A V mv V V V V ms 3

4 (Note 1 2) ( ) T 25 RESET V S Symbol Parameter Conditions Min Typ Max Units (Limits) t PD Trigger Propagation Delay V S 5V, Measure Delay from Trigger to Output 100 ns Note 1: Note 2: Note 3: Note 4: Note 5: GND IC IC AC DC (Typical) AN-450 micro-smd AN-1112 RESET 20 V S 2.0V Table 1 Test Circuit (Note 5) Maximum Frequency Test Circuit (Note 5) TABLE 5. Package Pinout Names vs. Pin Function Pin Function Package Pin numbers 8-Pin SO,MSOP, and MDIP 8-Bump micro SMD GND 1 A3 Trigger 2 B3 Output 3 C3 Reset 4 C2 Control Voltage 5 C1 Threshold 6 B1 Discharge 7 A1 V 8 A2 4

5 (Figure 1) (Trigger) 1/3V S V + Figure 3 RC Note: FIGURE 1. Monostable (One-Shot) t H 1.1R A C 2/3V S Figure 2 FIGURE 3. Time Delay Figure 4 (Trigger Threshold ) R A R B R B 2 V CC 5V TIME 0.1 ms/div. R A 9.1k C 0.01 F Top Trace: Input 5V/Div. Middle Trace: Output 5V/Div. Bottom Trace: Capacitor Voltage 2V/Div. FIGURE 2. Monostable Waveforms (Threshold) t H 20ns 400ns 10 s FIGURE 4. Astable (Variable Duty Cycle Oscillator) 1/3V S 2/3V S Figure 5 5

6 ( ) V CC 5V TIME 20 s/div. R A 3.9k R B 9k C 0.01 F FIGURE 5. Astable Waveforms ( ) t 1 Ln2 (R A R B )C ( ) t 2 Ln2 (R B )C T t 1 t 2 Ln2 (R A R B )C Top Trace: Output 5V/Div. Bottom Trace: Capacitor Voltage 1V/Div. V CC 5V TIME 20 s/div. R A 9.1k C 0.01 F FIGURE 7. Frequency Divider Waveforms Top Trace: Input 4V/Div. Middle Trace: Output 2V/Div. Bottom Trace: Capacitor 2V/Div. (Control) Figure 8 Figure 9 Figure 6 RC FIGURE 8. Pulse Width Modulator FIGURE 6. Free Running Frequency Figure 1 Figure 7 1/3 V CC 5V TIME 0.2 ms/div. R A 9.1k C 0.01 F FIGURE 9. Pulse Width Modulator Waveforms Top Trace: Modulation 1V/Div. Middle Trace: Output 2V/Div. Bottom Trace: Capacitor 2V/Div. Figure

7 ( ) Figure f 1/(1.4 R C C) FIGURE 10. Pulse Position Modulator FIGURE Duty Cycle Oscillator micro SMD Marking Orientation Top View V CC 5V TIME 0.1 ms/div. R A 3.9 k R B 3 k C 0.01 F Top Trace: Modulation Input 1V/Div. Bottom Trace: Output Voltage 2V/Div. FIGURE 11. Pulse Position Modulator Waveforms 7

8 inches (millimeters) Molded Small Outline (SO) Package (M) NS Package Number M08A 8-Lead (0.118 Wide) Molded Mini Small Outline Package NS Package Number MUA08A 8

9 inches (millimeters) ( ) Molded Dual-in-line Package (N) NS Package Number N08E 9

10 CMOS millimeters ( ) Sn/37 Pb EUTECTIC 3. NSMD (Non-Solder Mask Defined) 4. A1 ( ) 5. XXX X1 X2 X3 6. JEDEC MO-211 VARIATION BC micro SMD Package NS Package Number BPA08EFB X X X (a) (b) TEL.(03) /

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