A Highly Efficient Cascaded Multilevel Inverter Configuration for PV Systems

Transcription

1 A Highly Efficient Cascaded Multilevel Inverter Configuration for PV Systems PAGOTI PRAMOD KUMAR, Dr. K V S R Murthy, M.Tech, Professor & Head (R&D), ADITYA ENGINEERING COLLEGE, Kakinada. Abstract This Thesis presents a highly efficient and reliable cascaded multilevel inverter (CMLI) configuration for the minimization of the leakage current. Apart from a reduced switch count, the implemented scheme has additional features of low switching and conduction losses. The implemented topology with the given pulse width modulation (PWM) technique reduces the high-frequency voltage transitions in the terminal and common-mode voltages. Avoiding high-frequency voltage transitions achieves the minimization of the leakage current and reduction in the size of electromagnetic interference filters. Furthermore, the extension of the implemented CMLI along with the PWM technique for m + levels is also presented, where m represents the number of photovoltaic (PV) sources. The implemented PWM technique requires only a single carrier wave for all m + levels of operation. The total harmonic distortion of the grid current for the implemented CMLI meets the requirements of IEEE 547 standard. A comparison of the CMLI with the existing PV multilevel inverter topologies is also presented in this work. Complete details of the analysis of PV terminal and common-mode voltages of the simulated CMLI using switching function concept are presented in the Thesis. INTRODUCTION Transformer less multilevel inverter (MLI) topologies are highly efficient, and have low switch count, low weight, and reduced size. Removal of the transformer eliminates the galvanic isolation between the photovoltaic (PV) array and the output load. Removal of galvanic isolation increases the leakage current safety is reduced in Photovoltaic systems. It has led to the development of various safety standards for the PV systems, which restrict the value or magnitude of leakage current flow in the PV system. Apart from leakage current minimization, there is a demand for quality power output to be fed into the grid from the PV system. This requirement has led to the use of MLI in the transformer less PV systems. In the recent past, many configurations or topologies of MLIs are proposed for reducing of leakage current. These topologies implement two methods for minimization of the leakage current. First one is based on maintaining the common-mode Page No:646

2 voltage (CMV) constant, and the other one is based on the minimization of the highfrequency transitions. There is a requirement for a generalized transformer less PV system, with fewer switches to get high efficiency at lesser cost. The PV MLI should have reduced switching and conduction losses with a lower number of switches during the zero volt-age state. The extension to the higher number of levels should be possible. This Thesis implements one such solution for reducing the leakage current in transformer less MLIs connected to PV systems. The PWM technique for the implemented MLI is also discussed in the Thesis. The analysis of PV terminal and CMVs are presented. This analysis leads to the implementation of the PWM technique. PWM suppresses highfrequency voltage transitions in the terminal voltage and CMV. Salient features of the simulated cascaded MLI (CMLI) are as follows.. The topology uses 8 switches for the generation of five levels of output voltage.. During the zero voltage state only one switch and one diode will conduct. 3. In the implemented topology, four switches are operated at a low switching frequency. Hence, the switching losses are less. 4. The dead band in the PWM techniques does not have any affect on CMV. 5. The implemented inverter can be cascaded to achieve more than five levels. Rest of the Thesis is organized into five chapters. Chapter presents the literature survey. Chapter 3 describes the working principle and the operation for the five-level gridconnected CMLI along with the generalized structure. The details of the PWM technique employed with its generalization for m + levels are also explained. Chapter 4 gives the details of the maximum power point tracking (MPPT) algorithm which can be applied to the five-level CMLI. This is followed by the analysis of terminal and CMVs for the CMLI. Chapter 5 presents the simulation results of the five-level gridconnected CMLI. Chapter 6 presents the conclusions from the Thesis. OPERATION OF THE CASCADED FIVE-LEVEL MLI The schematic circuit diagram of the implemented five-level CMLI for the PV system is shown in Fig.. The given configuration consists of two converters (Conv- and Conv- ). Conv- is a half-bridge inverter comprising two switches Sx and Sx. The Conv- comprises of a highly efficient and reliable inverter configuration with six switches (Sx3 Sx8). Among the six switches, four switches (Sx3 Sx6) in Conv- constitute an H-bridge circuit. The remaining two switches (Sx7 and Sx8) in Conv- are bidirectional switches. The switches in the Conv- are used to generate the voltage levels of VPV and VP V /. When switch Sx is Page No:647

3 turned ON, the voltage VPV is applied at the terminal n with respect to the terminal z. Similarly, the terminal n attains the voltage VP V / when switch Sx is turned ON. The switches Sx and Sx are complementary in nature. The generated voltage levels at the terminal n of Conv- are given as an input to the Conv-. The Conv- generates the positive, negative, and zero levels of corresponding input voltage (voltage between the filter is used as a damping resistor. The resistance Rac refers to the grid side resistance and the resistance Rg indicates resistance in the ground path. The variable vac refers to instantaneous grid voltage. The variables Rp and Cp refer to the parasitic resistance and capacitance in the PV system, respectively, shown with dotted lines in Fig.. The parasitic capacitance in the PV system forms a resonant circuit with the filter inductances. The variables io, ic, and iac denote the output current of the five-level CMLI, current flowing through shunt branch of the filter, and the current flowing into the sx S x S x 3 S x 4 S x 5 S x 6 S x 7 S x 8 v u v V P V V P V / V P V / V P V five-level grid-connected CMLI with PV and parasitic elements. the terminals n and z) across the load. The bidirectional switches Sx7 and Sx8 provide the free-wheeling path during zero voltage state. The output of the five-level CMLI is connected to the grid through an LCL filter as shown in Fig. ]. It consists of inverter side inductance Li, capacitance Cf, and grid side inductance Lac. The resistance Rd in the shunt branch of grid, respectively. The current ilea k indicates the leakage current flowing from the PV array into the ground through parasitic capacitance. SWITCHING STATES WITH THEIR RESPECTIVE OUTPUT VOLTAGE The implemented MLI topology contains four pairs of complementary switches (Sx, Sx), (Sx3, Sx4), (Sx5, Sx6), and (Sx7, Sx8) in the implemented configuration. However, to minimize the leakage current, the complementary switching is employed only for the two pairs of switches (Sx, Sx) and (Sx7, Sx8). Avoiding complementary action for the other pairs of switches helps in isolating the PV and the grid source during the zero voltage state 3 Page No:648

4 Fig. shows the operation of the inverter in all its switching states. The inverter output voltage vuv at different voltage levels with the corresponding switching states of all the switches is shown in Table I. The inverter output voltage vu v attains the voltage levels +VP V or VP V when switch Sx is turned ON along with other inverter switches (Sx3, Sx6 ) or (Sx4, Sx5 ), respectively, as shown in Fig. (a) and (e). Similarly, the voltage levels +VP V / or VP V / are obtained at vuv when switch Sx is turned ON with the same switching combinations as shown in Fig. (b) and (d). The most important feature to be noticed during zero voltage state or free-wheeling stage is the isolation or disconnection between PV source and the grid. The isolation between the PV source and the grid can be achieved by turning OFF all the switches of the H-bridge inverter as shown in Fig. (c). switching cycle. This action helps in minimizing the leakage current flowing through the parasitic capacitance. As there is no direct connection between the two sources, the PV terminal points (nodes x, y, and z) float and have undefined volt-ages. The float or undefined value restricts the terminal voltages from becoming zero. Thus, high-frequency voltage transitions at the PV terminals are avoided. In other words, the possibility of the flow of leakage current can be minimized. Also, in the other intermediate states such as switching between VP V/ to VP V or vice-versa, again the same principle can be used. The above action further helps in the minimization of the leak-age current in the PV system. The PWM technique for the implemented five-level CMLI is broadly discussed in Section III. The expressions for the pole voltages vuz and vvz is given, respectively, as + (S 3 +S 4) () u uz = ( S S S S 3 (S 3 +S 4 )+(S +S ) ) V PV Single-phase five-level cascaded MLI for output voltage levels(a) +VP V, (b) + VP V /, (c) 0, (d) VP V /, and (e) VP V The turn-off state of four switches in H-bridge during the zero voltage state results in the isolation of PV source from the grid. The bidirectional switches Sx7 and Sx8 provide a free-wheeling path for the inductor current during the turn-off period of a u VZ = ( S S S S 3 + )V (S 5 +S 6) (S 5 +S 6 )+(S +S ) PV () Where Sa (a =,, 3,...) is the switching state of switch Sxa whose value can be either (stands for turn-on) or 0 (stands for turn-off). Fig.3 shows the switching pattern of all the switches for the 4 Page No:649

5 corresponding inverter output voltage vuv. The switches Sx and Sx in the half-bridge are operated at low switching frequency. In order to eliminate the high switching frequency operation, the switch Sx is kept turned ON in the zero state during voltage transition between the levels 0 to VPV/. Similarly, the switch Sx is kept turned ON, during voltage transition between levels 0 to VPV. The inverter switch pair (Sx3, Sx6 ) is operated with a high switching frequency during positive half-cycle, and it remains at the turn-off state during the negative half-cycle of the inverter output voltage vu v. Gate pulses for the switches corresponding to inverter output voltage.a similar operation is applicable to the other inverter switch pair (Sx4, Sx5), which is operated with higher switching frequency during the negative half-cycle. The switches Sx7 and Sx8 are turned ON during positive and negative half-cycles of the output voltage vuv, respectively. The removal of complementary action from the pair of switches (Sx3, Sx4) and (Sx5, Sx6) facilitates complete turn-off of the switches during each half-cycle of the output voltage vuv. Thus, the implemented system has the advantage of reduced switching losses, realizingto a highly efficient and reliable inverter configuration which may result in higher efficiency The generalized topology for m + levels can also be obtained for the implemented five-level CMLI. The number of PV sources in the CMLI is denoted by the term m. The value of m is always an integral multiple of (i.e., m =, 4,..) the extended version of the implemented CMLI for m + levels is presented in Fig.4. The generalized topology is obtained by cascading the basic units consisting of half-bridge and H-bridge. The bidirectional switches are connected in between the output terminals for the free-wheeling period. The implemented generalized m + level MLI is also compared with the halfbridge and full-bridge modular multilevel converter. The half-bridge modular multilevel converter requires less number of switches when compared to the implemented generalized m + level MLI. However, it is difficult to reduce or minimize the flow of leakage current in the half-bridge modular multilevel converter. Also, the number of electrolytic capacitors used at the input side of the half-bridge modular multilevel converter is high compared to the implemented generalized m+ level MLI. The implemented MLI has a lesser device count when compared to the fullbridge modular multilevel converter. However, both can minimize the leakage current flowing through the PV system. 5 Page No:650

6 desired modification, the output voltage includes the zero volt-age state (i.e., free-wheeling state) in all its switching periods. The expression for modified reference waveform v ref modified is given as u ref modified = { u mod u mod (3) for 0 u mod < m a for m a from V PV to 0 u mod < m a from V PV to 0 } Fig.4. Generalized m + level MLI topology derived from the pro-posed five-level CMLI. PWM strategy along with generalized strategy for minimization of the leakage current The operation of the implemented PWM technique is explained by considering the given five-level CMLI. The high-frequency transitions in the terminal voltages vxg and vyg of the fivelevel CMLI are minimized using the implemented PWM technique. The suggested action can be achieved by switching from VP V to 0 states or viceversa instead of the switching from VP V to VP V / states or vice-versa. Additionally, during the zero voltage state or free-wheeling period of the switching cycle, the PV array is isolated from the grid. The isolation of the PV array and the grid during zero voltage state is similar to the inverter configuration reported. The magnitude of reference wave vmod is lowered to 50% of its original value whenever the switching is toggled amongst the levels VP V and 0. The above action is mainly done to accommodate the value of PV voltage VP V. The modification in the value of v mod is done whenever the instantaneous magnitude of modulating wave v mod exceeds the value of ma /, where ma refers to the modulation index. By incorporating the The output voltage of the implemented PWM technique for the five-level CMLI is shown in Fig.5. In Fig. 5, the modified reference wave is compared with the triangular carrier wave. During the positive half-cycle of voltage v ac, whenever the phase angle ωt lies in range 0 30 and the instantaneous magnitude of v ref modified exceeds the carrier wave, then vu v attains the volt-age level of VP V / otherwise, it is switched to the zero voltage state. Similarly, when ωt lies in the range 30 50, the inverter output voltage v uv attains the voltage level of VP V whenever the instantaneous magnitude v ref modified exceeds the carrier wave or attains zero value otherwise. In the same positive half-cycle, for the remaining range of ωt (i.e., between 50 and 80 ), vu v attains the voltage levels VP V / if the instantaneous magnitude of v ref modified is greater than the carrier wave. A similar sequence is adopted during the negative half-cycle of voltage vac. Thus, in the complete cycle if the magnitude of v ref modified is less than the carrier wave, then vu v attains zero voltage level. 6 Page No:65

7 Waveform of output voltage vu v for the implemented PWM technique. For the implementation of the implemented PWM to a m + level inverter, the waveform of generalized modified reference wave v ref modified gen is shown in Fig. 6. The term m refers to the number of PV sources used. Whenever the instantaneous voltages (VP V and VP V for the PV sources PV and PV, respectively) and ) the currents (IP V and IP V for the PV sources PV and PV, respectively) are sensed and then given to their respective MPPT algorithms. The MPPT algorithms then use the sensed values of the PV voltages and currents for the calculation of the individual values of the modulation indices ma and ma for the two PV sources PV and PV, respectively. The outputs of two MPPT algorithms are then utilized for the calculation of overall modulation index ma. The expression for ma is given as Fig.6. Waveform of generalised modified reference wave of v ref modified gen Absolue magnitude of u mod exceeds the value j(m a /m), the magnitude of u ref.modified gen becomes k( u mod / m) where j=,,,,,m-. The expression for u ref.modified gen is given as { u ref.modified gen = u mod for 0 u mod < m a u mod u mod m m for m a u m mod < m a m.. for (m )m a m (4) from from V PV m to 0 V PV m to 0 u mod < m a from V PV to 0 } INTEGRATION OF MPPT FOR THE FIVE-LEVEL CMLI The well-known perturb and observe algorithm is employed for the two PV sources (considering five-level operation) individually to track maximum power point (MPP). Thus, each MPPT algorithm tracks the MPP for respective PV sources. To track the MPP, the required information of ) the average values of the two PV source m a V PV V PV +V PV + m a V PV V PV +V PV The calculated modulation index ma is then used by the PWM strategy as described in the above-mentioned section to generate the PWM pulses for the implemented five-level CMLI. 4. Analytical expressions of PV terminal voltage and common mode voltage for the cascaded five-level inverter The analysis of the leakage current can be carried out from the expression of be derived from the switching function analysis. From Fig., using the superposition theorem, the PV terminal voltages vxg and vyg are expressed as u xg = s u xg + s u xg u yg = s u yg + s u yg The terms of and u yg are the voltages at terminals x and y respectively. When switch s x is turned 7 Page No:65

8 on. Similarly u xg and u yg are the voltages at terminals x and y, respectively. When switch s x is turned on The expression for terminal voltages at u zg when switch s x is turned on is given as u zg = u xg V PV Similarly, the expression for voltage vzg when switch s x is turned on is given as u zg = u xg V PV With the use of the switching function analysis, the voltages u ug and u vg (from fig and ) expressed in terms of u xg and u zg are shown, respectively, as u ug = s s 3 u xg + s 4 u zg u vg = s s 5 u xg + s 6 u Zg u vg = L i di 0 dt + L ac di ac + v dt ac + R ac i ac R g i leak Now, with the addition of (4) and (5), and by ignoring the voltage drop in resistances Rg and Ra c / with assumptions of iac = iac and io = io, [] gives (6) u ug + u vg = u ac Substituting the values of vu g and vv g from (0) and () into (6) and simplifying those using (8) gives the expression for the terminal voltage vxg as u xg = u ac+v PV (S 4 +S 6 ) (S S 3 +S S 5 +S 4 +S 6 ) (7) Now, the other terminal voltage vyg (when switch s x is on) can be calculated by subtracting vxg and VP V /. Similarly, substituting () and (3) into (6) and simplifying for terminal voltage vyg using (9) results in Similarly, the expression for voltage v ug when switch u vg expressed in terms of u yg and u zg using switching functions are shown, respectively as (8) u yg = u ac+ V PV (S 4+S 6 ) (S S 3 +S S 5 +S 4 +S 6 ) u ug = s s 3 u yg + s 4 u zg u vg = s s 5 u yg + s 6 u Zg Now expressing the voltages vu g and vv g in terms of the grid voltage vac, the voltage drop in filter inductors (Li and La c ) and resistances (Rac and Rg ) can be given by di 0 + L ac dt u ug = L i R g i leak (4) di ac + v dt ac + R ac i ac 8 Page No:653

9 VALUES OF COMMON-MODE VOLTAGE AND POLE VOLTAGES FOR CORRESPONDING OUTPUT VOLTAGE u xg = u ac S W + V PV S W + u ac S W3 + V PV S V PV W4 S v u v v u z v v z v c m + V P V V P V 0 V P V / + V P V / V P V / 0 V P V / 4 0 Undefined Undefined Undefined V P V / 0 V P V / V P V / 4 V P V 0 V P V V P V / The other terminal voltage vxg can be calculated by adding vyg and VPV /. Now by using (6) and (7), the complete expression for terminal voltages vxg and vyg is given, respectively, as u xg = u ac S W + V PV S W + u ac S W3 + V PV S V PV W4 S (9) S S W3 = (S S 3 + S S 5 + S 4 + S 6 ) S (S 4 + S 6 ) S W4 = (S S 3 + S S 5 + S 4 + S 6 ) Substituting the values S 3 =0, S 4 =0, S 5 =0, and S 6 =0 in the terminal voltage state results in undefined value (0/0) in the terminal voltages u xg, u yg and u zg. the undefined value (0/0) during a zero voltage state is mainly because of isolating the PV source and grid. The isolation of PV source and grid can also be observed in fig.(c). The CMV u uz and u vz given in () and (), respectively. The expression for u cm is The terms S W, S w, S W3 and S w4 in (9) and (0) are given by S W = S W = S (S S 3 + S S 5 + S 4 + S 6 ) S (S 4 + S 6 ) (S S 3 + S S 5 + S 4 + S 6 ) Table II gives the values of pole voltages (u uz, u vz ) and CMV v cm at different levels in the output voltageu uv. During turn off period in a switching cycle in H-bridge are in a cut-off state so that the switching states S 3, S 4, S 5 and S 6 are equal to zero value. Substituting the corresponding values of S 3, S 4, S 5 and S 6 results in undefined value (i.e. u cm = 0/0) during the zero voltage state. The CMV attains the value V PV / for both positive and negative levels of output u cm = ((S + 0.5S )(S 3 + S 5 ) + ( ) ( )) V PV (S 5 +S 6 ) (S +S ) + (S 3 +S 4 ) () 9 Page No:654

10 PARAMETERS CONSIDERED FOR THE SIMULATION OF IMPLEMENTD FIVE- LEVEL CMLI Parameter P V dc f sw v ac f ac Value.5Kw 400 V 5kHz 0V 50 Hz Parameter L ac R ac Rg Li Cf Value 4 mh 0.0 Ω 0. Ω 4 mh 0. µf Parameter R d C p R p Value 50 mω 00nf Ω Voltage V PV and attains the valuev PV / 4 for both positive and negative levels of output voltage V PV / The expressious for terminals and CMVs can be verified with MATLAB software using Simulink block-set. The parameters Vpv=400v, switching frequency of carrier wave fsw=khz vac = 0 V (rms), and the grid frequency fg = 50 Hz are considered for the simulation. The carrier wave frequency is restricted to khz. This is done to demonstrate the undefined states clearly. Fig. 7 shows the waveforms of terminal voltages vxg, vyg, vzg, and CMV vcm. The discontinuity in the waveforms occurs when the PV source and grid are isolated. The isolation of grid and PV array results in an undefined value in the terminal and CMVs (discontinuity in the waveform). Since the value of the terminal and CMVs is undefined during the zero voltage state, they can be assumed to be restricted to the previous value thus transitions in the voltage waveform can be minimized. In other words, it results in minimizing the high-frequency voltage transitions in the terminal and CMVs. Minimization or reduction of highfrequency voltage transitions in the terminal voltage further helps in reducing the leakage current in the PV system The PV array parasitic capacitance offer a high impedance for the lowfrequency transitions in the terminal voltage. Thus, the magnitude of leakage current flowing through the parasitic capacitance is less. In other words, the implemented PWM technique minimizes the leakage current by reducing the highfrequency transitions in the terminal and CMVs. Fig.7. Analytical results of the implemented five-level CMLI showing the waveforms of (a) terminal voltage vxg; (b) terminal voltage vyg; (c) terminal voltage vzg; and (d) common-mode voltage vcm. SIMULATION RESULTS To support the switching function analysis the proposed five-level CMLI is simulated using POWERSIM blocks in the MATLAB software The PWM technique explained in Section III is used for the proposed five- 0 Page No:655

11 level CMLI configuration. Table III gives the value of various parameters used for simulating the proposed five-level CMLI. The proposed five-level CMLI needs to generate a voltage to feed the required amount of active power P into the grid. By substituting the parameters from Table III in respectively. The simulation waveforms of the proposed five-level CMLI using the proposed PWM technique are shown in Fig. 8. The Fig. 8 shows the output voltage of the five-level CMLI. The presence of the zero voltage state in all the voltage transitions of vuv can be clearly noticed from the plot simulation result for grid current The proposed PWM technique reduces the value of leakage current This is because of the low-frequency volt age transitions in the terminal voltage vxg.the spikes in the leakage current are observed when there is a sudden voltage transition in the terminal voltage.the fig 0 shows The waveform of terminal voltages vxg the observation made from these subplots is the absence of highfrequency voltage transitions simulation result for output voltage The grid current iac is shown in fig 9. The of grid current iac is around meets the requirement the crucial observation made from these subplots is the absence of highfrequency voltage transitions. Also, these waveforms match with the result obtained using the switching function analysis Fig 0: simulation result for terminal voltage Another simulation is carried out with the proposed configuration to demonstrate the MPPT operation. The proposed five-level CMLI is operated using two MPPT algorithms to extract the maximum power from the individual PV arrays Fig. shows the simulation results of MPPT performance for the proposed five-level CMLI show the waveforms of PV voltages VPV Page No:656

12 output power renewable distributed systems, IEEE Trans. Ind. Electron., vol. 60, no. 3, pp , Mar. 03. power (watts) Time (sec) simulation result for output power CONCLUSION In this Thesis, an improved five-level CMLI with low switch count for the minimization of leakage current in a transformer-less PV system was implemented. The implemented CMLI minimized the leakage current by eliminating the high-frequency transitions in the terminal and CMVs. The implemented topology also reduced conduction and switching losses which made it possible to operate the CMLI at high switching frequency. Furthermore, the solution for generalized m + levels CMLI was also presented in the Thesis. The given PWM technique required only one carrier wave for the generation of m + levels. The operation, analysis of terminal, and CMVs for the CMLI were also presented in the Thesis. The simulation results agree with results of the analysis carried out in this Thesis. The MPPT algorithm was also integrated with the implemented fivelevel CMLI to extract the maximum power from the PV panels. The implemented CMLI was also compared with the other existing MLI topologies. REFERENCES [] G. Buticchi, E. Lorenzani, and G. Franceschini, A five-level singlephase grid-connected converter for [] N. A. Rahim and J. Selvaraj, Multistring five-level inverter with novel PWM control scheme for PV application, IEEE Trans. Ind. Electron., vol. 57, no. 6, pp. 3, Jun. 00. [3] M. Cavalcanti, K. De Oliveira, A. M. de Farias, F. Neves, G. Azevedo, and F. Camboim, Modulation techniques to eliminate leakage currents in transformerless three-phase photovoltaic systems, IEEE Trans. Ind. Electron., vol. 57, no. 4, pp , Apr. 00. [4] L. Zhang, K. Sun, L. Feng, H. Wu, and Y. Xing, A family of neutral point clamped full-bridge topologies for Y. Tang, W. Yao, P.C. Loh, and F. Blaabjerg, Highly reliable transformerless photovoltaic inverters with leakage current and pulsating power elimination, IEEE Trans. Ind. Electron., vol. 63, no., pp , Feb. 06. [5] W. Li, Y. Gu, H. Luo, W. Cui, X. He, and C. Xia, Topology review and derivation methodology of singlephase transformerless photovoltaic inverters for leakage current suppression, IEEE Trans. Ind. Electron., vol. 6, no. 7, pp , Jul. 05. [6] J. Ji, W. Wu, Y. He, Z. Lin, F. Blaabjerg, and H. S. H. Chung, A simple differential mode EMI suppressor for the LLCL-filter-based single-phase grid-tied transformerless inverter, IEEE Trans. Ind. Electron., vol. 6, no. 7, pp , Jul. 05. Page No:657

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