ADVANCED MODULATION TECHNIQUES FOR NEUTRAL- POINT CLAMPED THREE-LEVEL INVERTERS IN AUTOMOTIVE APPLICATIONS

Transcription

1 ADVANCED MODULAION ECHNIQUES FOR NEURAL- POIN CLAMPED HREE-LEVEL INVERERS IN AUOMOIVE APPLICAIONS NAZAK SOLEIMANPOUR A hesis In the Deprtment of Electricl nd Computer Engineering Presented in Prtil Fulfilment of the Requirements for the Degree of Msters of Applied Science (Electricl nd Computer Engineering) Concordi University Montrel, Queec, Cnd NAZAK SOLEIMANPOUR, 214

2 his is to certify tht the thesis prepred CONCORDIA UNIVERSIY SCHOOL OF GRADUAE SUDIES By: Entitled: Nzk Soleimnpour Advnced Modultion echniques for Neutrl-Point Clmped hree-level Inverters in Automotive Applictions And sumitted in prtil fulfilment of the requirements for the degree of Msters of Applied Science Complies with the regultions of this University nd meets the ccepted stndrds with respect to originlity nd qulity Signed y the finl exmining committee: Chir Dr. M. Z. Kir Exminer, Externl Dr. Z. Zhu (BCEE) Exminer Dr. V. Rmchndrn Supervisor Dr. L. A. Lopes Approved y: Dr. W. E. Lynch, Chir Deprtment of Electricl nd Computer Engineering 2 Dr. Amir Asif Den, Fculty of Engineering nd Computer Science

3 ABSRAC Advnced Modultion echniques for Neutrl-Point Clmped hree-level Inverters in Automotive Applictions Nzk Soleimnpour he Neutrl-Point Clmped (NPC) three-level inverter is promising multilevel topology in the ppliction of Electric Vehicle (EV). However, the growing requirements y the EV initite the therml unlnce prolem for this inverter topology. he present thesis highlights the performnce of the NPC three-level inverter supplying Permnent Mgnet Synchronous Motor (PMSM) in the ppliction of EV. he PMSM is considered to operte in the region elow the se speed. In this condition, there is n unlnce of conduction power loss mong the semiconductors of the inverter. he project dels with the conduction power losses of the semiconductors in NPC three-level inverter controlled with specil Spce Vector Modultion (SVM) methods. In order to find n pproprite method for lncing the conduction power loss of devices, three SVM methods, Norml, O2 nd O3 re compred. By implementing these three techniques, primrily, the conduction duty cycle of the devices is clculted to demonstrte the durtion of conducting for ech device. Afterwrds, the conduction power loss of devices is computed in MALAB/Simulink. In ddition, the impct of two prmeters, modultion index nd power fctor, on conduction duty cycle nd conduction power loss is investigted. Furthermore, Comprison of the totl hrmonic distortion of the line-to-line current for different modultion indices is presented for ll three modultion techniques. According to the detiled comprisons of methods, O2 Spce Vector Modultion technique stnds out s etter cndidte for therml redistriution mong semiconductors. iii

4 ACKNOWLEDGEMEN Foremost, I would like to express my sincere grtitude to my supervisor Prof. Luiz A. C. Lopes for the continuous support of my Msters study nd reserch, for his ptience, motivtion, immense knowledge, thoughtful guidnce, criticl comments, nd correction of the thesis. I would like to thnk the memers of the committee, Prof. Rmchndrn nd Prof. Zhu for their excellent dvises nd detiled review of this thesis. I wnt to express my deep thnks to my friends t the Power Electronics nd Energy Reserch (PEER) group t the P. D. Ziogs Lortory especilly to Mr. Lesidi Msisi nd Mr. Ahijit Choudhury for their gret ssistnce nd motivtion towrds my work. I relly hd n dmirle time nd my experience t the l will lwys e rememered. Finlly, specil recognition goes out to my fmily, for their support, encourgement nd ptience during my pursuit of the mster. o my lovely prents, Mhmood nd Fri, who inspired me nd provided constnt encourgement during the entire process. I m lwys indeted to my eloved prents. o my rother, MohmmdAli, for his cre nd support throughout my studies. I thnk ll three of you nd love you nd your love nd cre will forever remin rooted in my hert. iv

5 Dedicted to My Beloved Prents, Mhmood & Fri & My lovely rother, MohmmdAli v

6 ABLE OF CONENS CHAPER1: INRODUCION O HESIS INRODUCION O PERMANEN MAGNE SYNCHRONOUS MOOR INRODUCION O POWER CONVERERS FOR ELECRIC VEHICLES GAING SIGNAL GENERAION POWER LOSSES IN HREE-LEVEL INVERER CONRIBUION OF HE HESIS HESIS OULINE CHAPER 2: MODEL OF HE PERMANEN MAGNE SYNCHRONOUS MOOR INRODUCION HE PMSM IN ROOR REFERENCE FRAME SINGLE PHASE EQUIVALEN CIRCUI OF PMSM INVERER VOLAGE AND ROOR CURREN NEURAL-POIN CLAMPED MULILEVEL INVERER DAA SHEE OF PERMANEN MAGNE SYCHRONOUS MACHINE ESIMAION OF POWER LOSSES CONCLUSION CHAPER 3: NEURAL-POIN CLAMPED (NPC) HREE-LEVEL INVERER WIH SPACE VECOR MODULAION (SVM) ECHNIQUE INRODUCION SPACE VECOR MODULAION (SVM) ECHNIQUE SPACE VECOR MODULAION (SVM) FOR HREE-LEVEL INVERER SECOR DEERMINAION RIANGLE DEERMINAION IN ONE SECOR CALCULAION OF SWICHING IMES SWICHING SAE DEERMINAION HREE SPACE VECOR MODULAION (SVM) MEHODS DUY CYCLE DEFINIION EFFEC OF POWER FACOR ON CURREN POLARIIES CONDUCION DUY CYCLE FOR NORMAL SPACE VECOR MODULAION (SVM) ECHNIQUE CONDUCION DUY CYCLE FOR O2 SPACE VECOR MODULAION (SVM) ECHNIQUE... 6 vi

7 CONDUCION DUY CYCLE FOR O3 SPACE VECOR MODULAION (SVM) ECHNIQUE CONCLUSION... 7 CHAPER 4: CONDUCION DUY CYCLE OF SEMICONDUCORS IN NEURAL-POIN CLAMPED (NPC) HREE-LEVEL INVERER INRODUCION ENABLED DUY CYCLE VERSUS CONDUCION DUY CYCLE FOR NORMAL SPACE VECOR MODULAION (SVM) MEHOD PLO ANALYSIS FOR OUER SWICH AND IS ANI- PARALLEL DIODE PLO ANALYSIS FOR INNER SWICH, IS ANI-PARALLEL DIODE AND CLAMPING DIODE PLO ANALYSIS FOR CLAMPING DIODES INFLUENCE OF LOAD ANGLE ON CONDUCION DUY CYCLE OF DEVICES CONDUCION DUY CYCLE FOR NORMAL SVM CONDUCION DUY CYCLE FOR O2 SVM CONDUCION DUY CYCLE FOR O3 SVM COMPARISON OF HE MEHODS INFLUENCE OF MODULAION INDEX ON CONDUCION DUY CYCLE CONDUCION DUY CYCLE FOR NORMAL SVM CONDUCION DUY CYCLE FOR O2 SVM CONDUCION DUY CYCLE FOR O3 SVM COMPARISON OF HE MEHODS CONCLUSION CHAPER 5: PERFORMANCE VERIFICAION BY SIMULAION INRODUCION COMPUAION OF CONDUCION LOSSES INFLUENCE OF LOAD ANGLE ON CONDUCION POWER LOSSES OF DEVICES CONDUCION POWER LOSS FOR NORMAL SVM CONDUCION POWER LOSS FOR O2 SVM CONDUCION POWER LOSS FOR O3 SVM INFLUENCE OF MODULAION INDEX ON CONDUCION POWER LOSS OF DEVICES CONDUCION POWER LOSS FOR NORMAL SVM CONDUCION POWER LOSS FOR O2 SVM vii

8 CONDUCION POWER LOSS FOR O3 SVM HD OF INVERER OUPU CURRENS FOR HREE MEHODS CONCLUSION CHAPER 6: CONCLUSION SUMMARY FUURE WORKS REFERENCES viii

9 LIS OF FIGURES Figure 1. 1: Digrm of converter nd PMSM... 2 Figure 1. 2: orque nd power vs. speed, PMSM... 3 Figure 1. 3: () wo-level inverter digrm, () output line voltge... 5 Figure 1. 4: NPC hree-level inverter... 8 Figure 1. 5: Line voltge of hree-level inverter with PWM... 9 Figure 1. 6: he SPWM modultion method... 1 Figure 1. 7: he Spce Vector Modultion digrm Figure 1. 8: herml model of switch, its nti-prllel diode nd clmping diode Figure 1. 9: Junction temperture of ech device versus speed Figure 2. 1: PMSM model in dq frme Figure 2. 2: Single phse digrm of PMSM Figure 2. 3: Phsor digrm of PMSM without field-wekening Figure 2. 4: orque nd power vs. speed for the PMSM Figure 2. 5: hree-level Neutrl-Point Clmped inverter Figure 2. 6: Single Phse Neutrl-Point Clmped hree-level inverter Figure 3. 1: Spce vector Digrm for three-level inverter Figure 3. 2: First Sector of the Hexgon Figure 3. 3: he length of the sectors Figure 3. 4: Switching Signls for ringle 1, Sector Figure 3. 5: Vectors Length in Sector Figure 3. 6: ringle 1 in Sector Figure 3. 7: Switching signl nd stte sequence in ringle 1, Sector 2 (Norml SVM) Figure 3. 8: Stte vectors in ringle 1, Sector Figure 3. 9: Stte vectors in ringle 1, Sector 2 relocted to Sector Figure 4. 1: Duty cycle of S1; Figure 4. 2: Duty cycle of S2; (): enled duty cycle of S2, (): conduction duty cycle of S2, (c): conduction duty cycle of D2, (d): conduction duty cycle of D Figure 4. 3: Duty cycle of D A5; (): enled duty cycle of D A5, (): conduction duty cycle of D A5, (c): conduction duty cycle of D A Figure 4. 4: Duty cycle of switches in phse A (Norml SVM); (): Conduction duty cycle of outer switch (S A1), (): Conduction duty cycle of inner switch (S A2) Figure 4. 5; Duty cycle of nti-prllel diodes in phse A (Norml SVM); (): Conduction duty cycle of outer diode (D A1), (): Conduction duty cycle of inner diode (D A2) Figure 4. 6: Conduction duty cycle of upper clmping diode (D A5) in phse A (Norml SVM) Figure 4. 7: Duty cycle of switches in phse A (O2 SVM); (): Conduction duty cycle of outer switch (S A1), (): Conduction duty cycle of inner switch (S A2) ix

10 Figure 4. 8: Duty cycle of nti-prllel diodes in phse A (O2 SVM); (): Conduction duty cycle of outer diode (D A1), (): Conduction duty cycle of inner diode (D A2) Figure 4. 9: Conduction duty cycle of clmping diode (D A5) in phse A (O2 SVM) Figure 4. 1: Duty cycle of switches in phse A (O3 SVM); (): Conduction duty cycle of outer switch (S A1), (): Conduction duty cycle of inner switch (S A2)... 9 Figure 4. 11: Duty cycle of nti-prllel diodes in phse A (O3 SVM); (): Conduction duty cycle of outer diode (D A1), (): Conduction duty cycle of inner diode (D A2) Figure 4. 12: Conduction duty cycle of clmping diode (D A5) in phse A (O3 SVM) Figure 4. 13: Duty cycle of switches in phse A (Norml SVM); (): Conduction duty cycle of outer switch (S A1), (): Conduction duty cycle of inner switch (S A2) Figure 4. 14: Duty cycle of nti-prllel diodes in phse A (Norml SVM); (): Conduction duty cycle of outer diode (D A1), (): Conduction duty cycle of inner diode (D A2) Figure 4. 15: Conduction duty cycle of clmping diode in phse A (Norml SVM) Figure 4. 16: Duty cycle of switches in phse A (O2 SVM); (): Conduction duty cycle of outer switch (S A1), (): Conduction duty cycle of inner switch (S A2) Figure 4. 17: Duty cycle of nti-prllel diodes in phse A (O2 SVM); (): Conduction duty cycle of outer diode (D A1), (): Conduction duty cycle of inner diode (D A2) Figure 4. 18: Conduction duty cycle of clmping diode in phse A (O2 SVM) Figure 4. 19: Duty cycle of switches in phse A (O3 SVM); (): Conduction duty cycle of outer switch (S A1), (): Conduction duty cycle of inner switch (S A2) Figure 4. 2: Duty cycle of nti-prllel diodes in phse A (O3 SVM); (): Conduction duty cycle of outer diode (D A1), (): Conduction duty cycle of inner diode (D A2) Figure 4. 21: Conduction duty cycle of clmping diode in phse A (O3 SVM) Figure 5. 1: Block digrm for conduction power loss of switch in NPC three-level inverter in Simulink Figure 5. 2: Scheme of NPC three-level inverter in Simulink Figure 5. 3: Sector nd ngle determintion in Simulink Figure 5. 4: ringle determintion in Simulink Figure 5. 5: Switching signl sequence lock in Simulink Figure 5. 6: Stte sequence in Simulink; (): Generting numer of stte vector; (): numer of stte sequences Figure 5. 7: Six sectors in Simulink Figure 5. 8: Stte vectors of ringle 1, Sector 1 in Simulink Figure 5. 9: Wveforms of current, voltge nd instntneous power for SA1 (Norml SVM) x

11 LIS OF ABLES le 2. 1: Rting of the selected PMSM le 2. 2: Dt of PMSM current nd inverter voltge rtio le 2. 3: Losses nd junction temperture for devices in three-level inverter with SPWM le 3. 1: Switching opertion of the NPC three-level inverter le 3. 2: he Rnge of Angle in All Sectors le 3. 3: he Conditions for Determintion of the ringles le 3. 4: All switching Stte Sequences in SVM scheme for three-level inverter in tringle 1, ll sectors le 3. 5: Comintion of Current Polrities le 3. 6: he summry of Phse Similrities for Current Wveforms... 5 le 3. 7: Clcultion of θ mx ccording to lod ngle le 3. 8: he procedure to find current polrities le 3. 9: Stte vectors nd Relted Switches nd Diodes in ringle 1, Sector 1 (Norml SVM) le 3. 1: Conduction duty cycle for devices in ringle 1, Sector 1 (Norml SVM) le 3. 11: Stte vectors nd Relted Switches nd Diodes in ringle 1, Sector 2 (Norml SVM) le 3. 12: Conduction duty cycle for devices in ringle 1, Sector 2 (Norml SVM) le 3. 13: Stte sequences in ringle 1, Sectors 1 nd 2 (O2 SVM)... 6 le 3. 14: Stte vectors nd Relted Switches nd Diodes in ringle 1, Sector 1 (O2 SVM) le 3. 15: Conduction duty cycle for devices in ringle 1, Sector 1 (O2 SVM) le 3. 16: Stte vectors nd Relted Switches nd Diodes in ringle 1, Sector 2 (O2 SVM) le 3. 17: Conduction duty Cycle for devices in ringle 1, Sector 2 (O2 SVM) le 3. 18: Stte sequences in ringle 1, Sectors 1 nd 2 (O3 SVM) le 3. 19: Stte vectors nd Relted Switches nd Diodes in ringle 1, Sector 1 (O3 SVM) le 3. 2: Conduction duty cycle for devices in ringle 1, Sector 1 (O3 SVM) le 3. 21: Stte vectors nd Relted Switches nd Diodes in ringle 1, Sector 2 (O3 SVM) le 3. 22: Conduction duty cycle for devices in ringle 1, Sector 2 (O3 SVM) le 4. 1: Averge duty cycle of upper devices in phse A for two lod ngles (Norml SVM) le 4. 2: Averge duty cycle of upper devices in phse A for two lod ngles (O2 SVM) le 4. 3: Averge duty cycle of upper devices in phse A for two lod ngles (O3 SVM) le 4. 4: Comprison of verge duty cycle of upper devices otined from ll methods for two different lod ngles le 4. 5: Comprison of methods for duty cycle of upper devices in three-level inverter le 4. 6: Averge duty cycle of upper devices in phse A for three modultion indices (Norml SVM) le 4. 7: Averge duty cycle of upper devices in phse A for three modultion indices (O2 SVM) le 4. 8: Averge duty cycle of upper devices in phse A for three modultion indices (O3 SVM) le 4. 9: Comprison of verge duty cycle of upper devices otined from ll methods for three different modultion indices le 4. 1: Comprison of methods for duty cycle of devices in three-level inverter xi

12 le 5. 1: Prmeters of the devices in NPC three-level inverter le 5. 2: Prmeters relevnt to the three-level NPC inverter le 5. 3: Conduction power loss for upper devices in phse A (Norml SVM) le 5. 4: Conduction power loss for upper devices in phse A (O2 SVM) le 5. 5: Conduction power loss for upper devices in phse A (O3 SVM) le 5. 6: Comprison of conduction power loss of devices for three SVM methods le 5. 7: Comprison of methods for conduction power of devices in NPC three-level inverter (different lod ngles) le 5. 8: Conduction power loss for upper devices in phse A (Norml SVM) le 5. 9: Conduction power loss for upper devices in phse A (O2 SVM) le 5. 1: Conduction power loss for upper devices in phse A (O3 SVM) le 5. 11: Comprison of conduction power loss of devices for three SVM methods le 5. 12: Comprison of methods for conduction power of devices in NPC three-level inverter (different modultion indices) le 5. 13: HD of output current for phse A le 5. 14: Comprison of methods for HD of current xii

13 LIS OF SYMBOLS R herml resistnce th emperture difference P Power loss loss Z(j-c) Z(c-h) therml impednce from junction to cse therml impednce from cse to het-sink / junction temperture jigb Diode P / totl loss in device (switch nd diode) IGB Diode het sink temperture H R therml resistnce of the device from the junction to the cse th ( j c ) R therml resistnce from the cse to the het sink th ( c h ) Rd Rq id iq ωrλq ωrλd λd λq L d d-xis resistnce q-xis resistnce d-xis current q-xis current Induced EMF Induced EMF flux linkge in d-xis sttors flux linkge in q-xis sttors d-xis inductnce L q q-xis inductnce xiii

14 λm p e permnent mgnet flux linkge numer of poles Field torque K t orque constnt l Lod torque B J ωm ωr V R XL viscous friction moment of inerti mechnicl speed electricl speed terminl voltge resistnce of the PMSM inductive rectnce of the PMSM continuous I Mximum q-xis current phse m Vdc Lod ngle Modultion index DC source voltge P verge conduction power loss cond P verge switching power loss sw E Switching energy (on stte) ON E Switching energy (off stte) OFF j ( IGB ) junction temperture of switch j ( Diode ) junction temperture of diode xiv

15 VA, VB, VC hree phse desired output voltges V, V Voltges fter Clrke trnsformtion ngle of the reference voltge vector S,, d, d, d Smpling time corresponding durtions of the vectors corresponding duty cycle of the vectors P cond (t ) instntneous conduction power loss v ce (t ) voltge over the device i (t ) current flowing through the device v DC voltge source in pproximte model of semiconductor ce r c Resistnce in pproximte model of semiconductor I Averge current of semiconductor c vg I RMS vlue of semiconductor current c rms xv

16 CHAPER1: INRODUCION O HESIS he present thesis dels with the performnce of Neutrl-Point Clmped three-level inverter for the ppliction in Permnent Mgnet Synchronous Motor drive. As the motor speed increses, the unlnce therml losses pper mong the semiconductors of the inverter. Due to this therml unlnce in the inverter, the sfe power hndling cpcity of the inverter will e restricted. In order to improve the inverter opertion, in the present thesis, set of Spce Vector Modultion techniques is presented. he thesis comprises of 5 chpters. At the end of this chpter, rief description of ll chpters is presented INRODUCION O PERMANEN MAGNE SYNCHRONOUS MOOR he development of Permnent Mgnet Synchronous Motors (PMSM) mkes them more ttrctive in electric vehicle pplictions. he PMSM offers the fetures s the following [1-2]: - High efficiency, high power density, high power fctor, high strting torque nd high cruising speed, - Smll size, light weight, smll moment of inerti, useful for limited-spce electric vehicles, - It is lso suitle for the ccelertion of strting due to its lrge output torque t low speed. he PMSM is supplied y the converter which hs DC source. he improvement in controlling the semiconductors of the converter hs lso llowed the converter to generte the wveforms with higher qulity. he digrm of PMSM nd the converter is shown in the Figure 1.1 [3-4]: 1

17 Figure 1. 1: Digrm of converter nd PMSM Considering Figure 1.1, in the present project, the gting pulse genertion nd three-phse inverter is studied. By pplying three controllers, speed nd torque re controlled. hese controllers re speed controller, torque controller nd flux controller. he control strtegy ccentutes the control of speed nd current in d nd q xes. Considering the speed rnge of the motor, there re two operting regions for the PMSM; the first region is the Norml rnge of opertion. In this region, the torque is constnt t its mximum vlue nd the speed is elow the rted vlue. 2

18 orque (NM) Power (KW) he other region is the Field-Wekening region. In this region, the speed is eyond the rted vlue nd the power remins constnt. he plot of these regions for the selected PMSM in this study is illustrted in Figure orque & Power vs. Speed Speed (RPM) orque Power Figure 1. 2: orque nd power vs. speed, PMSM 1.2. INRODUCION O POWER CONVERERS FOR ELECRIC VEHICLES In electric vehicles, it is essentil to increse the driving distnce. However, the driving distnce is limited y the losses in the devices. herefore, in order to reduce the size of the cooling system for the devices in the converter, the losses should e decresed. 3

19 Nowdys, controlled AC Drives re used in the ppliction res of medium voltge (MV) nd high power. Since it is hrd to connect single power semiconductor to the MV network, series of multi-level converters hve got ttention in the ppliction of medium voltge nd high power. here re two types of inverters; Voltge Source Inverter (VSI) nd Current Source Inverter (CSI). In the present study, the VSI hs een selected for the ppliction of PMSM drive, ecuse the electric vehicle will e powered y ttery pck. A VSI is pplicle to convert DC voltge to three phse AC voltge. ypiclly the converters used in EVs re 3-phse 2-level inverters with Pulse-Width Modultion (PWM). However, the inverters tht re controlled y PWM, led to dditionl switching losses. So they need greter cooling components [5-6]. he min reson for the ppernce of the multilevel inverters insted of 2-level inverters is the high vlue of DC voltge in the source. herefore, for higher voltge rtings, there is no need to use switches with high voltge rtings. herefore, it is possile to connect in series the switches with low voltge rtings. Unlike the simple connection of switches in series, multi-level converters nturlly limit the voltge stress on the switches to sfe vlues. he digrm of two-level inverter nd the voltge wveform is shown in Figure 1.3: 4

20 () () Figure 1. 3: () wo-level inverter digrm, () output line voltge 5

21 According to Figure 1.3, the voltge is comprising fundmentl frequency component nd severl hrmonic components. hese hrmonics cuse the losses in switches nd lower power qulity in the output. In ddition, in two-level inverter, ech switch tolertes the voltge vlue of V dc 2 considering tht the DC source isv dc. A multilevel converter divides the DC source vlue directly or indirectly, so tht the output of ech leg cn e more thn two steps (levels). In ddition, the qulity of the output wveform gets improved with lower distortion due to the use of oth mplitude modultion nd pulse width modultion. Multilevel converters re eing used in high nd medium power pplictions due to their dvntges such s low hrmonic contents nd low electromgnetic interference (EMI) outputs. Moreover, the switching technique selected to control the converter will hve n effective role in hrmonic elimintion even in two level inverters. he switching technique nd the topology of the converter is selected ccording to power demnds of the converters. Multi-Level converters comprise series of power semiconductors in ech leg nd cpcitors s voltge sources. Due to this configurtion, the power semiconductors withstnd the reduced voltges while in the output, there is high level voltge. his cn e done y mens of clmping diodes in NPC inverters or y flying cpcitors in other configurtion of multilevel inverter. he more incresing the numer of levels, the more steps will pper in the output voltge, so the multi-level converter genertes stircse wveform, with lower hrmonic distortion. he numer of levels of the multilevel inverter is indeed, the numer of steps of phse voltge with respect to the negtive terminl of the converter [7]. So, three-level inverter genertes the output voltge with three-levels. In ddition, the numer of levels of the output line voltge (voltge etween two phses), denoted s K is clculted s the following: 6

22 K 2 M 1 (1.1) where M is the numer of levels in the multi-level inverter. For exmple, for three-level inverter, there re 2 3-1=5 steps in the output line voltge. Multi-level inverters offer severl dvntges s the following [7-8]; ) Applicle in networks with high power nd medium (high) voltge with low hrmonic distortion in the output voltge nd current ) Low common mode voltge, so the stress in the motor erings is reduced c) Low voltge stress on power semiconductors d) High efficiency for fundmentl frequency switching e) he output voltges hve lower distortion thn conventionl two level inverter f) hey drw input current with very low distortion here re numer of topologies of multilevel converters tht hve een proposed since he most populr multi-level inverter topologies re Flying Cpcitor (Clmping Cpcitors) [9], Neutrl-Point Clmped (NPC) [1] nd Cscded H-Bridge [11]. In this study, the three-level NPC hs een selected. he three-level inverter consists of 12 switches which re divided into three phses. If the DC source hs the voltge vlue of V, ech switch hs to e rted t V 2 dc dc. In the present study, the Neutrl-Point Clmped (NPC) three-level inverter hs een selected in the ppliction of PMSM drive. In ddition, the choice of the switches is IGB ecuse they re the most common switches for the power rnge under considertion (6V nd 75 kw). he configurtion of three-level NPC VSI nd the voltge wveforms re illustrted in Figures 1.4 nd

23 Figure 1. 4: NPC hree-level inverter 8

24 Figure 1. 5: Line voltge of hree-level inverter with PWM By compring Figure 1.3 () nd Figure 1.5, it cn e seen tht in three-level inverter, the voltge hs more steps, so it is more similr to sinusoidl wveform thn the output voltge of two-level inverter GAING SIGNAL GENERAION here re different modultion techniques to control the switches of multi-level inverters [7]: ) Sinusoidl Pulse Width Modultion (SPWM) 9

25 ) Spce Vector Modultion (SVM) he sic principle of PWM technique is the comprison of two wveforms: reference wveform t low frequency (fr) nd tringle or sw-tooth crrier t high frequency (fs). If the mgnitude of the reference wveform is greter thn the mgnitude of the crrier wveform, then the switch gets on; otherwise it remins in its off stte. he Sinusoidl Pulse Width Modultion (SPWM), is kind of PWM technique to control the switching of converter. he SPWM technique is populr modultion method in the pplictions regrding hrmonic reduction. In SPWM, to generte the gte signls for the switches of the inverter, sinusoidl reference voltge wveform is compred with tringulr crrier wveform. he SPWM modultion method is depicted in Figure 1.6. Figure 1. 6: he SPWM modultion method he sinusoidl reference wveform is compred to tringulr crrier wveform. herefore, the gting signl is generted for prticulr complementry pir of switches in the inverter. Since SPWM seprtely controls the phses, for three phse converter, three SPWM controllers re needed. In these three SPWM controllers, the reference wveforms should e 12 o prt from ech other. 1

26 In Spce Vector Modultion (SVM) method, the switching sttes re determined y the position of the reference voltge vector nd the corresponding vector times. In SVM method, the inverter cn e controlled y mens of switching sttes. Hence, ech switching stte is relted to set of three phse voltge. he desired output phse voltges of the inverter re synthesized. he tsk of the modultor is to decide out two concepts: the switching stte the switches should hve nd then, the duty cycle of the switches for synthesizing the reference voltge vector. he numer of switching sttes in n n-level converter is n 3. he detils of the modultion scheme re presented in Chpter 3. he Spce Vector digrm for three-level inverter is illustrted in Figure 1.7. Figure 1. 7: he Spce Vector Modultion digrm 11

27 According to Figure 1.7, the switching sttes re three-it numers tht will e discussed completely in Chpter POWER LOSSES IN HREE-LEVEL INVERER Ech power device hs some fetures such s limited tempertures. While the inverter is operting, the temperture of the device cn e evluted y clculting the losses. Semiconductor power losses re divided into three groups: Conduction losses (Pcond), Switching losses (Psw) nd Blocking (Lekge) losses (P) [12]. he Blocking losses re normlly neglected, so the power losses re comprising the conduction nd the switching losses. In the present study, novel modultion strtegy hs een proposed y virtue of which the conduction loss of devices hs een redistriuted. herefore, the life cycle of devices will e incresed nd the sfe opertion region of inverter will e extended. In order to compute the junction temperture of switch, tht switch is mounted on multilyer structure. hese lyers hve different tempertures, therefore there will e n energy flow from the lyer with higher temperture towrd the lyer with lower temperture. herml resistnce defines the temperture difference etween two successive lyers for unit power loss: R th (1.2) P loss here is loss model presented in [13] to evlute the losses of power semiconductor devices. he therml model of switch with nti-prllel diode nd clmping diode hs een shown in Figure

28 Figure 1. 8: herml model of switch, its nti-prllel diode nd clmping diode In this model, Z(j-c) is the therml impednce from junction to cse nd Z(c-h) is the therml impednce from cse to het-sink. here is formul from which the stedy stte men junction temperture of ech device cn e evluted [14-15]: jigb P. ( R R ) H IGB / Diode th ( j c ) th ( c ) (1.3) / Diode h where is the junction temperture, P is the totl loss in device (switch nd diode), jigb / Diode IGB / Diode is the het sink temperture, R th ( j is the therml resistnce of the device from the junction to c ) H the cse nd R th ( c is the therml resistnce from the cse to the het sink. he junction temperture h ) of ech device of three-level NPC inverter leg versus motor speed, for n inverter operting with 13

29 Junction emperture (degree) SPWM hs een illustrted in Figure 1.9. here one cn oserve the unlnce in the junction tempertures Junction emperture vs. Speed Speed (RPM) Figure 1. 9: Junction temperture of ech device versus speed 1.5. CONRIBUION OF HE HESIS In this project, NPC three-level inverter is considered in the ppliction of PMSM drive in electric vehicles. he min concern is regrding the therml losses of the semiconductors in the inverter. herefore, series of modultion techniques re investigted for three phse NPC threelevel inverter. hese methods re the modified Spce Vector Modultion strtegies y virtue of which the conduction power loss of devices hs een redistriuted. he conduction loss hs een trnsferred from the switches with higher loss to those with lower losses. herefore, the criticl switches will tolerte less stress nd operte for longer term. 14

30 In ddition, n index conduction duty cycle is introduced in the thesis in order to nticipte the efficiency of the presented methods for lncing the conduction power losses of devices. his is verified y conventionl simultion HESIS OULINE he first chpter hs een llocted to introduce the PMSM fetures for electric vehicles. hen, rief comprison of two-level nd multilevel inverters nd their common topologies hs een presented. here exist the switching strtegies for inverters tht hve een explined riefly. Moreover, sic principles of therml model for devices nd relted equtions hve een reviewed. In chpter 2, model of PMSM in rotor reference frme is presented. According to the PMSM s plot, the opertion rnge of the PMSM hs een determined. In tht region, the inverter opertion hs een evluted y mens of the voltge nd motor current. hen, the losses of the devices hve een clculted for three-level inverter with SPWM method. In chpter 3, the principle of the SVM methods (the conventionl nd the new ones) is explined. Accordingly, the conduction duty cycle of devices in NPC three-level inverter hs een clculted y pplying SVM methods. Chpter 4 hs een dedicted to evlute the impct of two prmeters individully on conduction duty cycle of devices in the NPC three-level inverter. hese prmeters re lod ngle nd modultion index tht re explined precisely in Chpter 3. In ddition, to determine the proper vlues for these prmeters, the opertion region of the PMSM is considered. In Chpter 5, the conduction power losses of the devices in the NPC three-level inverter re clculted. In this chpter lso, the impct of those two prmeters on conduction power loss is 15

31 investigted individully. In ddition, the HD of output current of the inverter is clculted to evlute the effect the new methods on the current hrmonic. In chpter 6, ccording to the results presented in chpter 4 nd chpter5, some conclusions re otined. In ddition, few future works re proposed tht demnds further reserches. 16

32 CHAPER 2: MODEL OF HE PERMANEN MAGNE SYNCHRONOUS MOOR 2.1. INRODUCION In this chpter, the PMSM model in rotor reference frme, the phsor digrm nd the single phse equivlent circuit for the PMSM re presented. Furthermore, the rms vlues of the output voltge nd current of the inverter re identified y mens of which the PMSM is supplied. he norml rnge of the PMSM hs een considered ccording to the torque-speed plot. hese will e used in the following chpters to clculte the required operting conditions for the power converter HE PMSM IN ROOR REFERENCE FRAME he PMSM is n AC synchronous motor. he rotor structure contins permnent mgnets without ny windings nd it provides the constnt field excittion. he PMSM is clssified into two types depending on the position of the mgnets in the rotor: the Surfce Mounted (round rotor) PM (SPMSM) nd the Interior Mounted PM (IPMSM). In this study, the Surfce Mounted Permnent Mgnet Motor hs een considered. Most of the control methods re sed on the PMSM model in the rotor reference frme. Accordingly, this model is presented in the following. With the help of Clrke trnsformtion, the lnced three phse quntities cn e trnsformed into lnced two phse qudrture quntities to otin simpler model for nlysis. By pplying the Prk trnsformtion, the lnced two phse orthogonl sttionry system cn e trnsformed into two phse orthogonl rotting reference frme. hus, the three phse sttionry 17

33 c frme is trnsformed into two phse synchronously rotting dq frme, where the voltges nd currents of the PMSM cn e represented y dc quntities, s opposed to c in the other references frmes. he model of PMSM in dq frme or the rotor reference frme hs een shown in Figure 2.1 [16]. Figure 2. 1: PMSM model in dq frme According to Figure 2.1, the induced voltges in d-xis nd q-xis windings cn e clculted s the following: 18

34 u d d d R i d d (2.1) r q dt u q R i d q (2.2) q r d q dt where Rd nd Rq re d-xis nd q-xis resistnces nd id nd iq re d-xis nd q-xis currents. he rottionlly induced EMF in the sttor is due to the rottion of dq reference frme t synchronous speed, ωr. hese EMFs re denoted s ωrλq nd ωrλd. he terms λd nd λq re the flux linkges in d-xis nd q-xis sttors nd defined s the following: d L i (2.3) d d m L i (2.4) q q q In SPMSM, the d-xis nd q-xis inductnces re equl: L L (2.5) d q he torque eqution in SPMSM is defined y [9]: e 3 2 p i m 2 (2.6) q his torque is essentilly the field torque due to the permnent mgnet flux linkge, λm nd the torque-producing component, Iq. In SPMSM, the numer of poles p, nd the permnent mgnet flux linkge λm re constnt. herefore, these prmeters cn e replced y constnt, Kt nd the torque cn e re-written s: K i (2.7) e t q 19

35 K t 3 2 p m 2 (2.8) he electro-mgnetic torque of motor should e lnced y the lod torque l, the viscous friction B nd the moment of inerti J of the motor. So, the electro-mgnetic torque is s the following: e d m B J (2.9) l m dt where ωm is the mechnicl speed nd it cn e defined y mens of the electricl speed, ωr nd the numer of poles, p : p (2.1) r 2 m 2

36 2.3. SINGLE PHASE EQUIVALEN CIRCUI OF PMSM he single phse digrm of PMSM is illustrted in Figure 2.2 [17]: Figure 2. 2: Single phse digrm of PMSM he sttor current in the PMSM is comprising two components: the flux producing component Id nd the torque producing current Iq. he lod ngle (power fctor ngle) is the ngle etween sttor phse current nd terminl voltge. Moreover, the torque ngle is the ngle etween the sttor phse current nd flux vector. In PMSM drive, there is constrint for the voltge; tht is the voltge increses with speed ut it cnnot exceed the nominl vlue. herefore, the flux component (or the ck EMF) must e reduced to llow the nominl voltge to e mintined while the speed is incresing [18]. In order to solve this limittion, it is vlule to introduce the Field-Wekening technique in PMSM. Accordingly, the PMSM hs two different phsor digrms for operting conditions; without Field-Wekening in which the speed is elow the se vlue nd with Field-Wekening tht is the 21

37 speed is eyond the se vlue. In the present study, the motor hs een nlyzed for the region elow the rted speed. hus, there is no need to pply the Field-Wekening technique. he phsor digrm of PMSM hs een illustrted in Figure 2.3 [19]: Figure 2. 3: Phsor digrm of PMSM without field-wekening According to the phsor digrm, the terminl voltge (V) is given y: V 2 2 ( E RI ) ( X I ) q q q (2.11) 2 V ( E RI ) ( X I ) (2.12) q q q In the region without Field-Wekening, 2. he speed is defined s elow: N 12 f (2.13) p where p is the numer of poles nd f is the sttor electricl frequency nd N is the electricl speed in RPM. According to (2.13), the fundmentl frequency of output voltge nd current of the inverter cn e otined vi (2.14): 22

38 f p N (2.14) 12 he power nd torque re relted y mens of the speed s elow: P (2.15). m m where ωm is the mechnicl speed of mchine in rd/sec. Below the se speed, the mximum torque is the rted torque nd the mximum power is incresing with speed increment. In this study, the following prmeters re considering for the PMSM, le 2.1: le 2. 1: Rting of the selected PMSM Prmeter R L Pcontinuous I pek Vlue 54 mω 278 μh 54 KW 116 A J.5 kgm 2 B.335Nm.sec No. of poles (p) 1 Bse speed 7367 RPM Furthermore, the orque-speed plot of the selected PMSM is lso shown in Figure 2.4. In this figure, the power versus speed is lso illustrted. 23

39 orque (NM) Power (KW) orque & Power vs. Speed Speed (RPM) orque Power Figure 2. 4: orque nd power vs. speed for the PMSM 2.4. INVERER VOLAGE AND ROOR CURREN A three phse Voltge Source Inverter (VSI) hs the responsiility to switch the DC-link voltge in the input nd generte sinusoidl fundmentl component of voltge to three phse motor t the output of the inverter. he speed of the motor is controlled y the mgnitude nd frequency of the sinusoidl output voltge [2]. In this study, three phse three-level NPC inverter is considered nd PMSM is connected to the output of the inverter NEURAL-POIN CLAMPED MULILEVEL INVERER he NPC inverter hs n importnt role in the wind turines nd electric vehicle industries. he multi-level NPC inverter offers dvntges such s common DC us for three phses to minimize the numer of cpcitors, high efficiency in the ppliction of fundmentl frequency switching nd the ility of pre-chrging the DC link cpcitors s group. 24

40 he topology of three-level NPC inverter is shown in Figure 2.5 [7-8]: Figure 2. 5: hree-level Neutrl-Point Clmped inverter In the three-level NPC inverter, the three phses of the inverter hve common DC us nd the DC us voltge is divided into three-levels y mens of two series-connected cpcitors, C1 nd C2. hese three-levels re V dc 2, nd V dc In ech leg, there re two pirs of complementry switches (S1 nd S3) nd (S2 nd S4) nd two clmping diodes (D5 nd D6). he outer switches (S1 nd S4) re minly operting for pulse width modultion nd the inner switches (S2 nd S3) re clmping the output terminl to the neutrl point, n. Moreover, the two clmping diodes re for clmping the switch voltge to hlf level of the DC us voltge, V dc 2. According to Figure 2.6, the output voltges cn e clssified into two groups; the AC voltge denoted s v n denoted s v, which is the voltge cross nd the neutrl point n, nd the DC voltge,, which is the voltge cross nd the negtive inverter terminl,. he difference etween v nd v is the voltge cross C2, V 2 [7]. n dc

41 Figure 2. 6: Single Phse Neutrl-Point Clmped hree-level inverter he neutrl point, n, is the middle point of the cpcitors, C1 nd C2. he output phse voltge, v hs three different sttes: 2, nd 2. For the first level, 2, the two upper n V dc V dc V dc switches, S1 nd S2, need to e turned on. For the zero level, two middle switches, S2 nd S3 nd for the third level, V dc 2 the two lower switches, S3 nd S4 need to e turned on. When the two upper switches, S1 nd S2 turn on, v V, so the lower clmping diode, D6, dc lnces the voltge shring etween the two lower switches, S3 nd S4 ecuse S3 locks the voltge cross C1 nd S4 locks the voltge cross C2. In three-level inverter, it cn e sid tht ech ctive switching device is required to lock voltge level of V 3 1) V 2. If the voltge rting of ech clmping diode is ssumed to e dc ( dc similr to tht of the ctive device, the numer of clmping diodes needed for ech phse is ( 3 1) (3 2 ) 2 [7]. 26

42 DAA SHEE OF PERMANEN MAGNE SYCHRONOUS MACHINE As mentioned efore, the PMSM hs two regions of opertion which re elow nd ove the se speed. For the region elow the se speed, the Field Wekening is not required. herefore, the current hs only the q-xis component which is the torque-producing current. In this region, the mximum torque is constnt nd the power is incresing depending on the speed increment s given: P m (2.16) m where is the torque nd ωm is the mechnicl speed of PMSM. he system frequency is lso getting lrger with speed incresing: f r 6 p (2.17) where p is the numer of the pole pirs nd ωr is the synchronous speed of PMSM. he inverter voltge is clculted ccording to the sinusoidl ck EMF nd motor currents s the following: V 2 2 [ EMF 6 ( RI X I )] [ 6 ( X I RI )] inv ( LL ) q L d L q d (2.18) 27

43 where R nd XL re the resistnce nd inductive rectnce of the PMSM nd Iq nd Id re q-xis nd d-xis currents of the PMSM. In the region elow the se speed, the d-xis current is zero ecuse there is no Field-Wekening. he q-xis current cn e clculted from (2.19). Below the se speed, the q-xis current is equl to its mximum vlue which is the continuous I. phse I continuous I phse ( no. of 6 P continous phses ) EMF 6 P ( no. of phses I ) EMF (2.19) q ( rms ) continous otherwise continuous phse In ddition, the lod ngle is clculted s the following: 18 X I RI L q d tnh( ) (2.2) ( EMF 6 ) RI X I q L d he dt tht hve een clculted ccording to the previous formuls re presented in le

44 le 2. 2: Dt of PMSM current nd inverter voltge rtio Speed (rpm) orque (Nm) Power (KW) EMF (V) Frequency (HZ) Vinv (V) Iq (A) Modultion index Lod Angle (degree) PF In le 2.2, the modultion index hs een clculted y (2.21): m Vinv (2.21) Vdc In the present study, the DC source voltge (Vdc) is ssumed to e 6V. he dt presented in le 2.2 re for the region elow the rted speed nd for the selected PMSM, the rted speed is 7367 rpm. 29

45 ESIMAION OF POWER LOSSES According to [15], to otin the junction temperture of the devices in the inverter, the verge vlues of conduction losses nd the switching losses re required. Conduction loss is the product of the current flowing through the device nd the voltge cross the device during its conduction. o otin the verge conduction loss, the conducting durtion of the device is lso needed: P cond 1 / 2 v ( t ) i ( t ) ( t ) d ( t ) (2.22) o clculte the verge switching power loss, the switching energy nd the switching frequency re required. he switching energy cn e otined from the switching energy curve versus the current tht is presented in the device dtsheet. he switching energy cn e plotted vi curve fitting s second-degree polynomil eqution of current. he expression for the verge switching power loss is s the following: 1 / 2 P f ( E E ) d ( t ) (2.23) sw sw ON OFF o determine the junction temperture of the devices, the verge conduction loss nd verge switching loss of the devices re required. he junction temperture cn e clculted s given elow for the IGB module F3L3R7PE4-INFINEON: ( IGB j j ( Diode ).16 ( P P ) con ).32 ( P P ) con sw sw cse cse (2.24) where cse is dependent on the totl verge power losses in one leg of the inverter nd the het sink temperture s given in (2.25). he het sink temperture is lso dependent on the totl 3

46 verge power losses in one leg of the inverter. In ddition, the liquid temperture is nother term of het sink temperture which is constnt. In this study, the liquid temperture is 55 o C. cse (.154 P totl ) ( 1 leg ) het sin k (2.25) het sin k ) (.35 Ptotl ( 1 leg ) liquid he losses nd the junction temperture of the devices in three-level inverter for vrious speeds in the region elow the se speed re presented in le 2.3. According to this tle, y incresing the speed, the junction temperture of ll devices re incresing. his sttement is vlid in the region elow the rted speed. Among the devices, the nti-prllel diodes re the coldest devices nd the clmping diodes re the hottest devices up to the speed of 45 RPM. 31

47 le 2. 3: Losses nd junction temperture for devices in three-level inverter with SPWM Speed Averge Conduction Power Loss Averge Switching Power Loss Junction emperture S1/4 S2/3 D1-4 D5/6 S1/4 S2/3 D1-4 D5/6 S1/4 S2/3 D1-4 D5/ CONCLUSION In this chpter, the norml rnge of the PMSM hs een considered ccording to the torquespeed plot. In ddition, for this rnge, the power losses of devices in the three-level inverter hve een clculted. In the following of the thesis, set of Spce Vector Modultion methods re presented in order to lnce the het mong the devices. 32

48 CHAPER 3: NEURAL-POIN CLAMPED (NPC) HREE-LEVEL INVERER WIH SPACE VECOR MODULAION (SVM) ECHNIQUE 3.1. INRODUCION In [14], the three-level NPC converter hs een investigted under low voltge ride through condition in the wind power genertion system. In this sitution, there is n unlnce in the junction temperture of devices in the three-level NPC converter. herefore, the sfe power hndling cpcity of the power converter will e restricted due to the hottest switches, while the others in principle re operting elow full cpcity. In order to lnce the temperture of devices in three-level NPC converter, the uthors hve proposed series of new SVM methods. In [14], the modultion index, m s n importnt fctor in SVM strtegy, hs een considered s.3. his prmeter is in fct the rtio etween the desired mplitude of the output voltge nd the mximum possile mplitude of undistorted sinusoidl voltge tht cn e generted. Since the modultion index is less thn.5, the SVM is pplicle only in the smll hexgon of SVM scheme tht hs een shown in Figure 1.9. In ddition, the phse ngle hs een considered to e 8 o in which the converter opertes with lrge mount of rective power. In the present study, the therml loss mong the power devices in three-level NPC inverter hs een investigted. he inverter is supplying the sttor voltges for SPMSM in n electric vehicle. he PMSM is operting in the region elow the se speed. So, there is no need to implement field wekening. In ddition, in order to conduct the study in the smll hexgon of SVM scheme, the modultion index is considered less thn.5. Since the hottest switches (inner switches nd clmping diodes), in this ppliction re the sme s those in [14], the techniques proposed in 33

49 [14] re implemented in the present project. In order to decrese the conduction power loss of the hottest switches in the NPC three-level inverter, the dwelling time of zero voltge level should e reduced. Hence, in the present study, the two modified SVM methods proposed in [14] re investigted for the SPMSM in electric vehicle to see how they performs for this ppliction. While pplying the proposed methods, the conduction power losses of devices in the inverter hs een clculted. he product of voltge cross the device nd current through the device hve een computed s instntneous conduction power of the device. he results illustrte tht the new methods cn help to redistriute the conduction losses mong the devices in order to prolong the life cycle of devices nd extend the inverter opertion rnge. For specific modultion index, the SVM methods hve een pplied for two different lod ngles to indicte the impct of lod ngle on conduction power loss of the devices. Afterwrds, to investigte the influence of modultion index on conduction power of the devices, for specific lod ngle, different SVM methods hve een implemented for three different modultion indices tht re less thn.5. In the following chpter, for ll conditions, the conduction power loss hs een computed to evlute the effectiveness of the methods regrding conduction power lncing mong power devices. Finlly, the HD of output phse current of the inverter hs een clculted for three different modultion indices to evlute the effect of the proposed methods on the current supplying the motor SPACE VECOR MODULAION (SVM) ECHNIQUE here re severl types of modultion techniques for two nd three-level converters. One of the most common techniques is Spce Vector Pulse Width Modultion. his method genertes the 34

50 gte drive signls for ll switches in the converter. he opertion of the inverter while producing sinusoidl output voltges cn e represented y different switching sttes (or stte vector) nd the SVM provides unique switching time clcultions for ech of these stte vectors. In this method, the desired output phse voltges of the converter re synthesized. he tsk of the modultor is to decide out the stte vector the switches should hve nd the duty cycle of the switches for synthesizing the reference voltge vector. he reference rotting spce vector voltge representing VA, VB nd VC (the desired output phse voltges) is computed s the following [21]: V ref 2 3 j ( 2 j 2 3 V j V V V e V e ) (3.1) A B C 3 So the mgnitude nd ngle of the reference voltge vector is [22]: V ref 2 ( V ) ( V ) 2 V ref V tn 1 ( V ) (3.2) By expnding (3.1), Vα nd Vβ cn e clculted s the following: 35

51 V 2 ( V 3 A 1 V 2 B 1 2 V C ) (3.3) V 2 ( V B V C ) 2 2 At every smpling instnt, the reference vector is synthesized from the three phse voltges. herefore, the durtion time for ech stte vector, tht will e discussed shortly, is clculted. Considering the following eqution, Vref is synthesized with three groups of spce vectors, (V), (V) nd (V). V S ref ( V V V ) (3.4) where V, V nd V re the vectors defining the tringle in which Vref is locted nd, nd re the corresponding durtions of the vectors nd S is the smpling time. So, the smpling time is equl to sum of the durtion of ech vector: S ) (3.5) ( All the switching sttes (stte vectors) nd the reference vector cn e represented in twodimensionl spce, which is hexgon comprising 6 sectors. 36

52 SPACE VECOR MODULAION (SVM) FOR HREE-LEVEL INVERER For three-level inverter, the spce vector digrm consists of 6 sectors nd ech sector is divided into 4 tringles. he spce vector digrm for three-level inverter hs een demonstrted in Figure 3.1 nd s smple, the first sector including 4 tringles hs een depicted in Figure 3.2. he short vector is in lue, the medium is in green nd the lrge vector is rown. Figure 3. 1: Spce vector Digrm for three-level inverter 37

53 Figure 3. 2: First Sector of the Hexgon Ech stte vector hs three its tht re pertined to three phses of the three-level inverter. he first it in the left side is relted to phse A, the middle it is for phse B nd the it in the right side is relted to phse C. For exmple, for the stte vector of 1-1, in phse A, the two upper switches, S1 nd S2; in phse B, the two middle switches, S2 nd S3 nd for phse C, the two lower switches, S3 nd S4 need to e turned on. Following the pttern for ech tringle in the sector results in n On/Off wveform for ech phse. he switch hs its switching informtion depending on where the reference vector is locted. According to Figure 3.1, the sequence of the stte vectors in ech tringle is defined in such wy tht only one switching trnsition occurs etween two stte vectors, otherwise the stress on the devices will e incresed if the switching trnsition occurs t two or three switches simultneously. herefore, in ll sectors, tringle 2 nd tringle 4 hve the counter clockwise direction nd tringle 3 hs the clockwise direction. But for tringle 1, it is little it different; in odd sectors, 1, 3 nd 5, the direction is counter clockwise nd for even sectors, 2, 4 nd 6, the direction is clockwise. he sequences should commence with the lowest vlues to keep the switching trnsition once per stte vector. So, -1 hs higher priority thn nd hs lso higher priority thn 1. As n exmple, for two stte vectors t the sme position, -1-1 nd 38

54 1, the sequence should commence with In ddition, to determine the strt point for sequence, the vlue of its should e considered. For exmple, in tringle 3 in sector 1, there re three stte vectors for the commencement, -1-1, -1 nd 1-1. he est stte vector to select is -1-1 ecuse the numer of lowest vlues in this stte vector is more thn other two stte vectors. As n importnt prmeter, the modultion index cn e determined ccording to the side length of the tringles in the sector. As illustrted in Figure 3.3, if the side length of the sector is 2 V dc 3, the modultion index is the rtio of the desired output phse voltge to the mximum sinusoidl phse voltge which is V 3. dc Figure 3. 3: he length of the sectors 39

55 For three-level NPC inverter, there re 288 wveforms for switching sequences; tht is 6 sec tors 4 tringles 3 phses 4 switches. However, only 144 of these wveforms re needed to clculte ecuse the lower switches in ech leg re complementry to the upper switches. he switching signls of ringle 1 in sector 1 hve een shown in Figure 3.4. he sequence is otined from Figure 3.1. Figure 3. 4: Switching Signls for ringle 1, Sector 1 In NPC three-level inverter, the output phse voltge hs three different vlues: V dc 2, nd V dc 2 ; ssuming tht the dc voltge source is V dc voltge, different switches in one leg need to e turned on.. Depending on the vlue of the output phse 4

56 Conforming to Figure 2.5, for V dc 2 in the output, upper switches S1 nd S2 need to e turned on. For the zero level, two middle switches, S2 nd S3 nd for the third level, V dc 2 the two lower switches, S3 nd S4 need to e turned on. he opertion of the switches hs een summrized in le 3.1 [23]. le 3. 1: Switching opertion of the NPC three-level inverter Output Phse Voltge S1 (Phses A,B,C) S2 (Phses A,B,C) S3 (Phses A,B,C) S4 (Phses A,B,C) V dc V dc As it is illustrted in Figure 3.5, ccording to the vector length, the stte vectors hve een clssified into 4 groups [24-25]: 41

57 Figure 3. 5: Vectors Length in Sector 1 ) Zero vectors which re locted in the center of the hexgon or t the origin of the sector. hese vectors re , nd 111. ) Lrge vectors whose length is 2 V dc 3. hese vectors re 1-1-1, 11-1, -11-1, -111, nd c) Medium vectors which re the height of ech sector nd their length is V 3 dc. hese vectors re 1-1, 1-1, -11, -11, -11 nd 1-1. d) Short vectors which re the digonls of the inner hexgon nd their length is V 3 dc vectors re -1-1, 1, -1, 11,-1-1, 1,-1, 11,-1-1, 1 nd -1,11.. hese 42

58 he SVM for three-level inverters cn e implemented y 4 successive steps: ) Sector determintion ) ringle determintion in one sector c) Clcultion of switching times;, nd d) Determintion of the switching sttes (stte vectors) SECOR DEERMINAION o determine the sector in which the reference voltge vector is locted, the following procedure should e considered. Since the hexgon is comprised of six sectors, ech sector is 6 o. Due to circulr symmetry, if the reference vector is locted in sectors other thn sector 1, it is possile to relocte the reference vector to the first sector. he equtions re in le 3.2. le 3. 2: he Rnge of Angle in All Sectors Sectors he rnge of the ngle How to get into the 1 st sector o 6 new old o 6 12 o o 18 o 24 o o o o o o 6 new old 12 new old 18 new old 24 new old 3 new old o o o o o 43

59 RIANGLE DEERMINAION IN ONE SECOR o determine the tringle in which the tip of the reference vector lies, there re four comprisons for two prmeters, denoted s m1 nd m2 which re clculted ccording to the ngle of the reference vector, θ: m 1 m (cos sin ) 3 (3.6) m 2 2 sin m ( ) 3 If (m1+m2) 1 3, then the reference vector is in tringle 1. If m1> 1 3, then the reference vector is in tringle 2. If m1 nd m2 1 3 nd (m1+m2) > 1 3, then the reference vector is in tringle 3 nd finlly, if m2> 1 3, then the reference vector is in tringle 4. he following tle is the summry of the procedure to find the tringle in which the reference vector lies. le 3. 3: he Conditions for Determintion of the ringles ringle Condition 1 m m ) 1 3 ( m m 1 1 m ( 2 m m ) m

60 CALCULAION OF SWICHING IMES Due to the similrity of sectors, it is sufficient to consider the first sector ( θ 6 o ) to clculte the times,, nd. he definition for times re different for the 4 tringles in sector 1 ut they re identicl for the corresponding tringle in other sectors. In this study, the PMSM is operting under the se speed. So, the nlysis in this work is limited to ringle 1. Accordingly, the time definition will e presented for ringle 1 in sector 1 nd they cn e generlized for other sectors. For the first tringle, the reference vector is synthesized y two short vectors nd one zero vector. Figure 3.6 hs shown the scheme nd the time clcultion is s the following [21]: Figure 3. 6: ringle 1 in Sector 1 45

61 11. is the time regrding the stte vectors -1-1 nd 1 nd is the time for -1 nd S ( m 3 cos sin ) S ( 2 m sin ) (3.7) S (1 m ( 3 cos sin ) ) SWICHING SAE DEERMINAION In the present study, the modultion indices hve een considered less thn.5. Hence, the reference voltge vector will e locted in ringle 1 in ll sectors (inner hexgon). he stte vector sequences of ringle 1 in ll sectors hve een presented in le 3.4. In ringle 1, there re 7 stte vectors in the stte sequence tht commences with zero stte vector, It should e considered tht these sequences re for hlf spce vector cycle nd for the second hlf, the sequence will e reversed. herefore, it will e terminted with the stte vector s indicted in Figure 3.4. le 3. 4: All switching Stte Sequences in SVM scheme for three-level inverter in tringle 1, ll sectors Sector ringle Switching Sttes Sequence , -1-1, -1,, 1, 11, , -1-1, -1,, 1, 11, , -1-1, -1,, 1, 11, , -1-1, -1,, 1, 11, , -1-1, -1,, 1, 11, , -1-1, -1,, 1, 11,

62 HREE SPACE VECOR MODULAION (SVM) MEHODS In the present study, three methods sed on SVM strtegy hve een presented; Norml, O2 nd O3. All these methods re pplied to generte the gting signls for the switches in threelevel inverter. he Norml SVM method is the common modultion method in which ll stte vectors mentioned in le 3.4 re used in the stte sequences. he stte sequence strts from zero stte vector, nd returns to the sme stte vector. herefore, the stte sequence comprises ll 7 stte vectors. In order to reduce the zero voltge dwelling time to redistriute the conduction power mong switches, two new SVM strtegies hve een presented; O2 nd O3 [14]. In O2 SVM, the stte vector is eliminted ut other stte vectors re kept in the stte sequence. herefore, there will e 6 stte vectors in sequence. In this method, the inner switches, S2 nd S3 will e relieved more due to the elimintion of the stte vector. In O3 SVM, two zero stte vectors nd 111 re ignored to decrese the stress on the outer switches, S1 nd S4. Hence, the stte sequence comprises 5 stte vectors, it strts from non-zero stte vector nd returns to the sme stte vector. In the following sections, the duty cycle of the devices otined vi these three modultion methods hve een presented to e lter used in the nlysis of the performnce of the methods DUY CYCLE DEFINIION he term Duty Cycle is principlly the proportion of ON time to one switching period, s (SVM cycle). In other words, the duty cycle descries the ON-stte of the device s percentge of the totl SVM cycle. herefore, low duty cycle for power device corresponds to low 47

63 conduction power losses ecuse the device is in OFF-stte for most of the time. In the present study, two terms regrding duty cycle hve een introduced; Enled Duty Cycle nd Conduction Duty Cycle. Bsed on the generted gting signls in SVM scheme, the switches in one leg get enled to conduct the current. However, either the switch or the nti-prllel diode is going to conduct depending on the direction of the output phse current, in tht leg. So, ech device conducts for frction of the switching period nd for the rest of the switching period, it remins open-circuit. In principl, since only switches need to e enled to conduct, the term Enled Duty Cycle is pplicle only for switches. However, this term is lso usele for clmping diodes, D5 nd D6, ecuse they conduct the zero stte current simultneously with S2 nd S3. he enled duty cycle is the durtion in which the switch is turned on ccording to the SVM method, ut it does not necessrily men tht the switch is going to conduct. he term Conduction Duty Cycle is for oth switch nd diode. It defines the proportion of conducting time to the switching period. In order to clculte the conduction duty cycle, it is importnt to determine the direction of the output phse current. Initilly, the switch needs to e enled. hen, if the direction of the output phse current is in ccordnce with the switch direction, the switch will conduct; otherwise the nti-prllel diode will conduct the current. herefore, the conduction duty cycle is the prmeter tht should e closely relted to the conduction losses of diodes nd switches. 48

64 EFFEC OF POWER FACOR ON CURREN POLARIIES After synthesizing given reference voltge vector, the current direction should e evluted. In order to determine the direction of output phse current, Power Fctor, tht is, the cosine of the ngle etween the voltge nd the current wveforms in phse, hs n importnt role. he power fctor long with the knowledge of the ngle of the phse voltge cn define whether the current is positive or negtive. Consequently, the pproprite devices (either switches or diodes) for conducting the current cn e determined. Afterwrds, the duty cycle of the devices cn e clculted ccording to the conduction time ssigned to ech device. Hence, to otin the conduction duty cycle, it is essentil to investigte the polrities of the output phse current. he comintion of the polrities for three phse currents is shown in le 3.5 ssuming the lnced sinusoidl currents with 12 o phse shift; ( t ) I Sin ( t ) i o, i ( t ) I Sin ( t 12 ) nd o i ( t ) I Sin ( t 12 ). c he polrities of phse currents re chnging every 6 o. Since the hexgon is 36 o, there re six groups of current polrities. le 3. 5: Comintion of Current Polrities Comintions Rnge of ωt Current Polrities -degree o < ωt < 6 o I > I < Ic > 6-degree 6 o < ωt < 12 o I > I < Ic < 12-degree 12 o < ωt < 18 o I > I > Ic < 18-degree 18 o < ωt < 24 o I < I > Ic < 24-degree 24 o < ωt < 3 o I < I > Ic > 3-degree 3 o < ωt < 36 o I < I < Ic > 49

65 he spce vector digrm is comprising six sectors ut due to the circulr symmetry, only the first two sectors hve een considered to study. herefore, for Sectors 1 nd 2, the rnge for reference vector ngle is o < θ < 12 o. In ddition, three phse wveforms cn e divided into three 12 o degrees. Bsed on the three phse wveforms, it cn e oserved tht there is similrity etween the second nd third 12 o segments of ech phse nd the first 12 o of the other phses. herefore, one cycle (36 o ) of 3 wveforms cn e otined from 12 o of the 3 wveforms. Accordingly, only the clcultion of the first 12 o of three phses is required to otin the whole 36 o of duty cycles for 3 phses. Regrdless of the power fctor, this strtegy for getting the 36 o of duty cycle is pplicle for different SVM methods. his homogeneous chrcter of wveforms is summrized in le 3.6. le 3. 6: he summry of Phse Similrities for Current Wveforms Phse Angle o < ωt < 12 o 12 o < ωt < 24 o 24 o < ωt < 36 o A A12 C12 B12 B B12 A12 C12 C C12 B12 A12 5

66 In order to investigte the ngle t which the first chnge in current polrity occurs for o < ωt < 12 o, mx should e clculted. Hence, for current wveform lgging the voltge wveform y certin ngle α, the vlue of mx is presented in le 3.7. le 3. 7: Clcultion of θmx ccording to lod ngle Lod ngle (α) θmx o 9 3 o mx 9 o 3 o o o 3 3 mx 3 o o o 3 9 mx o otin the current polrities for specific power fctor (or the phse ngle etween current nd voltge wveforms, α) there re two steps s the following: ) Find the pproprite comintion tht defines the polrities of the three-phse currents t certin time. his cn e done from o 9 : new he proper comintion for eginning cn e found ccording to this new ngle, comintion in which loctes will e the first comintion. new ) Determine the ngle t which current polrity chnges sed on. mx new. he o determine the comintion shifting, should e used; he first comintion is used mx in 6 nd if it is pplicle, the o, the second comintion in o mx mx mx third comintion in o o mx For vrious rnges of lod ngle, the procedure to investigte the current polrities is illustrted in le

67 le 3. 8: he procedure to find current polrities Lg lod ngle (α) θmx Strt comintion Comintion for sectors 1 & 2 Current polrities o o 3 I, I, Ic o 3 o Com_6 o o I, I, Ic o 3 9 o o 9 12 I, I, Ic o mx o 3 o o 3 Com_6 o 6 mx o I, I, Ic o o 6 6 I, I, Ic mx o o 6 12 I, I, Ic mx mx o I, I, Ic o 3 9 o o 3 Com_ o 6 mx 6 mx o o 6 o I, I, Ic o o 6 12 I, I, Ic mx 9 o 6 o Com_ o o o 6 I, I, Ic o o 6 12 I, I, Ic 52

68 CONDUCION DUY CYCLE FOR NORMAL SPACE VECOR MODULAION (SVM) ECHNIQUE For Norml SVM, there re 7 stte vectors in ringle 1; three of which re zero stte vectors nd the other four stte vectors re the ctive sttes. In Norml SVM, ll stte vectors re used in the sequence in order to synthesize the reference voltge. As stted in section 3.2.1, the direction of stte sequences in ringle 1, odd sectors differs to even sectors. herefore, due to the circulr symmetry in SVM scheme, only the nlysis pertining to Sector 1 nd Sector 2 re presented nd this could e generlized for other sectors. As mentioned previously, the conduction duty cycle is pplicle for oth switch nd diode. Considering the switching sttes, the switches nd diodes tht re conducting corresponding to ech stte vector hve een shown in le 3.9 for ringle 1, Sector 1. Recll tht the switches to e enled in given phse, depend on the spce vector to e used, which is defined y the SVM method. However, the conducting switches s well s diodes will lso depend on the direction of the current. For instnce, for spce vector , the stte of phse A is -1, mening tht SA3 nd SA4 re enled, ut will only conduct when IA<. Otherwise, with IA>, DA3 nd DA4 will conduct. Since spce vector with -1 s the first it is only used in the first of the 7 elements of the stte sequence in ringle 1 Sector 1, the enled time of, sy, SA4 is only 8 in 2 53 s. Its enled duty cycle would then e 8 2 while its conduction duty cycle could e the s sme vlue or zero, if t tht spce vector cycle the current in phse A ws positive. s 2 is used in this cse ecuse in one spce vector cycle (s) one executes the spce vector sequence once in the clockwise nd once in the counter clockwise directions, s shown in Figure 3.4 nd Figure 3.7. he durtion of, s well s of nd, will depend on the mgnitude nd position of the reference voltge vector t given time. Conversely, one cn see tht SA3 will e enled not only

69 during 8, ut lso 4, 4 nd 4, which correspond to the first 4 stte vectors of the 7-stte sequence used in ringle 1, Sector 1. S 1 1 ( ) d d d S (3.8) le 3. 9: Stte vectors nd Relted Switches nd Diodes in ringle 1, Sector 1 (Norml SVM) ringle 1 Zero(/8) (/4) (/4) 2*Zero(/4) (/4) (/4) Zero(/8) Phse Phse Phse c I> D 3, D 4 D 5, S 2 S 1, S 2 I< S 3, S 4 D 6, S 3 D 1, D 2 I> D 3, D 4 D 5, S 2 S 1, S 2 I< S 3, S 4 D 6, S 3 D 1, D 2 I> D 3, D 4 D 5, S 2 S 1, S 2 I< S 3, S 4 D 6, S 3 D 1, D 2 le 3.1 shows the expressions tht should e used for clculting the conduction duty cycle for the switches nd diodes of ll three phses when the reference voltge vector lies in ringle 1 Sector 1. As shown in le 3.6, one cn study full line cycle (36 ) of the three phse voltge wveforms from the first 12 of the three-phses. his corresponds to the reference voltge vector rotting in Sector 1 nd Sector 2. le 3.11 nd le 3.12 ring the sme informtion for Sector 2 tht le 3.9 nd le 3.1 presented for Sector 1. 54

70 Current Phse Phse Phse c le 3. 1: Conduction duty cycle for devices in ringle 1, Sector 1 (Norml SVM) I > I < Phse Switch Conduction duty Cycle Switch Conduction duty Cycle S ( ) D 1 ( ) s s S 2 2 s 2 ( ) D 2 ( ) s 2 8 s D ( ) S 3 ( 2 ) s 8 s D ( ) S 4 ( ) s 8 s 8 D ( 2 ) D 6 ( 2 ) s s S ( ) D 1 ( ) s 4 8 s 4 8 S ( 2 ) D 2 ( ) s s 4 8 D ( ) S 3 ( 2 ) s 8 4 s D ( ) S 4 ( ) s 8 4 s 8 4 D ( 2 ) D 6 ( 2 ) s s S c1 2 2 ( ) D c1 ( ) s 8 s 8 S c2 2 2 ( 2 ) D c2 ( ) s s 8 D c3 2 ( ) S c3 2 s ( ) s s 2 8 D c4 2 2 ( ) S c4 ( ) s s D c5 2 ( 2 ) D c6 2 ( 2 ) s s

71 le 3. 11: Stte vectors nd Relted Switches nd Diodes in ringle 1, Sector 2 (Norml SVM) ringle 1 Zero(/8) (/4) (/4) 2*Zero(/4) (/4) (/4) Zero(/8) Phse Phse Phse c I> D 3, D 4 D 5, S 2 S 1, S 2 I< S 3, S 4 D 6, S 3 D 1, D 2 I> D 3, D 4 D 5, S 2 S 1, S 2 I< S 3, S 4 D 6, S 3 D 1, D 2 I> D 3, D 4 D 5, S 2 S 1, S 2 I< S 3, S 4 D 6, S 3 D 1, D 2 Regrding the clcultion of times, nd in ringle 1 Sector 2, the first step is to relocte the vector to ringle 1, Sector 1 in order to rech esier nlysis. Although the initil stte vectors in sectors 1 nd 2 re identicl, the stte sequences re in opposite direction. According to Figure 3.8, the stte sequence in Sector 2 is in clockwise direction nd it should e shuffled to Sector 1 ( 6 new old o ). herefore,, nd will e used s the sequence of time s mentioned in le is the time regrding the stte vectors -1 nd 11 nd is the time for -1-1 nd 1. 56

72 Figure 3. 7: Switching signl nd stte sequence in ringle 1, Sector 2 (Norml SVM) Figure 3. 8: Stte vectors in ringle 1, Sector 2 57

73 Figure 3.7 depicts the switching signls of three phses in ringle 1, Sector 2 nd Figure 3.9 illustrtes Sector 2 shuffled to Sector 1. Figure 3. 9: Stte vectors in ringle 1, Sector 2 relocted to Sector 1 58

74 Phse Phse Phse c le 3. 12: Conduction duty cycle for devices in ringle 1, Sector 2 (Norml SVM) Current I > I < Phse Switch Conduction duty Cycle Switch Conduction duty Cycle S ( ) D 1 ( ) s 4 8 s 4 8 S ( 2 ) D 2 ( ) s s 4 8 D ( ) S 3 ( 2 ) s 8 4 s D ( ) S 4 ( ) s 8 4 s 8 4 D ( 2 ) D 6 ( 2 ) s s S ( ) D 1 ( ) s s S 2 2 s 2 ( ) D 2 ( ) s 2 8 s D ( ) S 3 ( 2 ) s 8 s D ( ) S 4 ( ) s 8 s 8 D ( 2 ) D 6 ( 2 ) s s S c1 2 2 ( ) D c1 ( ) s 8 s 8 S c2 2 2 ( 2 ) D c2 ( ) s s 8 D c3 2 ( ) S c3 2 s ( ) s s 2 8 D c4 2 2 ( ) S c4 ( ) s s D c5 2 ( 2 ) D c6 2 ( 2 ) s s

75 CONDUCION DUY CYCLE FOR O2 SPACE VECOR MODULAION (SVM) ECHNIQUE As mentioned efore, in this study, the modultion index is less thn.5. So in ll sectors, the reference voltge vector is locted in the first tringle. According to section , in Norml SVM, ll stte vectors re implemented in the switching stte sequence. However, in the first modified SVM method (O2), one of the zero stte vectors, is eliminted nd replced y the other two equivlent stte vectors which re nd 111. herefore, the time durtion for the zero stte vectors will e different from those of Norml SVM method. he stte sequences of ringle 1 in Sectors 1 nd 2 for O2 SVM re presented in le le 3. 13: Stte sequences in ringle 1, Sectors 1 nd 2 (O2 SVM) Sector ringle Switching Sttes Sequence , -1-1, -1, 1, 11, , -1-1, -1, 1, 11, 111 he stte sequence nd time durtion ssigned to ech stte vector in ringle 1, Sector 1 is shown in le

76 le 3. 14: Stte vectors nd Relted Switches nd Diodes in ringle 1, Sector 1 (O2 SVM) ringle 1 Zero(/4) (/4) (/4) (/4) (/4) Zero(/4) Phse Phse Phse c I> D 3, D 4 D 5, S 2 S 1, S 2 I< S 3, S 4 D 6, S 3 D 1, D 2 I> D 3, D 4 D 5, S 2 S 1, S 2 I< S 3, S 4 D 6, S 3 D 1, D 2 I> D 3, D 4 D 5, S 2 S 1, S 2 I< S 3, S 4 D 6, S 3 D 1, D 2 From le 3.13, it cn e seen tht the zero stte vector hs een eliminted from the stte sequences. herefore the totl time durtion for zero stte vectors is divided etween other zero stte vectors, nd 111. Since the zero stte vectors re common for the first tringle in ll sectors, the time division for zero stte vectors in other sectors resemles to tht of the first sector. Except the stte sequence nd zero stte time division, other properties of this method re similr to those of Norml SVM such s the direction of stte sequence of ringle 1 in ll odd sectors nd time durtion for other stte vectors. According to the generted gting signls, the switches in one leg get enled nd considering the direction of output current, either the switch or the nti-prllel diode is going to conduct. he devices conducting the current regrding ech stte vector hve een presented in le le 3.15 shows the expressions tht should e used for clculting the conduction duty cycle for the switches nd diodes of ll three phses when the reference voltge vector lies in ringle 1 Sector 1. In ddition, le 3.16 nd le 3.17 ring the sme informtion for Sector 2 tht le 3.14 nd le 3.15 presented for Sector 1. 61

77 Phse Phse Phse c le 3. 15: Conduction duty cycle for devices in ringle 1, Sector 1 (O2 SVM) Current I > I < Phse Switch Conduction duty Cycle Switch Conduction duty Cycle S ( ) D 1 ( ) s s S 2 2 s 2 ( ) D 2 ( ) s 2 4 s D ( ) S 3 ( ) s 4 s D ( ) S 4 ( ) s 4 s 4 D ( ) D 6 ( ) s 4 4 s 4 4 S ( ) D 1 ( ) s 4 4 s 4 4 S ( ) D 2 ( ) s s 4 4 D ( ) S 3 ( ) s 4 4 s D ( ) S 4 ( ) s 4 4 s 4 4 D ( ) D 6 ( ) s 4 4 s 4 4 S c1 2 2 ( ) D c1 ( ) s 4 s 4 S c2 2 2 ( ) D c2 ( ) s s 4 D c3 2 2 s ( ) S c3 ( ) s s 2 4 D c4 2 2 ( ) S c4 ( ) s s D c5 2 ( ) D c6 2 ( ) s 4 4 s

78 2 s. s 2 4 Conforming to le 3.15, the conduction duty cycle of inner switch, S2, is ( ) 2 s Compring this expression with the corresponding one in le 3.1 ( ( ) ), it cn e deduced tht the y implementing O2 SVM technique, the conduction duty cycle of inner switch, S2 is reduced. o mention the sme comprison for other inner switch, S3, these expressions re s ( 2 ) nd ( ) s s for Norml nd O2 SVM strtegies respectively. Accordingly, O2 SVM technique hs reduced the conduction duty cycle of inner switches. Moreover, for the clmping diodes, the conduction duty cycle in Norml SVM is ( ) 8 2 s 2 nd in O2 SVM is ( ). It is ovious tht the conduction duty cycle of clmping diodes hs een reduced y using O2 SVM technique. s 4 4 Phse Phse Phse c le 3. 16: Stte vectors nd Relted Switches nd Diodes in ringle 1, Sector 2 (O2 SVM) ringle 1 Zero(/4) (/4) (/4) (/4) (/4) Zero(/4) I> D 3, D 4 D 5, S 2 S 1, S 2 I< S 3, S 4 D 6, S 3 D 1, D 2 I> D 3, D 4 D 5, S 2 S 1, S 2 I< S 3, S 4 D 6, S 3 D 1, D 2 I> D 3, D 4 D 5, S 2 S 1, S 2 I< S 3, S 4 D 6, S 3 D 1, D 2 63

79 Phse Phse Phse c le 3. 17: Conduction duty Cycle for devices in ringle 1, Sector 2 (O2 SVM) Current I > I < Phse Switch Conduction duty Cycle Switch Conduction duty Cycle S ( ) D 1 ( ) s 4 4 s 4 4 S ( ) D 2 ( ) s s 4 4 D ( ) S 3 ( ) s 4 4 s D ( ) S 4 ( ) s 4 4 s 4 4 D ( ) D 6 ( ) s 4 4 s 4 4 S ( ) D 1 ( ) s s S ( ) D 2 ( ) s s D ( ) S 3 ( ) s 4 s D ( ) S 4 ( ) s 4 s 4 D ( ) D 6 ( ) s 4 4 s 4 4 S c1 2 2 ( ) D c1 ( ) s 4 s 4 S c2 2 2 ( ) D c2 ( ) s s 4 D c3 2 2 s ( ) S c3 ( ) s s 2 4 D c4 2 2 ( ) S c4 ( ) s s D c5 2 ( ) D c6 2 ( ) s 4 4 s

80 CONDUCION DUY CYCLE FOR O3 SPACE VECOR MODULAION (SVM) ECHNIQUE In Norml SVM method, ll 7 stte vectors in ringle 1 re used in the stte sequence. But in the second modified SVM (O3), two of the zero stte vectors, nd 111 re eliminted nd replced y the zero stte vector,. herefore, the time ssigned to ech stte vector will e different from tht in Norml SVM method. he stte sequences of the ringle 1 in Sectors 1 nd 2 for O3 SVM method is presented in le le 3. 18: Stte sequences in ringle 1, Sectors 1 nd 2 (O3 SVM) Sector ringle Switching Sttes Sequence , -1,, 1, , -1,, 1, 11 he stte sequence nd time ssigned to ech stte vector in ringle 1, Sector 1 for O3 SVM method is shown in le le 3. 19: Stte vectors nd Relted Switches nd Diodes in ringle 1, Sector 1 (O3 SVM) Phse Phse ringle 1 (/4) (/4) Zero(/2) (/4) (/4) I> D 5, S 2 S 1, S 2 I< D 6, S 3 D 1, D 2 I> D 3, D 4 D 5, S 2 S 1, S 2 I< S 3, S 4 D 6, S 3 D 1, D 2 Phse c I> D 3, D 4 D 5, S 2 I< S 3, S 4 D 6, S 3 65

81 According to le 3.19, it cn e deduced tht y eliminting the stte vectors nd 111, the totl time for zero stte vectors is llocted to the only remined zero stte vector,. Since the zero stte vectors re common for the first tringle in ll sectors, the time division for zero stte vectors in other sectors is similr to tht of Sector 1. All properties of this method re similr to those of Norml SVM except the stte sequence nd time division. le 3.2 shows the expressions tht should e used for clculting the conduction duty cycle for the switches nd diodes of ll three phses when the reference voltge vector lies in ringle 1 Sector 1. 66

82 Phse Phse Phse c le 3. 2: Conduction duty cycle for devices in ringle 1, Sector 1 (O3 SVM) Current I > I < Phse Switch Conduction duty Cycle Switch Conduction duty Cycle S ( ) D 1 ( ) s 4 4 s 4 4 S 2 2 ( ) 1 D 2 2 ( ) s 2 s 4 4 D 3 S 3 2 ( ) s D 4 S 4 D ( ) D 6 ( ) s s S ( ) D 1 ( ) s 4 s 4 S 2 2 s 2 ( ) D 2 ( ) s 2 4 s 4 D s ( ) S 3 ( ) s 4 s 2 4 D ( ) S 4 ( ) s 4 s 4 D ( ) D 6 ( ) s s S c1 D c1 S c2 2 ( ) s D c2 D c3 2 ( 2 ) S c3 ( ) 1 s 4 4 s 2 D c4 2 ( 2 ) S c4 ( ) s 4 4 s 4 4 D c5 2 2 ( ) D c6 ( ) s s

83 Along with the expressions in le 3.1 nd le 3.2, the conduction duty cycle of outer 2 switch, S1 is ( ) nd ( ) for Norml nd O2 SVM methods s s respectively. In ddition, for other outer switch, S4, the conduction duty cycle in Norml SVM is 4 4 ( ) 8 2 s nd in O2 SVM is. It indictes tht O3 SVM strtegy is n pproprite method to reduce the conduction duty cycle of outer switches. le 3.21 nd le 3.22 ring the sme informtion for Sector 2 tht le 3.19 nd le 3.2 presented for Sector 1. le 3. 21: Stte vectors nd Relted Switches nd Diodes in ringle 1, Sector 2 (O3 SVM) Phse Phse Phse c ringle 1 (/4) (/4) Zero(/2) (/4) (/4) I> D 3, D 4 D 5, S 2 S 1, S 2 I< S 3, S 4 D 6, S 3 D 1, D 2 I> D 5, S 2 S 1, S 2 I< D 6, S 3 D 1, D 2 I> D 3, D 4 D 5, S 2 I< S 3, S 4 D 6, S 3 68

84 Phse Phse Phse c le 3. 22: Conduction duty cycle for devices in ringle 1, Sector 2 (O3 SVM) Current I > I < Phse Switch Conduction duty Cycle Switch Conduction duty Cycle S ( ) D 1 ( ) s 4 s 4 S 2 2 s 2 ( ) D 2 ( ) s 2 4 s 4 D ( ) S 3 ( ) s 4 s D ( ) S 4 ( ) s 4 s 4 D ( ) D 6 ( ) s s S ( ) D 1 ( ) s 4 4 s 4 4 S 2 2 ( ) 1 D 2 2 ( ) s 2 s 4 4 D 3 S 3 2 ( ) s D 4 S 4 D ( ) D 6 ( ) s s S c1 D c1 S c2 2 ( ) D c2 s D c3 2 ( 2 ) S c3 ( ) 1 s 4 4 s 2 D c4 2 ( 2 ) S c4 ( ) s 4 4 s 4 4 D c5 2 2 ( ) D c6 ( ) s s

85 3.3. CONCLUSION In this Chpter, the expressions regrding the conduction duty cycle of switches nd diodes hve een computed. hese expressions present close reltion with the conduction losses. herefore, one should e le to etter ssess the impct of different modultion techniques on the conduction losses nd junction tempertures y oserving conduction duty cycle index. 7

86 CHAPER 4: CONDUCION DUY CYCLE OF SEMICONDUCORS IN NEURAL-POIN CLAMPED (NPC) HREE-LEVEL INVERER 4.1. INRODUCION his Chpter is focused on the determintion of the conduction duty cycle of switches nd diodes of three-level three-phse NPC inverter, with the three SVM methods mentioned in the previous Chpter. he ojective is to identify which one is more effective in providing the desired shift of conduction losses, required for reducing the power dissiption nd junction tempertures in key components. he impct of the modultion index nd lso of the power fctor will e considered in this study. Since the devices in three phses hve similr duty cycles, the plots hve een otined for only phse A. For the other phses there is 12 o phse shift etween the plots ENABLED DUY CYCLE VERSUS CONDUCION DUY CYCLE FOR NORMAL SPACE VECOR MODULAION (SVM) MEHOD As mentioned in section 3.2.3, the enled duty cycle of ll semiconductors of the converter operting with given SVM method cn e clculted from the mgnitude of the reference voltge vector. he conduction duty cycle requires the knowledge of the power fctor. In the following sections, since the inverter is expected to operte in symmetricl wy, insted of presenting the results of ll 4 switches nd 4 diodes of ll phses, only the results concerning S1 nd S2, outer nd inner switches, D1 nd D2, outer nd inner nti-prllel diodes s well s D5, clmping diode, of phse A re presented. 71

87 he vlues of the conduction duty cycle will e plotted versus the ngle of the reference voltge vector (θ) since this is common prmeter to ll SVM methods. he gol is to compre the mximum nd the verge vlues of conduction duty cycle of the semiconductors otined with the three SVM methods. hese plots hve een drwn y using the expressions in Chpter 3. For instnce, ccording to le 3.1, the conduction duty cycle of the outer switch, SA1 in Norml SVM strtegy is ( 2 s ) ( 4 4 8). his expression is for Sector 1 tht is the first 6 o. For the second 6 o which is Sector 2, the expression for conduction duty cycle is 2 s ) ( 4 8) considering ( le he sme procedure should e done for corresponding switches in phses B nd C. Afterwrds, for the second nd third 12 o segments of S1 in the three phses, the rules presented in le 3.6 should e implemented; tht is, the conduction duty cycle of SA1 in the second 12 o segment is equl to the conduction duty cycle of SC1 in the first 12 o. o drw the following plots for the conduction duty cycle of the devices, the expressions hve een implemented in MALAB/M-File for the three phses PLO ANALYSIS FOR OUER SWICH AND IS ANI- PARALLEL DIODE In order to demonstrte the seprte prts of the plots clerly, the following plots hve een otined for unity power fctor (φ = o ) nd modultion index (m) = he pproch of the reltion etween the plots of the conduction duty cycle nd enled duty cycle cn e generlized for other vlues of power fctor nd modultion index. In ddition, for other devices, the power fctor nd 72

88 modultion index re unity nd.4863 respectively. he modultion method is Norml SVM method ut the principl of the plots re the sme for other modultion methods, O2 nd O3 SVM. According to Figure 4.1, the enled duty cycle of S A1, (Figure 4.1 ) is exctly comprising the conducting duty cycle of S A1 (Figure 4.1 ) nd its nti-prllel diode, D1, (Figure 4.1 c). From o to 9 o nd 27 o to 36 o, the enled duty cycle of the switch is equl to the conduction duty cycle of the switch; tht is, during this period, the output current is in the direction of the switch. herefore, the outer switch is conducting the current. From 9 o to 27 o, lthough the switch is enled with vrying duty cycle, the nti-prllel diode conducts the current. So, the conduction duty cycle of the ntiprllel diode is identicl to the enled duty cycle of the outer switch. 73

89 () () (c) Figure 4. 1: Duty cycle of S1; (): enled duty cycle of S1, (): conduction duty cycle of S1, (c): conduction duty cycle of D1 74

90 PLO ANALYSIS FOR INNER SWICH, IS ANI-PARALLEL DIODE AND CLAMPING DIODE According to Figure 4.2, the enled duty cycle of S2, (Figure 4.2 ) consists of two prts; the conducting duty cycle of S2 (Figure 4.2 ) nd the nti-prllel diode, D2 (Figure 4.2 c). In two periods of o to 9 o nd 27 o to 36 o, the conduction duty cycle of the switch is identicl to its enled duty cycle ecuse the inner switch is conducting the current. From 9 o to 27 o, the nti- prllel nd clmping diodes conduct the negtive current. When the inner switch is operting for zero stte vectors, the clmping diode is lso conducting the current. herefore, the conduction duty cycle of inner switch is the enled duty cycle for o to 9 o nd 27 o to 36 o nd conduction duty cycle of the diode is the enled duty cycle for 9 o to 27 o. 75

91 () (c) () Figure 4. 2: Duty cycle of S2; (): enled duty cycle of S2, (): conduction duty cycle of S2, (c): conduction duty cycle of D2, (d): conduction duty cycle of D6 (d) 76

92 PLO ANALYSIS FOR CLAMPING DIODES As stted in le 3.1, the conduction duty cycle of D A5 is equl to tht of D A6 which is ( 2 s ) ( ). herefore, the conduction duty cycle of clmping diodes is.5. However, the clmping diodes do not conduct simultneously. When the output current is positive, D A5 conducts the current, otherwise for negtive current, D A6 conducts. In ddition, ccording to Figure 4.3, the enled duty cycle of D A5 is comprising the conducting duty cycle of D A5 nd D A6. It cn e deduced tht when D A5 is enled, either D A5 or D A6 conducts depending on the current polrity. () () (c) Figure 4. 3: Duty cycle of DA5; (): enled duty cycle of DA5, (): conduction duty cycle of DA5, (c): conduction duty cycle of DA6 77

93 4.3. INFLUENCE OF LOAD ANGLE ON CONDUCION DUY CYCLE OF DEVICES he plots of conduction duty cycle for two different lod ngles hve een otined from MALAB/M-File. he lod ngles selected from le 2.2 re o nd o nd the modultion index is he following plots re regrding upper devices in phse A ; outer switch, inner switch, outer nti-prllel diode, inner nti-prllel diode nd clmping diode. he lower devices re complementry with upper devices. Since the men vlue is ctully clculted y dding ll vlues together nd then verging them, to hve etter comprison, the verge vlue of conduction duty cycles of upper devices in one leg hve een presented CONDUCION DUY CYCLE FOR NORMAL SVM he plots of conduction duty cycle re shown in Figures for Norml SVM method. Furthermore, the verge vlue of conduction duty cycles of upper devices in one leg (phse A) hve een clculted nd presented in le 4.1. All the explntions re relevnt to upper devices nt it cn e generlized for corresponding switches. 78

94 () () Figure 4. 4: Duty cycle of switches in phse A (Norml SVM); (): Conduction duty cycle of outer switch (SA1), (): Conduction duty cycle of inner switch (SA2) 79

95 According to Figure 4.4, s the lod ngle increses, the conduction duty cycle of outer nd inner switches is shifting on the horizontl xis nd mke the plot wider in the first segment, where the mgnitude is lower nd nrrower in the second segment, where the mgnitude is higher. herefore, the verge vlue of the conduction duty cycle is decresed s the lod ngle is incresed. In ddition, the shpe of the conduction duty cycle for inner nd outer switch is similr ut they hve different mgnitudes. When the stte vector is 1 for phse, oth inner nd outer switches re conducting nd when the stte vector is, only the inner switch is conducting. herefore, when the current is in ccordnce with the switch direction, the inner switch hs higher conduction duty cycle thn the outer switch. Accordingly, there is difference in mgnitudes (.5) in the plot of outer nd inner switches. For the lower switches in one leg, the plot of conduction duty cycle will e with 18 o phse shift. As indicted in Figure 4.5, for the nti-prllel diodes, s the lod ngle increses, the plot of the conduction duty cycle includes higher vlues in the right section. Hence, the conduction duty cycle is incresed. Furthermore, oth inner nd outer nti-prllel diodes hve similr conduction duty cycle. his similrity indictes tht the outer nd inner switches conduct the output current for the equl period of time. In les 3.1 nd 3.11 lso, the conduction duty cycle for inner nd outer nti-prllel diodes is identicl. he conduction duty cycle of the upper clmping diode hs een shown in Figure 4.6. According to this figure, s the lod ngle gets lrger, the plot reloctes on 8

96 the horizontl xis ut the mount is constnt. So, the lod ngle does not hve ny impct on the conduction duty cycle of the clmping diode. In ddition, ccording to le 3.1, the conduction time for clmping diode is equl to hlf of the SVM smpling time, ( s 2 ) nd the duty cycle is.5 ( 2 s ( s 2 ) 1 2 ). 81

97 () () Figure 4. 5; Duty cycle of nti-prllel diodes in phse A (Norml SVM); (): Conduction duty cycle of outer diode (DA1), (): Conduction duty cycle of inner diode (DA2) 82

98 Figure 4. 6: Conduction duty cycle of upper clmping diode (DA5) in phse A (Norml SVM) le 4. 1: Averge duty cycle of upper devices in phse A for two lod ngles (Norml SVM) Phse A Devices m=.4863 φ = o φ =-2.17 o Switches Antiprllel diodes Clmping diodes S1 S2 D1 D2 D

99 According to le 4.1, the following sttements cn e deduced: 1- As the lod ngle increses (the power fctor decreses), the verge conduction duty cycle of switches is decresing. According to Figure 4.4 with φ = o, the switch will e conducting in segment with lower conduction duty cycle thn tht with φ = o. herefore, the switches will e less stressed in terms of conduction losses. 2- When the power fctor is reduced, the verge duty cycle of nti-prllel diodes gets lrger. So, the conduction duty cycle of diodes will e incresing. 3- he clmping diode hs constnt verge duty cycle. Also, s shown in Figure 4.6, the duty cycle plot is constnt. herefore, s the lod ngle chnges, there will e no chnge in duty cycle of clmping diode CONDUCION DUY CYCLE FOR O2 SVM he plots of conduction duty cycle re shown in Figures for O2 SVM method. Moreover, the verge vlue of conduction duty cycle of upper devices in one leg (phse A) is presented in le

100 () () Figure 4. 7: Duty cycle of switches in phse A (O2 SVM); (): Conduction duty cycle of outer switch (SA1), (): Conduction duty cycle of inner switch (SA2) 85

101 According to Figure 4.7, s the lod ngle increses, the switches will e operting more in segment with lower vlue. So, the conduction duty cycle of switches hs reduced. Furthermore, the shpe of conduction duty cycle for outer switch is different to the correspondence plot for Norml SVM (Figure 4.4.()). As indicted in le 3.1, the duty cycle of outer switch (S1) in Norml SVM is s ( 4 4 8) nd ccording to le 3.15, in O2 SVM is 2 2 s ( ). It is ovious tht in O2 SVM, the duty cycle of the outer switch is.5 which is constnt for o to 6 o tht is Sector 1, s seen in Figure 4.7.(). It seems tht y using O2 SVM method, the usge of the outer switch is incresing. For the inner switch, in Figure 4.7. (), the curve of the plot hs lrger slope in O2 SVM thn in Norml SVM (Figure 4.4.()). herefore, the inner switch is conducting less in O2 SVM thn in Norml SVM due to elimintion of the stte vector. As indicted in Figure 4.8, for the nti-prllel diodes, s the lod ngle increses, they re operting more in the segment with higher duty cycle. So, the conduction duty cycle gets lrger. In ddition, the inner nd outer nti-prllel diodes hve identicl conduction duty cycle. his similrity illustrtes tht the outer nd inner switches conduct the output current for the equl period of time. Even in les 3.15 nd 3.17, the nti-prllel diodes hve the sme conduction duty cycle. he conduction duty cycle of the upper clmping diode hs een depicted in Figure 4.9. Conforming to this figure, the shpe of the plot hs some convex curves which hve not ppered in plot of Norml SVM. Due to the elimintion of the stte vector nd ccording to le 86

102 3.15, there is no time regrding this stte vector (). So, the duty cycle does not hve constnt vlue nd it is smller thn the duty cycle in Norml SVM. () () Figure 4. 8: Duty cycle of nti-prllel diodes in phse A (O2 SVM); (): Conduction duty cycle of outer diode (DA1), (): Conduction duty cycle of inner diode (DA2) 87

103 Figure 4. 9: Conduction duty cycle of clmping diode (DA5) in phse A (O2 SVM) le 4. 2: Averge duty cycle of upper devices in phse A for two lod ngles (O2 SVM) Devices Switches Antiprllel diodes Clmping diodes S1 S2 D1 D2 D5 Phse A m=.4863 φ = o φ =-2.17 o

104 As indicted in le 4.2, the following sttements cn e deduced: 1- As the lod ngle is incresing, the verge duty cycle of switches is decresing. It cn e sid tht the lrger the lod ngle is, the less the switches re operting. 2- For ech lod ngle, the verge duty cycle of nti-prllel diodes re pproximtely similr. When the power fctor is reduced, the verge duty cycle of nti-prllel diodes gets lrger. So, the conduction durtion of the nti-prllel diodes will e incresing. 3- he verge duty cycle for the clmping diode is constnt. In ddition, ccording to Figure 4.9, lthough the device conducts more in the first segment, it will e less conducting in the second segment. So, the verge of the plot is constnt. Hence, y vrying the lod ngle, the verge duty cycle of the clmping diodes is not chnging CONDUCION DUY CYCLE FOR O3 SVM he plots of conduction duty cycle re depicted in Figures for O3 SVM method. Furthermore, the verge conduction duty cycle of upper devices in one leg (phse A) hs een presented in le

105 () () Figure 4. 1: Duty cycle of switches in phse A (O3 SVM); (): Conduction duty cycle of outer switch (SA1), (): Conduction duty cycle of inner switch (SA2) 9

106 According to Figure 4.1, s the lod ngle increses, the switches will e operting more in segment with lower vlue. So, the conduction duty cycle of switches hs reduced. Furthermore, for outer switch, the curve of the plot in O3 SVM hs lrger slope thn in Norml SVM (Figure 4.4. ()). So, the outer switch in O3 SVM is conducting less thn in Norml SVM, ecuse in O3 SVM, two zero stte vectors, nd 111 hve een eliminted. For inner switch, there is flt prt in the plot. As indicted in le 3.1, the duty cycle of the inner switch (S2) in Norml SVM is s ( s 2 8) nd s shown in le 3.2, in O3 2 SVM is 1 for the first 6 o which is Sector 1, s seen in Figure 4.1. (). herefore, y using O3 SVM method, the usge of the inner switch is incresing. As indicted in Figure 4.11, for the nti-prllel diodes, s the lod ngle increses, they re operting more in the segment with higher vlue of duty cycle. So, the conduction duty cycle gets lrger. In ddition, the inner nd outer nti-prllel diodes hve identicl conduction duty cycle. his similrity illustrtes tht the outer nd inner switches conduct the output current for the equl period of time. Figure 4.12 illustrtes the conduction duty cycle of upper clmping diode. Conforming to this figure, the shpe of the plot hs some concve curves which hve not een exposed in plot of Norml SVM. In Norml SVM, the conduction duty cycle is constnt t.5. In O2 SVM, it hs some curves etween.4 nd.5 tht indictes the decrement in the conduction. But in O3 SVM, the curves re vrying etween.5 nd.6 tht illustrtes the increment in the conduction. 91

107 () () Figure 4. 11: Duty cycle of nti-prllel diodes in phse A (O3 SVM); (): Conduction duty cycle of outer diode (DA1), (): Conduction duty cycle of inner diode (DA2) 92

108 Figure 4. 12: Conduction duty cycle of clmping diode (DA5) in phse A (O3 SVM) le 4. 3: Averge duty cycle of upper devices in phse A for two lod ngles (O3 SVM) Devices Switches Antiprllel diodes Clmping diodes S1 S2 D1 D2 D5 Phse A m=.4863 φ = o φ =-2.17 o

109 According to the results in le 4.3, the following sttements cn e deduced for modultion index (m) =.4863: 1- As the lod ngle is incresing, the verge duty cycle of switches is decresing. It cn e deduced tht y incresing the lod ngle, the verge conduction duty cycle of switches is reducing. 2- For ech lod ngle, the verge duty cycle of nti-prllel diodes re pproximtely similr. When the power fctor is reduced, the verge duty cycle of nti-prllel diodes gets lrger. So, the conduction of nti-prllel diodes will e incresing. 3- For the clmping diode, the verge duty cycle is constnt. According to Figure 4.12, the duty cycle plot hs some curves ut the verge of the plot is constnt. herefore, when the lod ngle is vrying, the verge duty cycle of the clmping diode remins constnt COMPARISON OF HE MEHODS In order to etter nlyze the SVM methods, ll the results concerning the verge conduction duty cycles for different power fctors re presented in le

110 le 4. 4: Comprison of verge duty cycle of upper devices otined from ll methods for two different lod ngles Modultion index m=.4863 Lod ngle φ = o φ =-2.17 o Methods Switches Anti-prllel diodes Clmping diodes S1 S2 D1 D2 D5 Norml O2 O3 Norml O2 O According to le 4.4, the following sttements cn e otined for m=.4863: 1- In Norml SVM, the inner switch, S2 hs lrger verge conduction duty cycle thn the outer switch, S1. By pplying O2 SVM, the duty cycle of outer switch, S1 hs een incresed y out 4.2% nd the duty cycle of inner switch, S2 hs een decresed y out 1.9% for oth lod ngles. It indictes tht y pplying O2 SVM, the conduction duty cycle for the inner switch hs een reduced nd for the outer switch, hs een incresed. herefore, O2 SVM is helpful to reduce the conduction duty cycle of the outer switch which hs lrger duty cycle thn inner switch for this prticulr vlue of modultion index nd specific lod ngle. 2- By implementing O3 SVM, the conduction duty cycle of outer switch, S1 ecomes less thn tht in Norml SVM nd the duty cycle of inner switch, S2 ecomes higher thn tht in Norml SVM. Hence, it cn e deduced tht for outer switch, S1, the conduction duty cycle cn e reduced y 4.2% nd for inner switch, S2, there will e n increment of out 1.9%. So, O3 95

111 SVM is useful to reduce the conduction duty cycle of outer switch for the modultion index (m) =.4863 nd specific lod ngle (either o or o ). 3- According to the lst two sttements, O2 SVM hs superiority over O3 SVM ecuse with the help of O2 SVM, the switches tht hve higher conduction duty cycle in Norml SVM, will e relieved nd the conduction duty cycle will e more lnced mong the switches for m= As indicted in previous sections, in ech SVM method, the clmping diodes hve similr duty cycles for different lod ngles. So, the clmping diodes hve identicl ehvior during conduction. If O2 SVM method is pplied, the duty cycle of the clmping diode is getting smller y out 7.13% nd y using O3 SVM, it hs n increment y out 7.9% for oth lod ngles. It indictes tht for the clmping diode, O2 SVM method is more efficient thn O3 SVM method for m= For the lod ngle of o, y pplying O2 SVM method, the conduction duty cycle of ntiprllel diodes hs een incresed y out 24.93% nd with the help of O3 SVM method, the conduction duty cycle hs een decresed y out 25.21%. Moreover, for the lod ngle of o, these percentges will e 23.75% of increment y O2 SVM nd 23.48% decrement y O3 SVM for diodes. herefore, for nti-prllel diodes, O3 SVM method is preferle to O2 SVM method ecuse it helps the diodes to hve less conduction losses. he comprison of SVM methods is presented in le 4.5. hese comprisons re vlid for two presented lod ngles. 96

112 le 4. 5: Comprison of methods for duty cycle of upper devices in three-level inverter Devices Switches Anti-prllel diodes Clmping diodes S1 S2 D1 D2 D5 Comprison of methods O3 SVM < Norml SVM < O2 SVM O2 SVM < Norml SVM < O3 SVM O3 SVM < Norml SVM < O2 SVM O3 SVM < Norml SVM < O2 SVM O2 SVM < Norml SVM < O3 SVM According to le 4.5, O2 SVM is fvorle method for inner switches (S2 & S3) nd clmping diodes ecuse it helps to reduce the conduction duty cycles of these devices. On the other hnd, the conduction duty cycle of outer switches (S1 & S4) nd nti-prllel diodes is incresed. Furthermore, O3 SVM is fvorle for outer switches nd nti-prllel diodes due to the decrement in their conduction duty cycle. 97

113 4.4. INFLUENCE OF MODULAION INDEX ON CONDUCION DUY CYCLE he plots of conduction duty cycle for three different modultion indices hve een otined from MALAB/M-File. he modultion indices selected from le 2.2 re.853,.2218 nd.4863 nd the lod ngle is o. he following plots re relted to the upper devices in phse A ; outer switch, inner switch, outer nti-prllel diode, inner nti-prllel diode nd clmping diode. he lower devices re identicl with upper devices. In ddition, to hve simply sis for comprison, the verge vlue of the conduction duty cycles of upper devices in one leg hve een presented. Since the devices in the three phses hve similr duty cycles, the plots hve een otined for only phse A. For other phses there is 12 o phse shift etween the plots CONDUCION DUY CYCLE FOR NORMAL SVM he plots of conduction duty cycle re shown in Figures for Norml SVM method. Furthermore, the verge vlue of conduction duty cycles of upper devices in one leg (phse A) hve een clculted nd presented in le

114 () () Figure 4. 13: Duty cycle of switches in phse A (Norml SVM); (): Conduction duty cycle of outer switch (SA1), (): Conduction duty cycle of inner switch (SA2) 99

115 According to Figure 4.13, s the modultion index increses, the switches will e conducting more. So, the conduction duty cycle of outer nd inner switches gets lrger. In ddition, the shpe of the conduction duty cycle curves of the inner nd of the outer switch for specific modultion index re similr ut there is different mgnitude in the plot of the inner switch which is.5. When the stte vector is 1 for phse, oth inner nd outer switches re conducting nd when the stte vector is, the inner switches re conducting. herefore, when the current is in ccordnce with the switch direction, the inner switch hs higher conduction duty cycle thn the outer switch. Accordingly, there is reduction in the mgnitude in the plot of the inner switch. According to Figure 4.14, s modultion index increses, the plot of conduction duty cycle will e including less re. herefore, the conduction duty cycle of the nti-prllel diodes will e decresed. Furthermore, oth inner nd outer nti-prllel diodes hve similr conduction duty cycle. his similrity indictes tht the outer nd inner switches conduct the output current for n equl period of time. he conduction duty cycle of the upper clmping diode hs een shown in Figure According to this figure, the clmping diode hs constnt vlue for conduction duty cycle. According to le 3.1, the conduction time is equl to hlf of the SVM smpling time, s nd the duty cycle is.5. In ddition, since the lod ngle is constnt, there is no mgnitude difference for the plots. So, for different modultion indices, the plot of conduction duty cycle is unique. While the conduction duty cycle for upper clmping diode is zero, the lower clmping diode conducts the output current. 1

116 () () Figure 4. 14: Duty cycle of nti-prllel diodes in phse A (Norml SVM); (): Conduction duty cycle of outer diode (DA1), (): Conduction duty cycle of inner diode (DA2) 11

117 Figure 4. 15: Conduction duty cycle of clmping diode in phse A (Norml SVM) le 4. 6: Averge duty cycle of upper devices in phse A for three modultion indices (Norml SVM) Devices Switches Antiprllel diodes Clmping diodes S1 S2 D1 D2 D5 Phse A φ =-2.17 o m=.853 m=.2218 m= According to le 4.6, the following sttements cn e deduced for φ =-2.17 o : 12

118 1- here is correltion etween modultion index nd conduction duty cycle. For instnce, in Sector 1, when the modultion index (m) gets lrger from to.5, the reference vector gets closer to the stte vectors -1-1 nd 1 in one side nd -1 nd 11 in the other side of ringle 1. herefore, the durtion of using these stte vectors for vector synthesizing ugments nd the conduction duty cycle of switches is incresing. Hence, the switches will e conducting more. 2- When the modultion index is incresed, the verge duty cycle of nti-prllel diodes is decresing. So, the conduction of diodes will e reducing. 3- he clmping diodes hve constnt verge duty cycle. Moreover, Figure 4.15 hs shown tht the duty cycle plot is constnt. herefore, y vrying the modultion index, there will e no chnge in duty cycle of the clmping diodes CONDUCION DUY CYCLE FOR O2 SVM he plots of conduction duty cycle re shown in Figures for O2 SVM method. In ddition, the verge vlue of conduction duty cycles of upper devices in one leg (phse A) hve een clculted nd presented in le

119 () () Figure 4. 16: Duty cycle of switches in phse A (O2 SVM); (): Conduction duty cycle of outer switch (SA1), (): Conduction duty cycle of inner switch (SA2) 14

120 According to Figure 4.16, s the modultion index increses, the conduction duty cycle of the outer switch gets smller nd tht of the inner switch gets lrger. As mentioned in le 3.15, the 2 2 s 2 s s conduction duty cycle of SA1 in O2 SVM is ( ) ( ) ( ) nd of s s 4 s s SA2 is ( ). It is ovious tht s is smller thn s. So, the conduction duty cycle of 2 the inner switch increses while tht of the outer switch decreses. As indicted in Figure 4.17, the inner nd outer nti-prllel diodes hve identicl conduction duty cycle tht illustrtes the outer nd inner nti-prllel diodes conduct the output current for n equl period of time. he conduction duty cycle of the upper clmping diode hs een depicted in Figure Conforming to this figure, the shpe of the plot hs some convex curves which hve not ppered in plots of Norml SVM. Due to elimintion of the stte vector nd ccording to le 3.15, 2 there is no time () regrding this stte vector ( ( ) ). So, the duty cycle does not hve constnt vlue. s

121 () () Figure 4. 17: Duty cycle of nti-prllel diodes in phse A (O2 SVM); (): Conduction duty cycle of outer diode (DA1), (): Conduction duty cycle of inner diode (DA2) 16

122 Figure 4. 18: Conduction duty cycle of clmping diode in phse A (O2 SVM) le 4. 7: Averge duty cycle of upper devices in phse A for three modultion indices (O2 SVM) Devices Switches Antiprllel diodes Clmping diodes S1 S2 D1 D2 D5 Phse A φ =-2.17 o m=.853 m=.2218 m=

123 As indicted in le 4.7, the following sttements cn e deduced: 1- As the modultion index is incresing, the usge of zero stte vector 111 is decresing nd usge of non-zero stte vectors including is incresing; tht is, the outer switch will e conducting for smller durtion nd inner switch will e conducting for lrger durtion. herefore, the verge duty cycle of the outer switch, S1 is decresing nd of the inner switch is incresing. It cn lso e seen in Figure 4.16 tht y incresing the modultion index, the plot for the outer switch gets lrger slope nd the plot of the inner switch gets higher vlue of duty cycle. 2- For ech modultion index, the verge duty cycle of the nti-prllel diodes re pproximtely similr. When the modultion index gets lrger, the verge duty cycle of the nti-prllel diodes ecomes smller. So, the conduction of the nti-prllel diodes will e decresing. 3- According to Figure 4.18 nd le 4.7, s the modultion index is incresing, the verge duty cycle for the clmping diode is getting lrger CONDUCION DUY CYCLE FOR O3 SVM he plots of the conduction duty cycle re depicted in Figures for O3 SVM method. Furthermore, the verge conduction duty cycle of the upper devices in one leg (phse A) hs een presented in le

124 () () Figure 4. 19: Duty cycle of switches in phse A (O3 SVM); (): Conduction duty cycle of outer switch (SA1), (): Conduction duty cycle of inner switch (SA2) 19

125 According to Figure 4.19, s the modultion index increses, the conduction duty cycle of the outer switch ugments nd tht of inner switch reduces. When the modultion index increses from to.5, the reference vector gets closer to the non-zero stte vertices. herefore, the usge of 1 increses nd tht of decreses which mens tht the conduction duty cycle of S1 gets lrger nd tht of S2 gets smller. 2 As indicted in Figure 4.2, s the modultion index gets lrger, the nti-prllel diodes will e conducting more in the segment with higher vlue of duty cycle. herefore, the conduction duty cycle of nti-prllel diodes increses. In ddition, the inner nd outer nti-prllel diodes hve identicl conduction duty cycle. According to le 3.2, the conduction duty cycle for upper ntiprllel diode is ( ). Considering the figure nd the tle, it is resonle tht the outer s 4 4 nd inner switches conduct the output current for the equl period of time. Figure 4.21 illustrtes the conduction duty cycle of upper clmping diode. Conforming to this figure, s the modultion index increses, the usge of zero stte vectors decreses. herefore, the conduction duty cycle of the clmping diode gets smller. 11

126 () () Figure 4. 2: Duty cycle of nti-prllel diodes in phse A (O3 SVM); (): Conduction duty cycle of outer diode (DA1), (): Conduction duty cycle of inner diode (DA2) 111

127 Figure 4. 21: Conduction duty cycle of clmping diode in phse A (O3 SVM) le 4. 8: Averge duty cycle of upper devices in phse A for three modultion indices (O3 SVM) Devices Switches Antiprllel diodes Clmping diodes S1 S2 D1 D2 D5 Phse A φ =-2.17 o m=.853 m=.2218 m=

128 As indicted in le 4.8, the following sttements cn e deduced: 1- As the modultion index is incresing, the verge conduction duty cycle of the inner switches is decresing due to the decrement in using zero stte vector nd the verge conduction duty cycle of the outer switches is getting lrger due to the increment in using the non-zero stte For ech modultion index, the verge duty cycle of the nti-prllel diodes re pproximtely similr. When the modultion index is ugmenting, the verge duty cycle of the nti-prllel diodes gets lrger. So, the conduction of the nti-prllel diodes will e incresing. 3- As the modultion index vries etween nd.5, the verge conduction duty cycle of the clmping diode reduces due to the decrement in using the zero stte vector COMPARISON OF HE MEHODS In order to etter nlyze the efficiency of the SVM methods in reducing the conduction duty cycle, ll the results re presented in le

129 le 4. 9: Comprison of verge duty cycle of upper devices otined from ll methods for three different modultion indices Lod ngle Modultion index Methods φ =-2.17 o m=.853 m=.2218 m=.4863 Norml O2 O3 Norml O2 O3 Norml O2 O3 Switches Anti-prllel diodes Clmping diodes S1 S2 D1 D2 D According to le 4.9, the following sttements cn e otined for φ =-2.17 o : 1- By compring results for 3 different modultion indices, it cn e seen tht for low vlue of modultion index, its impct on different methods is significnt, while for higher vlue, the impct is low. Becuse when the modultion index is low, the zero stte vectors re the most used stte vectors nd s the modultion index increses, the usge of stte vectors in vertices of tringles is incresing. 2- In Norml SVM, the duty cycle of outer switch, S1 is less thn tht of inner switch, S2. For modultion index of.853, y pplying O2 SVM, the duty cycle of the outer switch hs een incresed y out 74.6% nd the duty cycle of the inner switches hs een decresed y out 26.82%. For modultion index of.2218, y pplying O2 SVM, the duty cycle of S1 hs een incresed y out 43.71% nd the duty cycle of S2 hs een decresed y out 17.36%. Finlly, for modultion index of.4863, y pplying O2 SVM, the duty cycle of the outer switch hs een incresed y out 4.2% nd the duty cycle of the inner switch hs een 114

130 decresed y out 1.93%. As indicted in this tle, y pplying O2 SVM, the conduction duty cycle for the inner switches hs een reduced nd for the outer switches hs een incresed. herefore, O2 SVM is n pproprite method to reduce the conduction duty cycle of switches which hve lrger duty cycle especilly for smll modultion indices. 3- By using O3 SVM, the duty cycle of the outer switch, S1 is less thn tht in Norml SVM nd the duty cycle of the inner switch, S2 is more thn tht in Norml SVM. For modultion index of.853, y pplying O3 SVM, the duty cycle of S1 hs een decresed y out 74.6% nd the duty cycle of S2 hs een incresed y out 26.8%. For modultion index of.2218, y pplying O3 SVM, the duty cycle of S1 hs got smller y out 43.7% nd the duty cycle of S2 hs een ugmented y out 17.4%. Finlly, for modultion index of.4863, y pplying O3 SVM, the duty cycle of the outer switch hs een cut down for out 4.2% nd the duty cycle of the inner switch hs got lrger y out 1.9%. Accordingly, O3 SVM is useful method to reduce the conduction duty cycle of switches which hve lower duty cycle prticulrly for smll modultion indices. 4- According to lst two sttements, for switches, O2 SVM hs superiority over O3 SVM ecuse in O2 SVM, the switches tht hve higher conduction duty cycle will e relieved nd the conduction duty cycle will e more lnced mong the switches. In ddition, O2 SVM will e more efficient to otin lower overll conduction losses if it is pplied for smll modultion indices. 5- In ech SVM method, the two clmping diodes hve similr duty cycle for different modultion indices. So, the two clmping diodes hve identicl ehvior during conduction. For modultion index of.853, y pplying O2 SVM, the duty cycle of the clmping diodes hs een decresed y out 83.7%. For modultion index of.2218, y pplying O2 SVM, the 115

131 duty cycle of the clmping diodes hs got smller y out 57.6%. Finlly, for modultion index of.4863, y pplying O2 SVM, the duty cycle of the clmping diodes hs een cut down y out 7.1%. herefore, O2 SVM is n effective method especilly for smll modultion indices to reduce the conduction duty cycle of the clmping diodes. 6- By using O3 SVM method, the conduction duty cycle of the clmping diodes hs got lrger. For modultion index of.853, y pplying O3 SVM, the duty cycle of the clmping diodes hs een incresed y out 83.7%. For modultion index of.2218, the duty cycle of the clmping diodes hs een ugmented y out 57.7%. Finlly, the duty cycle of the clmping diodes hs een incresed y out 7.1% for modultion index of So, O3 SVM method is incresing the conduction duty cycle of the clmping diodes especilly for smll modultion indices. 7- According to the lst two sttements, for the clmping diodes, O2 SVM hs superiority over O3 SVM ecuse in O2 SVM, the clmping diodes will e relieved nd the conduction duty cycle will e decresed. In ddition, O2 SVM will e more efficient when it is pplied for smll modultion indices. he comprison of SVM methods is presented in le 4.1. hese comprisons re vlid for three presented modultion indices. 116

132 le 4. 1: Comprison of methods for duty cycle of devices in three-level inverter Devices Switches Anti-prllel diodes Clmping diodes S1 S2 D1 D2 D5 Comprison of methods O3 SVM < Norml SVM < O2 SVM O2 SVM < Norml SVM < O3 SVM O3 SVM < Norml SVM < O2 SVM O3 SVM < Norml SVM < O2 SVM O2 SVM < Norml SVM < O3 SVM According to le 4.1, O2 SVM is fvorle method for inner switches (S2 & S3) nd clmping diodes ecuse it helps to reduce the conduction duty cycle of these devices. Nevertheless, the conduction duty cycle of outer switches (S1 & S4) nd nti-prllel diodes is incresed. O3 SVM is fvorle method for outer switches nd nti-prllel diodes due to the decrement in the conduction duty cycle CONCLUSION According to the results presented in this chpter, it cn e deduced tht in the first tringle of three-level inverter SVM scheme, s the modultion index or lod ngle vries independently, the conduction duty cycle of devices will e chnging considering the SVM method. In ddition, for specific lod ngle nd modultion index, O2 SVM method is efficient to reduce the conduction duty cycle of the inner switches nd clmping diodes. Furthermore, O3 SVM is n efficient method to decrese the conduction duty cycle of the outer switches nd nti-prllel diodes. 117

133 CHAPER 5: PERFORMANCE VERIFICAION BY SIMULAION 5.1. INRODUCION In NPC three-level inverter, there re four switches, four nti-prllel diodes nd two clmping diodes in ech leg (phse). Considering the generted gting signls nd current direction, some specific switches need to e enled nd ccordingly, some devices, either switches or diodes, or oth, strt to conduct. he computtion of the conduction duty cycle of semiconductors for three SVM methods hs een discussed in Chpter 3. In the present project, one of the concerns is to lnce the conduction power loss mong the switches in NPC three-level inverter. herefore in this chpter, the conduction power losses of devices in NPC three-level inverter hs een clculted in MALAB/Simulink. he three SVM methods hve een compred to investigte the pproprite method for lncing the conduction power loss of the switches. In ddition, since power qulity is importnt in motor drives, the totl hrmonic distortion (HD) of the output current for three-level NPC inverter using different SVM techniques hve een evluted. he Fst Fourier rnsform of the output phse current of the inverter hs een presented for three different modultion indices COMPUAION OF CONDUCION LOSSES When the semiconductor is in its ON-stte, there is voltge drop cross the device nd current flowing through it, thus resulting in conduction power loss tht hve mjor contriution to the totl power losses nd junction temperture of the semiconductors. 118

134 he instntneous conduction loss is the product of the voltge over the device ( v ce (t ) the current flowing through it ( i (t ) ): ) nd P ( t ) v ( t ) i ( t ) (5.1) cond ce It is worthy to mention tht for semiconductor conduction loss, there is n pproximte model which is series connection of DC voltge source ( v ce ) nd resistnce ( r c ): v ( i ) v r i (5.2) ce c ce c c So, ccording to (5.1) nd (5.2), the instntneous conduction power loss for semiconductor is given y: P cond 2 ( t ) v. i ( t ) r i ( ) (5.3) ce t c c c In ddition, there is n expression for the verge conduction power loss over one switching period tht is clculted y using the verge current ( I c vg ) nd RMS vlue of semiconductor current ( I ) [15]: c rms P cond vg 1 1 sw sw 2 2 P ( t ) dt (. ( ) ( )) cond v i t r i t dt V I r I ce c c c ce c vg c (5.4) c rms sw sw where sw is the inverse of switching frequency (1/fsw). 119

135 he instntneous conduction power loss cn e computed in MALAB/Simulink y using the voltge cross the semiconductor nd current flowing through the device in the three-level inverter. he digrm of the locks for clculting the conduction power loss is shown in Figure 5.1. Figure 5. 1: Block digrm for conduction power loss of switch in NPC three-level inverter in Simulink he inverter prmeters such s the rtings regrding the devices implemented in the MALAB/Simulink nd the prmeters of the NPC three-level inverter such s switching frequency nd output current re indicted in le 5.1 nd le 5.2 respectively. In ddition, the scheme of the NPC three-level inverter implemented in Simulink is shown in Figure 5.2. le 5. 1: Prmeters of the devices in NPC three-level inverter Prmeter R switch V f-switch R diode V f-diode vlue.422 Ω.8 V.293 Ω.56 V 12

136 le 5. 2: Prmeters relevnt to the three-level NPC inverter Prmeter vlue I output 116 A f sw f sys 126 HZ 21 HZ m.4863 V DC 6 V he system frequency (f sys ) is ctully the fundmentl output voltge frequency nd it hs een clculted ccording to the speed nd the numer of poles of the PMSM presented in le 2.2. Figure 5. 2: Scheme of NPC three-level inverter nd generting gting signls in Simulink 121

137 According to Figure 5.2., the simultion includes the 3-level 3-phse NPC inverter, the 3-phse lod nd the generting gting signl lock. his lock is including 4 locks in order to generte gting signls in 4 steps tht is explined in the following. his lock is shown in Figure 5.3. Figure 5. 3: 4-step gting signl genertion lock digrm o otin the instntneous conduction power loss in MALAB/Simulink, there is product of the voltge cross the device nd the current flowing through the device. his clcultion hs een done for three methods; Norml, O2 nd O3 SVM strtegies. o generte the gting signls for the switches, 4 locks hve een developed s the following: 1) Determine sector nd ngle: According to the clculted ngle of the reference voltge vector, the sector cn e determined. As mentioned efore, due to circulr symmetry, the ngle should e moved to Sector 1. he procedure hs een presented in le 3.2. he lock is depicted in Figure

138 Figure 5. 4: Sector nd ngle determintion in Simulink 2) Determine tringle: As discussed in section , ccording to 4 comprisons for two prmeters m1 nd m2, the tringle in sector cn e determined. le 3.3, hs presented theses comprisons. he lock implemented in Simulink is illustrted in Figure

139 Figure 5. 5: ringle determintion in Simulink 3) Switching signl sequence: In this lock, there re two su-locks. Primrily, the time (, nd ) re clculted ccording to (3.7). Next in order, the numer of the stte vector is defined. In ringle 1, there re 7 stte vectors in the Norml SVM method, so the numer of stte vectors is from 1 to 7. he min lock consisting of two su-locks is depicted in Figure 5.6. he clcultion implemented in the second su-lock nd the plot of the output signl of this lock, regrding the numer of stte vectors, re shown in Figure 5.7. Figure 5. 6: Switching signl sequence lock in Simulink 124

140 () () Figure 5. 7: Stte sequence in Simulink; (): Generting numer of stte vector; (): numer of stte sequences 125

141 4) Generte switching signls: According to the numer of the stte vector otined from the previous lock nd the numer of the sector, the pproprite sttes (ON-OFF) re generted for the switches. As illustrted in Figure 5.8, there re 6 sectors in which there re 4 tringles. In the present project, the study is held only in ringle 1. In Figure 5.9, the stte vectors of ringle 1 in Sector 1 re shown. According to the stte vector selector (Figure 5.6), the proper one is generted. For instnce, if the signl from the stte vector selector rings the numer 2, this corresponds to spce vector [ -1-1], which is implemented y enling S2 nd S3 in leg A nd S3 nd S4 in legs B nd C. Figure 5. 8: Six sectors in Simulink 126

142 Figure 5. 9: Stte vectors of ringle 1, Sector 1 in Simulink In order to evlute the methods regrding the verge conduction power loss in one line cycle, the DC component in FF of the instntneous conduction power hs een otined s n indiction of verge vlue for ll devices in phse A. he trend for the other two phses re similr to tht of phse A. As discussed in chpter 3, the results hve een otined in order to indicte the influence of two prmeters individully on conduction power loss; the lod ngle nd the modultion index. In the present chpter, these influences hve een investigted in MALAB/Simulink. In the following, there re two sections; the impct of lod ngle on conduction power loss vi three methods nd the impct of modultion index on conduction power loss vi three methods. Furthermore, the effect of these methods on the HD of the output current hve een investigted for different modultion indices. 127

143 5.3. INFLUENCE OF LOAD ANGLE ON CONDUCION POWER LOSSES OF DEVICES he conduction power loss of devices otined y three methods in MALAB /Simulink re presented in the following su-sections. he impct of two different lod ngles on conduction power loss is shown for SVM methods. he lod ngles elong to the speed rnge in which there is no field wekening for the PMSM. hese vlues re o nd o nd hve een selected from le 2.2 for the modultion index of he conduction power losses of semiconductors in the three-level inverter hve een otined for the output phse current (Iph) = 116 A, DC-link voltge (Vdc) = 6 V, fundmentl output voltge frequency (f) = 21 Hz nd switching frequency (fsw) = 12.6 KHz. his condition hs een pplied for ll three methods; Norml, O2 nd O3 SVM CONDUCION POWER LOSS FOR NORMAL SVM he verge conduction power loss of the devices otined from MALAB /Simulink re shown in le 5.2. he first implemented modultion scheme is the Norml SVM method. he wveforms regrding the voltge cross the device, the current through the device nd the conduction power of the device re shown in Figure 5.1. As n exmple, these wveforms hve een depicted for SA1 for two cycles (.95 sec). In ddition, the conduction power loss for upper devices in phse A for Norml SVM method is presented in le 5.3. he unit of conduction power is wtt. 128

144 Figure 5. 1: Wveforms of current, voltge nd instntneous power for SA1 (Norml SVM) 129