Multiplierless sigma-delta modulation beam forming for ultrasound nondestructive testing

Transcription

1 Key Engineering Materials Vols (2004) pp online at (2004) Trans Tech Publications, Switzerland Citation Online available & since 2004/Aug/15 Copyright (to be inserted by the publisher) Multiplierless sigma-delta modulation beam forming for ultrasound nondestructive testing Ho-San Han and Tai-Kyong Song Center for Medical Solutions Research Department of Electronic Engineering, Sogang University, C.P.O. Box 1142, Seoul, Korea Keywords: Ultrasound Imaging, Sigma-Delta Modulation, Dynamic focusing Abstract. Beamforming techniques based on sigma-delta modulation (SDM) have been proposed to reduce the hardware complexity of conventional multi-bit digital delay-sum beamformer, in which beamforming operation is performed upon over-sampled single bit sequences obtained by applying SDM to the received signals from each array elements. In conventional single bit SDM beamforming, the single bit sequence is altered in accordance with the associated dynamic focusing delays. The sum of all these altered sequences are passed to a demodulator, which also serves as a decimator, to obtain the aimed focused signal. Due to this signal distortion phenomenon, conventional single bit dynamic focusing produces low signal to noise ratio(sr) signals. In this paper, a multiplierless single bit dynamic focusing method is presented, which can completely eliminate the demodulation error. In the proposed scheme, the low pass filter(lpf) produces the demodulated signals for successive receive focal points at the rate of yquist rate, F, which are stored in a two-port memory. ext, the focused signal is obtained by simply adding these samples to those from other array elements. Since the demodulation filter length, L, is generally larger than the over sampling ratio, M, however, the proposed method requires using K ( = L / M ) demodulation filters. To reduce the hardware complexity, we also propose an efficient scheme to implement the demodulation filter with a simple accumulator. Compared to a traditional delay-sum beamformer using 8-bit 40[MHz] analog-digital conterts (ADCs), the overall beamformer complexity is reduced by about 80[%] in gate counts by using the proposed scheme, whereas both scheme provide almost the same image quality. Introduction Traditional delay-sum digital beamformer uses multi-bit analog-digital converts(adcs) to digitize the received signals from each array elements, with the sampling rate, 4 f 0 ( f 0 : center frequency of input signal). The data rate is increased during beamforming process by a factor of at least four to obtain the required delay resolution, for which the delay-sum beamformer requires a data interpolator per each channel. Since one output sample is needed for each imaging point(i.e., for each input data interval), the data interpolation is performed by passing the input data sequence through a multi-tap LPF, of which the coefficients can change dynamically. In summary, the traditional delay-sum beamformer need to have one ADC and one interpolator per each channel, each with a high degree of hardware complexity. Therefore, it is inadequate to be used for small-scale ultrasound scanners or multi-dimensional array systems with a large number of active channels[1-4]. To reduce the hardware complexity of the traditional digital beamformer, a new approach was developed. In the SDM beamformer, the received data from each array element is converted into an over-sampled 1-bit digital data through SDM. Focusing delays are applied to the 1-bit SDM data, yielding multi-bit focused SDM data. The focused SDM data are then demodulated with a LPF. Since the SDM process can be implemented with a simpler hardware than conventional multi-bit ADCs and only one demodulation filter is needed regardless of the number of active channels, the entire beamformer complexity can be reduced greatly[5,6]. All rights reserved. o part of contents of this paper may be reproduced or transmitted in any form or by any means without the written permission of the publisher: Trans Tech Publications Ltd, Switzerland, (ID: /04/08,11:12:38)

2 216 Advances in ondestructive Evaluation In conventional single bit dynamic focusing beamformer, dynamic focusing is carried out at the oversampling rate, i.e., for every bit of SDM data. This implies that the 1-bit SDM data sequence is altered because focusing delays vary with the sample position. This signal distortion causes demodulation error, resulting in degradation in image quality. It has been known that SR is severely degraded due to the signal distortion. Moreover, the signal distortion may prevent SDM beamforming scheme from being used with pulse compression techniques. Moreover, the demodulation filter is a LPF that requires a few hundred multiplers in most cases[7,8]. In this paper, a multiplierless block-based single bit dynamic focusing SDM beamformer is presented, which can completely eliminate signal distortion with a reduced hardware complexity. In the proposed method, dynamic focusing is performed at the yquist rate, F, for input data. For each imaging point, SDM samples to be added together are selected from all active channels according to the corresponding focusing delays. Then, for each channel, a block of data centered at the selected SDM sample is defined. ext, bit-wise block addition is performed to obtain the sum of all the blocks. Finally, the output of the block addition is fed to the demodulation filter. In consequence, if the block length is equal to the demodulation filter length, one can obtain the focused signal without any signal distortion. Direct realization of the proposed method requires L / M demodulation filters, where L is demodulation filter length and M is over-sampling ratio, which diminishes the advantage of the SDM beamformer in hardware complexity. To implement the proposed method with as small hardware as possible, we also propose an efficient implementation method, in which the demodulation filters are replaced with simple accumulators. A block-based single bit dynamic focusing SDM beamformer Method. Fig. 1 shows a conceptual block diagram of the proposed SDM beamforming method. And Fig. 2 shows a detail block diagram of Fig. 1. Focusing Delay Generator M 1bit shift 1bit block block Coefficients L.U.T. M 1bit shift Bit-wise block adder n bit block LPF bit Focused Signal 1bit block block Fig. 1. Conceptual block diagram of the proposed block-based single bit dynamic focusing SDM beamformer As described earlier, focusing delays are updated at the signal yquist rate F and for each focusing delay pattern, a block of SDM data is selected from each channel. Location of each block, of which the length is set identical to the demodulation filter length, is determined by the corresponding focusing delay. These blocks are then added together on a bit-to-bit basis to yield a block of focused SDM data. These focused SDM samples are simultaneously fed to the demodulation filter. Since the block samples for each channel are not altered during the entire process, the demodulation filter output will be identical to the output of a beamformer, in which the 1-bit SDM data is demodulated first in each channel and then delay-sum beamforming is performed on the demodulated signals at the

3 Key Engineering Materials Vols yquist rate. Therefore, the proposed scheme is free from the signal distortion due to the dynamic focusing delays in the conventional SDM beamformer. Transducer TGC & Pre-AMP 1-bit shift Transducer 1-bit shift data block Focusing delay generator Σ Σ Σ n bit data block n bit Bit-wise block-adder C0 C 1 C L 1 Σ LPF MUX bit Focused Signal Fig. 2. Detail block diagram of Fig. 1 Input signal (Analog) Modulated signal (1- bit / Mfs) Selected Block signal (1- bit block / fs) Summing signal (n- bits block / fs) Focused signal (- bits / fs) S 1 ( t) t q [ n 1 ] r1 l [ n] S k (t) l'th focalpoint t q k [n] r kl [n] Bit- wise Sum LPF i l [n ] y[l] S K (t) t q K [n] r Kl [n] Width=LPF length(l) Fig. 3. Signal processing steps in the proposed beamformer Fig. 3 Shows the signal processing flow of the proposed beamforming method, where the signal waveforms at the output of each step are illustrated. The received Rignals are converted into over-sampled 1-bit data sequence q k [n] of data rate MF s rate through SDM, where the subscript k represents the channel index. For each channel, a block of SDM data of length L, r k [n], is selected for each receive focal point, where the block update rate is F. All these data blocks are then added on a bit-to-bit basis. Finally, bit-to-bit multiplication of the focused block data i [n] with the impulse response of the demodulation filter is performed and the L multiplication results are added together to produce the aimed focused signal. Implementation. Direct realization of the proposed method requires only one demodulation filter, if the demodulation filter length L is smaller than the over-sampling ratio M. But, the filter length is generally larger than the over-sampling ratio, since the demodulation filter should have a narrow transition band with sufficient stop-band attenuation, whereas M is seldom larger than 4. This implies that the proposed method requires K ( = L / M ) block adders and the same number of very long demodulation filters.

4 218 Advances in ondestructive Evaluation Coefficients L.U.T. Focusing delay Generator C[i] x[ n i] Accumulator y K[n] y 0[ n ] MUX bit FIFO Σ bit Focused signal Accumul MAC MAC ator MUX bit FIFO Fig. 4. Efficient hardware structure for proposed SDM beamformer To reduce the overall hardware complexity of the proposed SDM beamforming scheme, we propose a hardware efficient architecture as shown in Fig. 4. In the proposed realization scheme, the locations of the block adders and demodulation filters in the direct realization are interchanged. This means that K demodulation filters are needed for each channel. ow, at each channel, the K filters produce the demodulated signals for receive focal points successively at the rate of F, which are stored in a two-port memory. The focused signal can be obtained by simply adding the samples stored at the same address of all the memories. The size of each memory can be made very small by using the well-known serial adder (or partial sum) scheme. ote that only one adder is needed for each channel. In the proposed realization scheme, each demodulation filter is replaced by a multiplier-accumulator (MAC). Since the input to each demodulation filter is 1-bit SDM data, the MAC can be replaced again with a simple accumulator. Each accumulator sums only the filter coefficients in a manner that filter coefficients to be multiplied by nonzero SDM sample are added and other coefficients are subtracted. Since such an accumulator is composed of one adder and one, the proposed scheme can be implemented with much smaller hardware complexity than the conventional multi-bit delay-sum beamformer. Simulation Results Image quality. To verify the proposed method, computer simulations are performed with a 3.5[MHz] linear array having 192 elements, 60[%] of a 6[dB] bandwidth, and 0.2[mm] inter-element spacing. The number of active channels to form each scanline is assumed to be 64. Transmit focus is fixed at z=30[mm] and dynamic focusing is employed on receive. Fig. 5. Computer generated B-scan images of a point target phantom with a 3.5[MHz] linear array: (a) delay-sum beamformer using 8-bit ADCs, (b) a single bit dynamic focusing SDM beamformer, and (c) the proposed SDM beamformer.

5 Key Engineering Materials Vols Fig. 5(a) shows the image obtained with a delay-sum beamformer, in which the received signals are sampled at 40[MHz] using 8-bit ADCs and the sample rate is increased to 160[MHz] by using a 4-fold interpolator. Fig. 5(b) and 5(c) show the images obtained with a conventional single bit dynamic focusing SDM beamformer and with the block-based SDM beamformer, respectively. In both SDM beamforming schemes, the same over-sampling ratio, M(=4) is used. Hence, the SDM data rate is 160[MHz]. Accordingly, both schemes use the same demodulation filter, a 160 tap FIR LPF. As shown in Fig. 5(c), the proposed SDM beamformer produces almost the same image as that of the traditional 8-bit beamformer, with no SR loss due to the signal distortion, which is clearly observed in the conventional SDM beamformer (Fig. 5(b)). Fig. 6 shows the axial beam patterns at the center scan line of each image in Fig. 5. Fig. 6. Comparison of the axial beam patterns of the three images in Fig. 5: (a) delay-sum beamformer using 8-bit ADCs, (b) a single bit dynamic focusing SDM beamformer, and (c) the proposed SDM beamformer. The traditional 8-bit beamformer (Fig. 6(a)) and the proposed method (Fig. 6(c)) have almost identical axial responses except for approximately 10[dB] difference in noise levels, whereas the single bit SDM beamformer suffers form high noise levels ( 20[dB] ~ 40[dB]). ote that the noise level of the conventional SDM beamformer is higher in the near field where focusing delays change with time more dynamically. Hardware complexity. To compare the hardware complexity, the three 64-channel beamformers, an 8-bit delay-sum beamformer, a conventional SDM beamformer, and a block-based SDM beamformer(proposed), are designed and synthesized on FPGA devices (Spartan, Xilinx Co., USA). In both the SDM beamformer, a 160-tap FIR filter is used for demodulation (L is 160), F n is 20[MHz], over-sampling rate M is 8, and hence K is 20. Design Specifications (a) (b) (c) o. of channels Sampling rate( ) 40[MHz] 160[MHz] 160[MHz] Bit width 8-bits 1-bits 1-bits Filter specification Purpose Interpolation Demodulation Demodulation Length Multiplier 16 (4 interpolation) Adder o. of filter 1/channel 1/64 channels K(20)/channel( K = L/ M ) Table 1 : (a) delay-sum beamformer using 8-bit ADCs, (b) a single bit dynamic focusing SDM beamformer, and (c) the proposed SDM beamformer.

6 220 Advances in ondestructive Evaluation To synthesize logic design, synplify pro ver. 7.02(Synplicity, USA) is used. And ISE 4.1i(Xilinx, USA) is used for implementation of logic design with Spartan FPGA. Table 2 shows o. of gate count which is used for implementation of each beamformer. Total equivalent AD-gate counts for design (a) (b) (c) o. Multiplier/64ch 16*64ch= *1=160 0 o. Adder/64ch 16*64= *1=160 20*64=1280 Equivalent AD-gate count for design Table 2 : (a) delay-sum beamformer using 8-bit ADCs, (b) a single bit dynamic focusing SDM beamformer, and (c) then proposed SDM beamformer In comparison with a traditional delay-sum beamformer using 8-bit 40[MHz] ADCs, the overall beamformer complexity is reduced by about 80[%] in gate counts by using the proposed scheme. In addition, because the proposed scheme is implemented with simple adders instead of multipliers, its operation speed can be increased higher than other schemes. Conclusion A block-based single bit dynamic focusing SDM beamformer is presented. The proposed scheme can completely get rid of the signal distortion in the conventional SDM beamformer by adopting block-based focusing delay scheme. The proposed architecture can also be implemented with greatly reduced hardware complexity compared to traditional multi-bit delay-sum beamformers by using the efficient realization method, in which the demodulation filters are replaced with simple acculmlators. When implement on FPGA, the hardware complexity of the proposed scheme was only 20[%] of that of the conventional 8-bit beamformer. References [1] D. Lipschutz: U.S. Patents 5,345,426(1994). [2] R. G. Pridham and R. A. Mucci: Proc. of IEEE Vol. 67-6(1979), p [3] G. R. Lockwood, J. R. Talman, and S. S. Brunke: IEEE Trans. UFFC Vol. 45-4(1998), p [4] J. T. Yen, J. P. Steinberg, and S. W. Smith: IEEE Trans. UFFC, Vol. 47-1(2000), p.93. [5] S. R. Freeman: IEEE Trans. UFFC Vol. 46-2(1999), p [6] M. A. Pervez, V. S. Henrik, and J. V. Spiegel: IEEE Sig. Proc. Magazine 1996, p. 61. [7] K. C. -H. Chao, S. adeem, W. L. Lee, and C. G. Sodini: IEEE Trans. Cir. Sys. Vol. 37-3(1990), p [8] Pai-Chi Li, Jing-Jung Huang, Hsin-Lin Liu and Matt O'Donnel: Ultra. Imag. Vol. 22-4(2000), p. 197.