ITERATIVE INTERFERENCE CANCELLATION RECEIVERS

Transcription

1 CHAPTER 2 TERATVE NTERFERENCE CANCELLATON RECEVERS Single user detectors are not optimal for CDMA because they process other user interference as unstructured channel noise. Better CDMA receivers can be designed if the specific structure of multiple access interference (MA) is fully exploited. To realize this, novel receiver structures have been proposed over the years that take advantage of the knowledge of MA1 signal parameters [ Such receivers termed as multi-user receivers are more complex than conventional ones because of their capability of using MA1 signal information to help recover the desired user. A general multi-user detector depicted in Figure 2.1, is composed of an initial correlation stage followed by a set of additional stages where a multi-user detection algorithm is implemented. t is shown by Verdu that the set of correlator outputs for each user forms a set of sufficient statistics which, if processed properly, can lead to an optimal multi-user detection. The most commonly analyzed multi-user detectors are presented in this section Optimal Detector The optimal structure shown in Figure 2.2 consists of a bank of matched filters providing first order user amplitude estimates to a Viterbi decision algorithm. Verdu [491 has shown that the optimal structure afforded significant performance improvement over the conventional structures and is insensitive to the near-far problem. The extraordinary performance enhancements however come at a price. The optimal receiver assumes apriori knowledge of the received signal amplitudes as well as delays; in practice, such ideals are usually not attainable. n addition to that the use of Viterbi decision algorithm makes the receiver complex and more burdensome.

2 f Zl 22 b + / : First stage Processing/ Correlation ---* L 1 zk b Further processing/ Multiuser detection algorithm \ J ; ; ;! - r(t) Fig. 2.1 General multi user receiver structure - f ' Correlator ' \ 21 user 1 - b, i J ', orr relator ' ' 2 b2 ' user2 b L 1 Viterbi Decision Algorithm b UserK z, + \ J ; - 4 Fig33 BPSK based optlmrl CDMA reeeiver

3 The Viterbi decision algorithm performs maximal likelihood sequence estimation over the entire sequence of received message bits, thereby decoding the whole message sequence in a trellis with 2' states. The computational complexity per bit decision then becomes exponential in the number of users, clearly rendering the optimal receiver impractical for implementation. Due to its prohibitively expensive complexity, the role of the optimal receiver has bem relegated to that of a benchmark against which sub-optimal CDMA detectors exhibiting more reasonable computational complexity are compared. Some important sub-optimal multi-user receivers are discwed here Decorrelator The Decorrelator [ is a linear multi-- detector with K' as upper bound on complexity. t functions by applying a linear transformation to the set of matched-filter outputs obtained from the first stage. As its name implies, the receiver seeks to undo the various inter-user correlations so as to isolate users from one another. This decorrelation attempt is canied out by computing PN code waveform cross correlation values and storing these in a k x k matrix, and multiplying the inverse of this matrix by the vector of matched-filter outputs from the first stage. The decorrelator does not require knowledge of signal amplitudes and is completely insensitive to the near-far effect. ts k2 complexity stems from the k x k matrix storage requirement; and while not exponential, such complexity is formidable nonetheless. This matrix is time varying as users come on and drop off of the system, thereby making updates on such a large matrix expensive. Further, this correlation matrix needs to be inverted, bringing about the issue of singularity. The decorrelator relies upon accurate PN code correlation values, and if the inverse correlation matrix becomes unstable or undefined even, then the detector ceases to function adequately. Of concern as well is a noise enhancement produced by the decorrelation operation, rendering decision statistics noisier. n general, the decorrelator provides substantial performance and capacity gains over the conventional receiver, however, it has many drawbacks and hence it is not widely used.

4 2.1.3 Mldmum Mean Square Error Detector The MMSE detector [S], like the decornlator, operates by applying a linear transformation to the set of first stage matched-filter outputs. t seeks to minimize the averaged square error between actual data and the sot? outputs from the first stage. n this case, linear transformation TR=R" used in de-cornlator is replaced by (TR=R+N~~~Y'. The performance of MMSE approaches that of de-cornlator as the noise level drops to zero i.e. No+O, but as No increases, the performance deteriorates to that of conventional receiver. At low Ed No MMSE receiver outperfoms the de- correlator while at high Ed,, the de-correlator's performance approaches to that of a MMSE receiver. MMSE receiver rectifies the decorrelator's shortcoming of enhancing noise, but at the cost of requiring knowledge of signal amplitudes. Even though near far resistance of MMSE is slightly better than that of decorrelator, both MMSE and decorrelator has the same computational complexity due to the necessity of computing the inverse of a matrix. Owing to the complexity of these suboptimal detectors researchers concentrated on the less complex linear interference cancellation receivers. 2.2 NTERFERENCE CANCELLATON RECEVERS nterference cancellation has received a great deal of attention in the literature and the premier objective of this thesis is to design a Hybrid nterference Cancellation scheme. nterference cancellation detectors seek to remove interference by actually subtracting estimates of interfering signals from the received signal. A general interference cancellation receiver is depicted in Figure 2.3. t comprises of an initial stage of matched-filters, like the other multi-user receivers, followed by stages of interference cancellation. nterference cancellation receivers typically come in two forms: parallel and successive. n parallel interference cancellation, all interfering users are cancelled (subtracted) concurrently (in parallel) from the received signal. n the successive approach proposed by Patel and Holtzman [lo], users are cancelled serially in the descending order of estimated received power, from strongest to weakest. These two interference cancellation receivers are completely analyzed in the next section based on which the hybrid interference cancellation receiver is designed.

5 Fig.2.3 BPSK based interference cancellation CDMA receiver Successive nterference Cancellation Receiver The successive interference cancellation scheme uses the algorithm shown in Figure 2.4. During every iteration of the scheme, all the user's signals are estimated. The signal with the largest power is then regenerated and subtracted from the buffered received signal. The remaining signals are now re-estimated and a new largest user is selected. The process is continued until all the users' signals have been recovered or the maximum allowable number of cancellations is reached. Successive interference cancellation is robust to imperfect power control in a CDMA system. This is because of the fact that the interference offered by the best estimated signals are eliminated hm the received waveform. Figure 2.5 is the block diagram of successive interference cancellation r='eceiver for the DS SS system. Estimating the power of the user is fairly straightforward in a coherent DS BPSK system, since the receiver is equipped with

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7 Bank of Complex Cornlaton Cancellation Regenerate Decoded Signal Fig.2.5 Block diagram of successive interference cancellation receiver The reasons for canceling the signals in descending order of signal strength are obvious. First, it is easier to acquire and perform demodulation on the strongest users i.e. the probability of making a correct decision is high. Second, the removal of strongest users offers the maximum benefit for the remaining users. Even though, the strongest user will not benefit from any MA1 reduction; the weakest user however will potentially see a huge reduction in their MA. The SC detector requires only a minimal amount of additional hardware and has the potential to provide significant improvement over the conventional detector. t does, however, pose a couple of implementation difficulties. First, one additional bit delay is required per stage of cancellation. Thus, a tradeoff must be made between the number of users that are cancelled and the amount of delay that can be tolerated. Second, there is a need to tr order the signals whenever the power profile changes. Again, a tradeoff must be made between the precision of the power ordering and the acceptable processing complexity.

8 A potential problem with the SC receiver occurs if the initial data estimates are not perfect. n this case, even if the timing, amplitude and phase estimates are perfect, if the bit estimate is mng, the interfering effect of the bit on the Signal to noise ratio is quadrupled in power (The amplitude doubles, so the powa quadruples). Thus, a certain minimum performance level of the conventional detector is required for the SC detector to yield improvements; it is crucial that the data estimates of at least the strongest users that are cancelled fust be reliable. However, the SC receiver almost provides an optimal performance and is quite reliable. The only problem with the SC receiver is that the number of iterations to cancel out all the MA1 is directly proportional to the number of wrs. Hence the computation time is quite large Parallel nterference Cancellation Receiver n contrast to the SC receiver, the Parallel interference cancellation (PC) receiver [156,157] estimates and subtracts out all of the MA1 for each user in parallel. Fig.2.6 Block dtgnm of paunllel interference cancellation receiver 25

9 The basic block diagram of a single stage PC receiver is shown in Figure 2.6. The first block is that of a matched filter bank, which is used to anive at the initial bit estimates for each user. These bits are then rescaled by the amplitude estimates and re-spread by the individual PN codes to produce an estimate of the received signals of those users. The summer sums up all the estimated signals of various users and these are in turn subtracted kom the total received signal. Hence a partially error fnc signal with less effect of MA1 is obtained. The advantage of the PC receiver is that the process of cancellation is quite fast and there is no delay incorporated at the receiver. But the problem with this type of receiver is that the receiver complexity is quite large. Also the performance of the receiver is not reliable for there is a possibility of improper cancellation. The PC receiver is faster than the SC receiver, but at the same time, is more complex than the SC receiver. Hence in order to obtain an optimal receiver performance, a trade-off between the computational time and receiver complexity is necessary [158]. This trade-off is incorporated in the proposed SNR driven Hybrid nterference Cancellation (HC) receiver, presented in the next section Hybrid nterference Cancellation Receiver SC yields better performance with lot of processing time and PC is superior to SC in terms of time delay but is inferior in terms of BER. Hence a mix of SC and PC will yield an optimal result. The main idea behind hybrid C is that instead of canceling all k users either in series or in parallel, they are cancelled partially in parallel and partially in series. The configuration for cancellation will be k-pc-s,, where k is the total number of users and the number cancelled in parallel and in series at each stage is denoted by PC and S,, respectively. The block diagram and flow chart of HC are shown in Figures 2.7 and 2.8 respectively. The signals of the first PC stronger users (out of k) are chosen to perform PC between them. As a result of this action, the PC most reliable users are chosen, their signals reconstructed and subtracted from the buffered version of the received signal. Remaining k-pc (i.e. S,) users are arranged according to their strength and one by one, Usen are detected and subtracted.

10 ncoming - signal Parallel interference cancellation stage Successive interference cancellation stage Desired user's signal Fig. 2.7 Block diagram of hybrid interference cancellation receiver Compute decision statistic (d) for all existing users 1 A T + Cancel user Fig.2.8 Flow diagram of hybrid interference cancellation receiver

11 Obviously, HC pafms in an optimal way when compared with SC and PC. Many researchers have worked on optimizing the value of P and S, but in this work choosing of P and S is done in an optimistic way. Target BER is decided depending on the type of senice offered. Based on the modulation scheme, SNR that yields the target BER is chosen as the threshold. t enables to decide whether the usa should be detected in PC mode or SC mode. i.e, those users having SNR greater than the threshold can be detected using PC since it will yield required performance through PC itself and the remaining users are detected through SC means. 2.3 TERATVE NTERFERENCE CANCELLATON RECEVERS As direct implementation of a sliding window multi-user detector is computationally complex for the given multipath CDMA channel, a low-complex multi user detector is developed based on a novel nonlinear interference suppression technique. This makes use of both soft interference cancellation and instantaneous linear minimum mean-square error filtering. The properties of such a nonlinear interference suppressor are examined, and an efficient recursive implementation is derived. Simulation results demonstrate that the proposed low complexity iterative receiver structure for interference suppression and decoding offers a superior performance over the traditional non-iterative receiver structure. Moreover, at high signal-to-noise ratio, the detrimental effects of MA1 and S1 in the channel can almost be overcome by iterative processing, and single-user performance can be approached Block diagram of a three stage C scheme 28

12 A method to improve the performance for a higher numk of users or higher values of C~OSS- orr relation is to perfom a decorrelation prior to the first iteration. An iterative cancellation consists of an nterference Cancellation (C) based h4ud followed by k single user decoders. Each constituent block itmtively provides soft information to the others. Figure 2.9 shows a typical multistage interference cancellation receiver tentive Parallel nterference Cancellation Receiver n this section, an iterative parallel interference cancellation receiver structure is proposed (Figure 2.10) for decoding multi-user information data in a multipath MC CDMA system. The receiver performs three successive soft output decisions through an iterative process. n every iteration, extrinsic information is extracted from detection and decoding stages and is then used as apriori information in the next iteration, just as in turbo decoding. -...".".-..-." "."......""... "....- Fg.2.10 Block d i m of a three stage PC scheme

13 n the first multi-user detection iteration, the upriori information of data bits is not available [159]. The C stage delivers interference cancelled soft outputs to the input of the decoders. After a fixed number of decoder iterations, the extrinsic information of coded bits at the output of decoders is fed back to the input of the C detector as the apriori information for the next receiver iteration. n every new iteration, the aprion information in the multiuser receiver becomes more reliable and hence a greater amount of interference can be cancelled. The significant part of interference cancellation is in the first iteration. t is in this perspective that many C based iterative receivers with a first linear stage have been proposed. Nevertheless, a linear multiuser detector has the drawback of an extremely high computational complexity. n this work an iterative PC receiver where most interference cancellation is done in the first receiver iterations is proposed i.e a convmtional iterative receiver tries to cancel the MA1 from all the users only once at the end of each decoding iteration. Computational complexity needed by the iterative PC to perform interference cancellation in every iteration is greater than the conventional PC. However it will be shown by simulation that the proposed iterative receiver performance is better than the conventional one even with equal complexity Proposed terative Hybrid nterference Cancellation Receiver n iterative hybrid interference cancellation the PC part of HC is made iterative. mprovements in HC can be realized by using more stages of the cancellation unit. For practical implementations a three stage iteration is found to be optimal. More stages of PC would require more computational time and increased complexity. Reasonable improvements in HC can be achieved with three stages of PC in the HC receiver. The iterative three-stage HC receiver is shown in Figure The initial stages are that of PC receivers. Users within a certain threshold are cancelled in parallel fint. The same user's signal are further estimated and cancelled three times to obtain a near m r free signal for the SC stage. t can be seen that near optimal performances are obtained with three stages of the cancellation unit. t is not advantageous to make SC iterative because it will consume a lot of time and the system will become extremely slow. All these performance improvements are achieved at the cost of computational complexity, increased hardware and time. However if performance is the criterion all these will have to be sacrificed.

14 Fig 2.11 Block diagram of a three stage HC scheme 2.4 SMULATON RESULTS A DS CDMA and MC CDMA transmitter (involving generation of data, spreading sequence and subcarriers) has been simulated using MATLAB, with QPSK modulation and 16 bit Walsh code spreaded data. A Rayleigh fading channel (with parameters so as to match practical environment) is modelled in AWGN floor. Subsequently various types of receivers are simulated as per the blocwflow diagram given in Figures 2.5,2.6,2.8,2.10 and Performance of SC, PC and HC for DS CDMA System The error performance of the HC receiver has been obtained for DS CDMA system. For comparison the SC and PC receivers have also been simulated and their enor performances obtained. To keep the simulation time practical, a processing gain of 16 has been chosen. The simulation has been carried out by assuming that there are 15 users operating simultaneously and each user transmits bits. The error ~erformance thus obtained for SC, PC and HC is shown in Figure 2.12.

15 Fig.2.12 Performance of SC, PC and HC for DS CDMA system Performance of SC, PC and HC for MC CDMA System Figures 2.13 and 2.14 show the plot between signal to noise ratio and bit error rate for a 16 bit Walsh code spreaded 5000 and 1OOO bits data of 15 users, respectively. t is observed that the conventional receiver has the highest error rate due to uncontrolled multiple access interference. The PC receiver performs better when compared to the conventional receiver, but has high error rates due to imperfect cancellation particularly as the number of user increases. Even though the computation time is large, the SC technique provides the best possible error performance. The HC receiver, as seen from the plot, nearly matches the ~elformance of the SC receiver with less computational time and it serves as a compromise between these two techniques. Figures 2.15 and 2.16 depict the plot between number of users and BER at 3 db and 6 db level respectively. t can be noted that as the number of users increase, the error rate also increases. The performance of

16 the conventional receiver and the PC receiver are poor when compared with the performance of HC, which nearly approaches to that of SC Performance of terative PC and HC for MC CDMA System Figure 2.17 highlights the performance of a three stage PC receiver with OOO bits of data, 16 bit Walsh code spreading and 15 active users. t is seen that near optimal performance (close to SC) is achieved with a three stage of the PC receiver. However its realization is difficult because of the increased hardware complexity. Hence an iterative HC (with reduced hardware complexity as compared to iterative PC) is realized which yields a significant improvement in error performance, indeed with reduced hardware complexity. Figure 2.18 shows the improvement in error performance of iterative HC receiver and Figure 2.19 depicts the comparison of error performance of various interference cancellation receivers. Fig.2.13 BER of SC, PC and HC for MC CDMA system (5000 bits)

17 Fig.2.14 BER of SC, PC and HC for MC CDMA system (1000 bits) Fig.2.15 BER variations with no. of users (1000 bits at 3 db Level)

18 Fig.2.16 BER variations with no. of users (1000 bits at 6 db level) Fig.2.17 BER of iterative PC receiver 35

19 Fig.2.18 BER of iterative HC receiver Fig.2.19 Performance comparison of C receivers 36

20 2.4.4 Complexity Analysis Figure 2.20 brings out the computational complexity of the SC receiver and the HC receiver. The number of correlations required in SC increases exponentially as the number of users increase. n case of HC, the number of correlations required is much less compared to SC. The number of iterations for SC is k fork users whereas the number of iterations for hybrid system will vary and depend on channel conditions. The number of signal cancellations is k-1 for SC while it is reduced to k-x in a HC scheme, where X-l are the number of users cancelled in a SC scheme and in one iteration the remaining users are cancelled. This accounts for the greatest reduction in computational complexity in a HC scheme and the computational complexity works out to k2/2 for the successive scheme while it is reduced to the extent of (k-~)'/2 in case of HC where X is almost W2 in most cases. Figure 2.21 shows the hardware complexity of SC, PC and HC receiver. b.dm Fig.2.20 Comparison of computational complexity

21 Fig.2.21 Hardware complexity of HC, PC and SC scheme 2.5 CONCLUSON n this chapter, a DS CDMA and MC CDMA systems have been simulated. Hybrid interference cancellation receiver has been designed and the performance of the receiver obtained using simulations. The performance of the proposed receiver has been compared with the other interference cancellation receivers. From the results obtained, it is concluded that, the performance of the hybrid interference cancellation receiver matches the successive interference cancellation scheme with much lesser number of correlations and hence with less computational time. But the hardware complexity of the HC receiver is greater than that of the SC receiver and lesser than that of the PC receiver. Hence a perfect trade off between the computation time and receiver hardware complexity is achieved. Lmprovements in the performance of hybrid scheme have been obtained based on iterative schemes. This scheme has resulted in considerable improvements of the HC receiver. Through simulation it is identified that capacity of the MC CDMA system improves by around 20% due to the Proposed interference cancellation receivers.