Test Results for MOSIS Educational Program

Transcription

1 Test Results for MOSIS Educational Program (Research) A Circuit-Based Approach for the Compensation of Self-Heating- Induced Timing Errors in Bipolar Comparators Prepared by: Institution: Design Name: Kyle Webb Professor T. S. Kalkur University of Colorado at Colorado Springs Department of Electrical and Computer Engineering 1420 Austin Bluffs Parkway Colorado Springs, CO Lagarto Project Number: Process: Fab ID: IBM8HP 7LM V2BFAH Submission Date: August 10, 2013

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3 I. Introduction Comparator circuits fabricated in bipolar and BiCMOS processes, particularly those utilizing trench isolation, are highly susceptible to the effects of self-heating. Trench isolation exacerbates self-heating effects by providing a high degree of thermal isolation between transistors on a chip, which may result in significant differential self-heating between nominally-matched devices even for closely-spaced transistors. In bipolar comparator circuits, self-heating manifests itself as errors in the timing relationship between the input threshold crossing and the output switching instant, which can be a significant issue for comparators used in applications were precise timing is critical. The reduction of self-heating effects in clocked comparators used in sampled comparator systems has been addressed in [1] and [2]. This project, Lagarto, comprises the design of a circuit-based self-heating compensation scheme for use with comparators operating in asynchronous applications, where precise transition timing information is sought. A differential bipolar comparator circuit has been designed and fabricated in IBM s BiCMOS 8HP SiGe process through the MOSIS Educational Research Program. This comparator circuit includes circuitry to compensate for the timing errors that result due to self-heating of the comparator s transistors. The test chips have been packaged in 52-pin QFN packages, and mounted on a custom test board for characterization. This report details the results from the testing of this chip A. Self-Heating and Self-Heating Compensation in Differential Pairs The primary self-heating effect in a differential pair amplifier, a fundamental building block of many high-bandwidth comparators, is the temperature-dependent modulation of the transistors base-emitter voltages. The device models provided for many high-bandwidth bipolar and BiCMOS processes, including the IBM8HP process, account for self-heating effects by relating local device temperature variation to power dissipation through a low-order transistor thermal network as described in [3] and [4]. Conceptually, it is instructive to model the temperature dependence of the base-emitter voltage as an input-referred offset voltage, as shown in Figure 1. The self-heating offset voltage, v sh, is determined by the local device temperature rise, ΔT, scaled by a thermal gain constant, A th, where ΔT is given by the product of the transistor s power dissipation, P, and the impedance of its thermal network. The result is a signal-dependent offset voltage, with a bandwidth equal to the thermal bandwidth of the transistors typically in the range of tens to hundreds of kilohertz. For IBM8HP the modeled thermal bandwidth is 159 khz. Self-heating effects manifest themselves in linear differential pair amplifiers as slow thermal tails, and in digital differential pairs as signal-dependent propagation delay variation. At the digital output of a comparator, self-heating appears as signal-dependent variation of the switching instant, similar to intersymbol interference (ISI) or duty-cycle distortion (DCD). In applications where comparators are used to precisely measure the timing of input threshold crossings (e.g., oscilloscope trigger comparators), signaldependent timing variation at the output poses a significant problem that must be addressed. 1

4 Figure 1. Differential pair amplifier including self-heating-induced offset voltages. Because the effects of differential self-heating can be modeled as a signal-dependent input-referred offset voltage, these effects can be eliminated by generating and feeding back a compensating signal to cancel that offset voltage. A circuit for generating such a compensation signal is shown in Figure 2. A signal proportional to the differential power dissipation of the amplifier transistors, v PTP, is applied to the collectors of Q 1 and Q 2, thereby modulating their power proportionally to that of the amplifier transistors. Transistors Q 1 and Q 2 experience a base-emitter voltage modulation proportional to that of the amplifier transistors and therefore proportional to the self-heating offset voltage of the amplifier. This thermal voltage, v th, appearing between the emitters of Q 1 and Q 2 is amplified with a variable-gain amplifier, whose gain is calibrated to provide optimal compensation, and fed back to the differential pair input, canceling the self-heating offset voltage. Figure 2. Thermal voltage generation circuit. Differential emitter voltage, v th, is amplified, and the resultant signal is fed back to cancel the amplifier s self-heating offset voltage. 2

5 The geometry of the thermal voltage generator transistors is set equal to that of the amplifier transistors, in an effort to match their thermal bandwidths, and thereby match the bandwidth of the compensation signal to that of the self-heating offset voltage. The thermal voltage generator circuit requires an input signal that is proportional to the differential power dissipation of the amplifier transistors. For digital amplifiers, or for linear amplifiers with constant input common-mode voltage, the differential amplifier output voltage can serve as that proportional-topower (PTP) signal. For differential pairs in mixed-signal circuits (e.g., comparators), whose operating regime may be input-signal-dependent, or for linear differential pairs with varying input common-mode voltage, the amplifier output voltage does not provide a PTP signal over all input conditions. For such circuits, optimal compensation requires the generation of a true PTP signal. B. Proportional-to-Power Signal Generation The differential PTP signal used in the Lagarto comparator circuit is generated by a power-to-voltage converter (PVC), which comprises two cross-coupled multiplier blocks. Each multiplier calculates the power dissipation of a single transistor by monitoring its collector current and collector-emitter voltage as shown in Figure 3. Collector-emitter voltage is monitored directly, and collector current is monitored by dedicating portions of the amplifier s load resistors as current sense resistors. Cross-coupling the two multiplier outputs provides a PVC output signal that is proportional to the differential power dissipation of the amplifier transistors. The PVC output signal is applied to the input of the thermal voltage generator circuit of Figure 2, producing the self-heating compensation signal to be fed back to the input of the differential pair amplifier. Figure 3. The power-to-voltage converter (PVC) block generates the PTP input for the thermal voltage generator II. Lagarto Project Description The Lagarto project is a differential comparator chip fabricated in the IBM8HP process. A top-level block diagram of the chip is shown in Figure 4. The chip comprises 50Ω input and output amplifiers, both of which were designed to be inherently immune to the effects of self-heating, along with a comparator core. The comparator core is made up of four cascaded differential pair amplifiers, each of which is 3

6 individually compensated for the effects of self-heating. The comparator circuit also includes adjustable hysteresis. Figure 4. Top-level block diagram of the Lagarto comparator IC. A. Input amplifier Each of the two inputs to the comparator go into a 50Ω common-base input amplifier, as shown in Figure 5 and Figure 6. Included in the input amplifier circuit, Figure 5, is circuitry to allow for the nulling of any mismatch-induced offset voltage in the comparator path over a range of ±20mV. (The calibration procedure will be described later in this report.) The differential input signal to the chip should have a common-mode voltage of ~700mV. Figure 5. Top-level schematic of the 50Ω input amplifier, including the offset voltage nulling block. Figure 6. Common-base input amplifier schematic. 4

7 B. Output amplifier The emitter-follower output amplifiers are shown in Figure 7. These amplifiers are designed to drive load-terminated 50Ω lines. The 1.9kΩ resistor between the emitters of the first pair of emitter followers provides self-heating compensation for these transistors, which simulation indicates is effective over process variation. The 130Ω resistors in the collectors of the output transistors provide power-balancing and self-heating compensation for the output transistors. This compensation was seen in simulation to be slightly susceptible to process variation, so an adjustable positive supply, VCCout, was provided for these devices. A dummy output amplifier, whose inputs and outputs are pinned-out from the chip, was included for the calibration of this supply voltage. Figure 7. Emitter-follower output amplifier schematic. C. Comparator Core The core of the comparator chip is illustrated at a block-diagram level in Figure 4, and a schematic of this circuit is shown in Figure 8. The comparator circuit consists of four cascaded gain stages, each with its own self-heating compensation circuitry. An additional diff pair circuit provides hysteresis that is adjustable over a range of 0V 75mV. The self-heating compensation blocks, ShComp in Figure 8, share bias current with the diff pair transistors to conserve power. Input signals for these blocks are picked off from the comparator gain stages. These signals are used in the ShComp blocks to generate a proportional-to-differential-power signal for the amplifier s transistors. The compensation signal generated by the compensation block is a differential current that is fed back to the load resistors preceding the diff pair being compensated. Load resistors are broken into two segments, with the voltage drop across the 20Ω segment used as a measure of the collector current in the corresponding transistor. The compensating feedback current is injected into the intermediate node, so as not to affect the collector-current-sense voltage. The gain of 5

8 each compensation block is individually-programmable, and each gain-setting voltage, VtGain, is pinned out from the chip. However, simulation indicated that it is sufficient to program all gains equally, even when accounting for variations due to mismatch. When testing the chip all VtGain signals were adjusted together with a single voltage. Figure 8. Schematic of the comparator core. Note that the circuit includes four gain stages; the third differential pair gain stage has been excluded from this schematic for clarity. Note that the load resistors for the input amplifiers connect to their own adjustable supply, VCCin. This provides a way to vary the common-mode voltage at the input to the comparator, in order to assess the effectiveness of the self-heating compensation over a range of input common-mode levels. D. Self-Heating Compensation Block The self-heating compensation circuit, ShComp, is shown in Figure 9. This circuit consists of three main functional blocks: a power-to-voltage converter (PVC), the thermal voltage generation transistors, and a variable-gain transconductance amplifier. The PVC block uses signals from the diff pair amplifier to generate a differential signal that is proportional to the differential power dissipation of the diff pair transistors. This proportional-to-power signal is applied to the collectors of the thermal voltage generation transistors, Q 1 and Q 2, modulating their power dissipation proportionally to that of the diff pair transistors. The thermal voltage picked off from between the emitters of Q1 and Q2 is amplified, converted to a current, and fed back to the input of the diff pair amplifier. 6

9 Figure 9. The Self-heating compensation block, ShComp. E. Power-to-Voltage Converter (PVC) The PVC block comprises two cross-coupled four-quadrant multiplier circuits, as depicted by the block diagram of Figure 3, followed by a fixed-gain amplifier circuit. The top-level PVC schematic is shown in Figure 10. Each of the multiplier cells generates a signal that is proportional to the power dissipation of a single transistor in the diff pair being compensated. Cross-coupling their outputs yields a signal that is proportional to the transistors differential power dissipation. Figure 10. Top-level schematic of the PVC circuit. The schematic for the four-quadrant multiplier circuit, PVCmult, is shown in Figure 11. The CAL input is a digital control signal that, when high, forces the differential output of the PVC block to zero during calibration. The output signal from two cross-coupled PVCmult cells is amplified, and then applied to the thermal voltage generation transistors shown in Figure 9. 7

10 Figure 11. The four-quadrant multiplier circuit of the PVC block, PVCmult. F. Variable-Gain Transconductance Amplifier The thermal voltage generated by the circuit of Figure 9 is amplified and converted to a current by a variable-gain transconductance amplifier, VthermVTA, whose top-level schematic is shown in Figure 12. The first stage in the VthermVTA block is simply a voltage amplifier with a fixed gain of 28dB. The second stage is a transconductance stage, comprising both a fixed transconductance amplifier and a variable transconductance amplifier, as shown in Figure 13. The amplifier has two differential outputs, as shown in Figure 12 and Figure 13: the compensation current, i comp, that gets fed back to the diff pair input, and a voltage output, V cal, that is used during the calibration procedure. The calibration voltage signal is generated by steering the feedback compensation current to a different pair of 80Ω resistors instead of those at the diff pair input. The schematic for the circuit that provides variable transconductance, as well as steering of the compensation current for calibration, VthermVTAgmVariable, is shown in Figure 14. Figure 12. Top-level schematic of the variable-gain transconductance amplifier. 8

11 Figure 13. Top-level schematic of the variable portion of the variable transconductance amplifier. Figure 14. VthermVTAgmVariable circuit schematic. This circuit provides variable transconductance gain and also redirects the compensation current for generation of the calibration voltage. The overall gain of the transconductance amplifier is adjustable over the range of 46mS 100mS. G. Calibration Procedure The voltage generated by the thermal voltage generation transistors is on the order of several millivolts at full scale, so there is a significant amount of gain in the transconductance amplifier that amplifies it. The compensation signal path is therefore very susceptible to mismatch-induced offset voltages, necessitating a procedure to null out any such offsets. A digital input to the chip, CAL, puts the circuit into calibration mode, which zeros out the PVC output and steers the compensation current to the 9

12 resistors shown in Figure 13, thereby generating the V cal <i> outputs. Each of the four self-heating compensation blocks on chip includes circuitry, controlled by an external analog input voltage to allow for the nulling of the offset that appears at its respective V cal <i> output when in calibration mode. This nulling voltage, VthermOffNull<i>, applies an offset to the bias voltage of the two thermal voltage generation transistors (Figure 9) in the corresponding self-heating compensation block. The first step in the calibration routine is to adjust each VthermOffNull<i> voltage to null the voltage appearing at the corresponding V cal <i> output. Following the nulling of each ShComp block s offset voltage, the chip is taken out of calibration mode and any offset in the comparator signal path is nulled using the input offset nulling circuit, shown in Figure 5. This offset nulling block is also controlled by an external analog voltage, VinOffNull, which controls the injection of a differential offset current at the output of the input amplifiers. This control voltage, VinOffNull, is adjusted to balance the comparator output. After all offsets have been nulled, the gain of the variable-gain transconductance amplifiers can be calibrated. These gains are controlled by externally-generated analog control voltage inputs, VtGain<i>. While the gain of each of the four amplifiers is individually-programmable, they have all been set to the same values, using a single control voltage. This portion of the calibration procedure involves adjusting VtGain to optimize the self-heating compensation. The method used to assess the effectiveness of the compensation is described in the following section. III. Test Procedure A. Duty-Cycle Distortion (DCD) Self-heating of the differential pair transistors in the comparator causes signal-dependent offset voltages, which result in signal-dependent variation of the timing relationship between the switching instants of differential input and output signals. In other words, the result of self-heating is that the propagation delay through the comparator is signal-dependent. In applications where comparators are used to provide precise timing information about the switching time of a signal, self-heating will therefore be a source of error. The magnitude of this error, as well as the effectiveness of any attempt to compensate for this self-heating-induced error, can be evaluated by measuring the comparator s duty-cycle distortion (DCD). The amount of DCD observed, is dependent on the signal applied to the comparator. To determine the worst-case DCD, the input signal shown in Figure 15 is used. The comparator is first subjected to a thermal soaking period, in which the input signal is held low for a long time (many thermal time constants). This allows the comparator to reach a worst-case state of differential self-heating. 10

13 Figure 15. Test input signal used to generate worst-case self-heating and worst-case DCD. Following the thermal soaking period, the input signal begins switching at a frequency well above the thermal bandwidth of the circuit (50 MHz was used here), and continues to do so for a long time (again, many thermal time constants). During this switching period the comparator circuit approaches a state of thermal equilibrium. The rate at which thermal equilibrium is approached is dictated by the thermal time constants of the transistors in the circuit. Once thermal equilibrium had been reached, a second soaking period of opposite polarity can be applied, followed by another period of continuous switching. In this work, DCD has been measured as the difference between output and input pulse widths and has been calculated pulse-by-pulse for each positive and negative pulse at the input and output, as depicted in Figure 16. Figure 16. Pulse-by-pulse calculation of DCD. Because the differential self-heating is at its worst following the thermal soaking periods, the input-tooutput pulse width error and the DCD are at their maximum values at this point as well. As the input signal continues to switch, and the circuit approaches thermal equilibrium, the measured DCD decays toward zero. A negative error for positive pulses corresponds to a positive error for negative pulses and vice versa, so the polarity of the measured DCD values will oscillate as the magnitude decays. B. Test Setup The test setup used for the evaluation of the Lagarto comparator chip is depicted by the block diagram of Figure 17. The input signal was supplied by an Agilent 8131A pulse generator with differential outputs and 160psec risetime. The pulse generator s output was gated by a low frequency (10Hz) square wave from a function generator, providing the thermal soaking period depicted in Figure 15. The input and 11

14 output signals were measured with an Agilent DSO91304A 13GHz, 40GSa/sec oscilloscope. The input signal was probed on the test board with an N5381A 12GHz differential solder-in probe head connected to an 1169A 12GHz probe amplifier. The comparator outputs were cabled directly to the scope. A photograph of the test setup is shown Figure 18, and a photo of the test board is shown in Figure 19. Figure 17. Block diagram of the setup used for testing the Lagarto chip. Figure 18. Measurement setup used for characterization of the Lagarto test chip. Input and output signals were acquired on the scope at 40GSa/sec over a period of 10µsec, while triggering on the first input edge following a thermal soaking period and averaging over 256 acquisitions. Waveform data was exported to MATLAB for DCD calculation and analysis. Measurement results are presented in the following two sections. 12

15 Figure 19. The Lagarto test board. IV. Initial Test Results and Comparison with Simulation A. Uncompensated DCD Measured DCD for the comparator with the compensation circuitry disabled is shown in Figure 20. The plot shows the characteristic polarity oscillation as well as the exponential decay toward zero as the chip approaches thermal equilibrium. The maximum DCD value in this case is approximately 13.5psec. Figure 20. Measured DCD for the uncompensated comparator, i.e. compensation ciruitry disabled. 13

16 The envelope of the DCD plot in Figure 20 provides insight into the thermal behavior of the transistors on the chip. The design kit model for 8HP transistors sets the thermal time constant to 1µsec. Fitting a curve to the envelope of the DCD decay, as is done in Figure 21, shows that for these particular transistors a dual-time-constant model with time constants of τ th1 = 59nsec and τ th2 = 330μsec provides a good fit. Figure 21. Determining thermal time constants by fitting a sum of exponentials to the DCD envelope. Figure 22 compares the maximum measured and simulated DCD values for a range of input signal swings and common-mode voltages. The reasonably good agreement between measurement and simulation indicates similar agreement between the modeled and actual thermal resistances of the diff pair transistors. 14

17 Figure 22. Comparison of simulated and measured DCD for the uncompensated comparator over a range of input signal swings and common-mode voltages. B. Compensated DCD The variable-gain transconductance amplifiers in each compensation path were designed to have more than enough adjustable gain range to accommodate any potential process variation. However, initial DCD measurements showed that, even with VtGain at its minimum setting, the compensation path gain was too high. Figure 23 compares measured DCD from the uncompensated comparator with both measured and simulated DCD for the compensated comparator. The opposite polarity of the measured DCD values for the uncompensated and compensated cases indicates that, even at the minimum gain setting, the circuit is over-compensated. Measurements of the DC transfer characteristic between the VthermOffNull<i> inputs and the corresponding Vcal<i> outputs indicated that the gain range of the variable-transconductance amplifiers was as designed for. The other two gain components in the compensation path are the PVC and the thermal voltage generation transistors. While the gain of the PVC is not directly observable, all other observable amplifiers on the chip had gains within the expected range, giving no reason to believe that the PVC gain was significantly higher than intended. 15

18 Figure 23. Comparison of measured DCD for the uncompensated and compensated cases, along with the DCD predicted by simulation for the compensated comparator. It is suspected that excessively-high compensation path gain can be attributed to a thermal gain mismatch (i.e. a thermal resistance mismatch) between the diff pair transistors and the thermal-voltagegeneration transistors. The over-compensation observed in Figure 23 indicates that the thermal resistance of the thermal-voltage-generation transistors is higher than that of the diff pair transistors. To test this hypothesis, simulations were run in which the thermal-voltage-generation transistors were assigned a modified transistor model in which the thermal resistance had been increased. It was found that a 40% increase in thermal resistance for the thermal-voltage-generation transistors did a reasonably good job of explaining the measured DCD values, as is illustrated by the plot of Figure 24. It is suspected that, while the geometries of the diff pair and thermal-voltage-generation transistors are identical, a thermal resistance mismatch could easily be explained by different layout configurations, and, in particular, the different metal-layer connections of the different transistors. The primary difference between the two sets of transistors is the fact that the emitters of the diff pair transistors are directly connected on the metal layers, which could certainly result in a lower relative differential thermal resistance between the devices. A study of the impact of layout and wiring on the thermal characteristics of the transistors is beyond the scope of this work, though measurements here seem to indicate that significant variation in thermal behavior between identical devices used in different circuit configurations can be expected. If the above hypothesis is correct, it can also be expected that, along with thermal resistance, thermal bandwidth will differ between the two different pairs of transistors as well. The result of a thermal bandwidth discrepancy would be a mismatch between the bandwidth of the compensation signal and 16

19 the self-heating offset voltage it is meant to compensate, which would prevent optimal self-heating compensation. Figure 24. Disagreement between measured and simulated DCD values for the compensated case explained by a simulation in which the thermal resistance of the thermal-voltage-generation transistors is increased by 40% relative to the diff pair transistors. V. Test Results Following Reduction of Compensation-Path Gain A compensation circuitry disable control input DIS was provided in order to be able to completely disable the self-heating compensation circuitry. This bit controls a CMOS switch that, when DIS = 1, disconnects the current source bias voltage from the variable-transconductance amplifier, effectively powering that amplifier down entirely. This switch is illustrated in Figure 25. Figure 25. Disable switch for the amplifier current sources in the compensation path. By varying the DIS signal between its logic low and high levels it was possible to pull the bias voltage partially toward the negative supply, reducing the bias of the amplifier gain stages, thereby reducing the 17

20 compensation path gain to an appropriate level. DCD measurements were then taken at this reducedgain setting, and are summarized in the following figures. Figure 26 shows an example of measured DCD values for both the compensated and uncompensated cases at one set of input signal parameters. DCD results over a range of input signal parameters are summarized in the plot of Figure 27. It can be seen that the compensation circuitry is effective at significantly reducing self-heating-induced timing errors, and maintaining effective compensation over a range of range of input common-mode voltages. Note that DCD is plotted on a logarithmic scale in Figure 27. Figure 26. Comparison of the measured DCD for the uncompensated and compensated comparators for one set of input swing and common-mode conditions. Figure 27. Summary of maximum measured DCD values over a range of input signal swings and common-mode levels. 18

21 The increase in measured DCD at 500mV pp input swing shown in Figure 27 can be explained by the fact that the compensation path gain was calibrated for a 200mV pp input, combined with some non-linearity of the PVC and compensation path amplifiers. Another illustrative way to view the effectiveness of the compensation circuitry is to generate an eyediagram plot of the comparator output signal, using the input signal as a clock or timing reference. An example of such a plot is shown in Figure 28. The input signal conditions corresponding to this eye diagram are the same as those used to generate the plot of Figure 26. The width of the traces at the zero-crossings in Figure 28 corresponds to the maximum DCD value shown on the plots of Figure 26, in this case, approximately 38psec for the uncompensated case and 5.5psec for the compensated case. Figure 28. Eye diagram comparing the timing variation of the compensated vs. uncompensated comparators for the same input conditions as the DCD plot of Figure 26. In this case, the compensation circuitry reduces the maximum DCD from 38psec to 5.5 psec. VI. Conclusion A circuit-based self-heating compensation scheme for a bipolar comparator has been implemented on an IBM8HP integrated circuit. The compensation scheme was demonstrated to be effective at significantly reducing self-heating-induced timing errors over a range of input signal conditions. An excess of gain in the self-heating compensation paths on this comparator chip was observed. It is believed that this excess gain was due to a significant discrepancy between thermal resistances of the diff pair transistors and the thermal-voltage-generation transistors, which can likely be explained by the different circuit topologies, along with the associated layouts, in which these transistors are used. This is an important finding for IC designers who need to accurately model and design for transistor selfheating. 19

22 References [1] Bergman, D. I., & Waltrip, B. C. (2004). A Low Thermal Error Sampling Comparator for Accurate Settling Measurements. IEEE Int. Symp. on Circuits and Systems (pp ). Vancouver, B.C.: IEEE. [2] Laug, O. B., Souders, T. M., & Flach, D. R. (1992, Dec.). A Custom Integrated Circuit Comparator for High-Performance Sampling Applications. IEEE Trans. on Instrum. Meas., 41, [3] Munro, P., & Ye, F.-Q. (1991, Sept.). Simulating the Current Mirror with a Self-Heating BJT Model. J. Solid-State Circuits, 26(9), [4] Voglesong, R. S., & Brzezinski, C. ( May 1989). Extending Spice for Electro-Thermal Simulation. Proc. IEEE Custom Integrated Circuits Conf., (pp ). [5] Webb, K. M.; Kalkur, T. S., "A circuit-based approach for the compensation of self-heating-induced timing errors in bipolar comparators," Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), 2012 IEEE, vol., no., pp.1,4, Sept Oct