Maximum Power Point Tracking Techniques for Efficient Photovoltaic Microsatellite Power Supply System

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1 SSC1-III-1 Mximum Powe Point Tcking Techniques fo Efficient Photovoltic Micostellite Powe Supply System Hdi Mlek S Dds, YngQun Chen ECE Dept. of Uth Stte Univesity, Logn, Uth; Robet But, Jmes Cook Spce Dynmics Lbotoy 1695 N. Resech Pkwy, th Logn, Uth; ABSTRACT Due to limited powe vilbility nd constints imposed on stellite mss, volume, nd vilble e fo photovoltic (PV) pnels, high powe convesion efficiency is n impotnt gol in the design pocess of n electicl powe souce fo micostellites. In this esech, we model, design, nd build photovoltic bsed Electicl Powe System (EPS) fo stellite to ensue the supply of mximum powe nd stble opetion. This ppe pesents the esults of ou MPPT (mximum powe point tcking) esech. We descibe the EPS powe system boundy equiements used in ou esech. We lso descibe the design constints used in ou esech tht e typicl to the micostellite clss missions such s extemely low powe equiements, limited volume, nd miniml, fixed point, pocessing cpbilities. We descibe ou implementtion ppoch bsed on poposed lgoithms such s Intege Ode Extemum Seeking Contol (IO-ESC), nd Fctionl Ode Extemum Seeking Contol (FO-ESC). Compison esults fo the diffeent lgoithms e pesented s implemented in both the model nd on the ctul hdwe. These new MPPT techniques offe highe convesion efficiency eltive to the Petub & Obseve (PO) nd othe techniques conventionlly used in stellite powe supply systems. INTRODUCTION AND HISTORY Thee hs been ecent incese in emphsis on nnostellites becuse of thei low cost, shot development times, eltive simplicity, nd cost efficiency. Howeve, these smll stellites do hve dwbcks. The smll size of nnostellites esults in vey little sufce e which often tnsltes into theml nd powe constints. These smll stellites often do not hve enough sufce e fo tditionl sol pnels. Fo nnostellites, it is desible to use high efficiency sol powe systems to mximize the powe output fom the vey limited vilble e. The system includes the sol cell, the bttey, nd the powe mngement nd distibution (PMAD). Both SDL nd the Cente fo Self-Ognizing nd Intelligent Systems (CSOIS) fom the ECE deptment of Uth Stte Univesity begn to independently develop MPPT lgoithms nd pplictions. USU s pimy focus hs been t the lgoithm level with stong focus on theoy nd simultion. SDL s pimy focus hs been on nnost implementtion, using the bsic P&O lgoithm. The gol ws to build n EPS fo the PEARL spcecft. In 11, SDL nd USU combined effots to my the lgoithm esech with the hdwe development t SDL. In 1, SDL begn eseching MPPT lgoithms fo use in FPGA bsed designs. SDL looked t Petub nd Obseve, Incementl conductnce, nd voltge monitoing methods. The P&O lgoithm ws initilly selected due to its simplicity. Once SDL nd USU temed, USU suggested using n Extemum Seeking Contol lgoithm s potentil cndidte fo flight pplictions. Two specific vesions of the ESC wee consideed nd the intege ode vesion ws selected fo the fist instntition on the EPS contolle. The pocess of coding the lgoithm nd implementing them in fimwe is somewht time consuming, so the ppoch ws to implement both the P&O lgoithm nd the Intege Ode ESC (IO-ESC) lgoithm into the fimwe. In ddition to the EPS contol hdwe, USU possesses hose powe dynmomete used to test contol lgoithms in el wold envionment. The dynmomete is compute Mlek 1 6 th Annul AIAA/USU Confeence on Smll Stellites

2 contolled such tht lgoithms cn quickly be implemented nd tested vi softwe. The dynmomete ws used to compe the IO-ESC lgoithm nd Fctionl Ode ESC (FO-ESC) lgoithm. The PEARL EPS contolle ws used to compe the P&O nd the IO-ESC lgoithms. Pio to the ctul hdwe testing nd compisons, ech lgoithm ws simulted using MtLb to povide bseline design nd enble extpoltions fo finl esult, not edily chievble in hdwe implementtions. The esech pesented in this ppe discusses multiple lgoithms. The est of this ppe is ognized s follows: In Section II, the photovoltic chcteistics of the sol y e pesented. Section III-V, intoduces, nd discusses the diffeent lgoithms used in the esech. Section VI pesents simultion esult fo the two extemum seeking lgoithms. Sections VII IX e the expeimentl esults nd conclusions. PV CHARACTERISTICS Since PV pnels exhibit non-line Powe-Voltge chcteistic, thei powe output minly depends on the ntue of the connected lod. Beside this nonlineity, the mximum powe of the PV pnel vies by vying envionmentl condition like idition nd tempetue (Figue 1). Mximizing the powe, which is essentil, cn be chieved by eplcing the diect connected PV systems by PV systems hving n intemedite mximum powe point tcke (Figue ). Mny mximum powe point tcking techniques fo photovoltic systems hve been developed to mximize the enegy output nd lots of these e well estblished in the litetues: Open-Cicuit Voltge (OV), Shot- Cicuit Cuent (SC), Fuzzy Logic Contol, Ripple Coeltion Contol (RCC), Cuent Sweep (SC), Petub nd Obseve (P&O) nd etc. 1, These techniques vy in mny spects s: simplicity, convegence speed, digitl o nlogicl implementtion, sensos equied, cost, nd etc. Cuently, the most popul MPPT lgoithm is petub nd obseve (P&O) method, becuse of its blnce between pefomnce nd simplicity. Although this lgoithm benefits fom simplicity, it lcks the speed nd dptbility necessy fo tcking fst tnsients in wethe. A pomising new obust MPPT lgoithm is Extemum Seeking Contol (ESC), which is closely elted to the ipple coeltion contol (RRC) nd P&O methods. It tkes dvntge of the P&O method simplicity nd the obustness nd convegence speed of RRC method. Figue 1- nline behvio of sol ys The ESC method of Kstic 3 offes fst convegence nd good stedy-stte pefomnce with gunteed stbility fo nge of pmetes. Fo the fist time, in this ppe, we will pesent the fixed point implementtion of the intege ode ESC lgoithm. We will lso intoduce fctionl ode ESC contol. Figue -Genel Scheme of Sol Ay with MPPT Mlek 6 th Annul AIAA/USU Confeence on Smll Stellites

3 PERTURB & OBSERVE WITH BATTERY MANAGEMENT The petub nd obseve lgoithm, Figue 3, uses tditionl ppoch of ditheing ound the pek powe point. The sol y input voltge nd cuent is smpled. The cuent powe vlue is comped to the pevious powe vlue. A contol step vlue is then commnded bsed on the powe compison esults nd which side of the powe mximum we e on. The pek powe is mintined by epeting this pocess t the coect fequency to mtch the hdwe dynmics. In ddition to the pek powe tcking cpbility, this implementtion dds multiple step sizes to incese the esponse speed when conditions ou out of bounds of typicl sol y bounds. The lgoithm is lso implemented with bttey mngement contolle since the ultimte end item use is fo spcecft electicl powe systems. This lgoithm benefits fom knowing specifics bout the sol y being ttched, such s the y size, nd configution. Using this infomtion helps limit the numbe pemetions possible with evey dt smple nd limits the cses whee the lgoithm cn be confused. This fetue limits the univesl ppliction of the specific implementtion but since only few numbe of vlues e custom fo ech implementtion they e esily mde pogmmble nd cn be uploded nd modified s necessy. ΔVSAx_V > Eo ΔVSAx_V < -Eo VCTRLx = volts VCTRLx = VCTRLx - Delt Stoe new (k-1) Sttup VCTRLx = x ΔVSAx_V = VSAx_V(k) VSAx_V(k-1) ΔVSAx_P = VSAx_P(k) VSAx_P(k-1) VCTRLx = VCTRLx - Delt Stoe new (k-1) VCTRLx = VCTRLx + Delt1 Stoe new (k-1) VCTRLx = VCTRLx Delt1 Stoe new (k-1) VSAx_I < 5mA Vbt_V > Limit Vbt_I > Limit VSAx_V < 1.5V ΔVSAx_P > Eo1 ΔVSAx_P < -Eo1 VCTRLx = VCTRLx Delt1 Stoe new (k-1) Light on Ay Limit Bttey Voltge by educing lod on y Limit Bttey Cuent by educing lod on y Ay Voltge hs Collpsed VCTRLx = VCTRLx + Delt Stoe new (k-1) ΔVSAx_V > Eo ΔVSAx_V < -Eo VCTRLx = VCTRLx Delt1 Stoe new (k-1) Figue 3-Petub & Obseve Algoithm Flow Digm INTEGER ORDER EXTREMUM SEEKING CONTROL To mximize the PV y powe output, we employ n Intege Ode Extemum Seeking (IOES) scheme 3,5 fo sttic nonline mps, shown in Figue 4. The contol scheme pplies peiodic petubtion sin( t) to the duty tio signl ˆd, which is the cuent estimte of the optimum duty tio d. Assuming the boost DC/DC convete dynmics cn be ppoximted s instntneous 6, the sinusoidl vying duty tio imposes sinusoidl vying input voltge. This voltge psses though the sttic nonlineity f ( dˆ sin( t)), epesenting the PV y s P-V chcteistic cuve, to poduce peiodic powe output p. The high-pss filte s/ ( s h ) then elimintes the DC component of p, nd will be in phse o out of phse with the petubtion signl sin( t) if ˆd is less thn o gete thn d, espectively. This popety is impotnt, becuse when the signl η is multiplied by Mlek 3 6 th Annul AIAA/USU Confeence on Smll Stellites

4 the petubtion signl sin( t), the esulting signl hs DC component tht is gete thn o less thn zeo if ˆd is less thn o gete thn d, espectively. This DC component is then extcted by the low-pss filte / ( s ). Theefoe, the signl cn be l l f thought of s the sensitivity ( ˆ / ) ( d) d nd we my use the gdient updte ˆ f d k( ˆ / ) ( d) d to foce ˆd to convege to d nd contol gol is chieved. contol voltge between the fixed steps thus llowing the ESC lgoithm to incese the efficiencies. The ESC lgoithm implementtion ppoch ws to model the lgoithm in Mtlb / Simulink envionment using floting point mth to vlidte the lgoithm. A second ESC Mtlb / Simulink lgoithm ws ceted using fixed point mth which includes biny ddes, subtctos, multiplies nd divides. The divides e simplified using shift egistes s divide by ^N. The FPGA ESC lgoithm ws consideed completed once the pefomnce of the fixed point nd floting point model outputs mtched. FRACTIONAL ORDER EXTREMUM SEEKING CONTROL In this section, we fist pesent the Fctionl Ode Extemum Seeking Contol (FO-ESC) scheme nd then the stbility of this method is investigted. Figue 4-Block digm of poposed intege ode extemum seeking contol system [1] Fixed Point Extemum Seeking Contol implementtion Implementing the fixed point ESC lgoithm in n FPGA ws vey chllenging due to the chitectue limittions of the FPGA nd suounding subsystems. A floting-point coe ws uled out t the vey beginning of the design phse due to sevel key esons. The fist eson is the desie fo n FPGA design to use miniml powe. Floting point coes tke up significnt mount of el estte within the FPGA. A lge FPGA is equied to implement the floting point coe. Lge FPGA's equie moe sttic nd dynmic powe, theefoe, the floting-point implementtion consumes moe powe. The second eson is tht the input voltges nd cuents e digitized using n A/D convete. The digitized input voltges nd cuents e quntized to xxx mv/bit nd yyy ua/bit. These numbes don't hve infinite esolution. Theefoe, hving floting-point coe doesn t poduce ny moe pecision in the ESC lgoithm thn comped to biny mth. Anothe limiting fcto is the D/A convete used in poviding the contol voltge to the BCR's. The contol voltge hs fixed step size tht contols the mount of cuent the BCR's supply to the bttey. The ESC lgoithm closes the loop by ditheing the contol voltge ound cetin voltge to poduce n vege A. Fctionl Ode Extemum Seeking Contol Scheme A fctionl ode extemum seeking ppoch is pesented in Figue 5. In this ppoch the intege ode integto of IO-ESC is eplced by fctionl ode integto. As we will show lte, this eplcement cn impove the convegence speed of ESC lgoithm. Figue 5-Fctionl Ode Extemum Seeking Contol Scheme Conside genel single input single output (SISO) nonline model x f ( x, u) y h( x) u ( x, ) Assumption 1: Thee exists smooth function n l : such tht Mlek 4 6 th Annul AIAA/USU Confeence on Smll Stellites

5 f ( x, ( x, )) if nd onlyif x l( ) Assumption : Fo ech, the equilibium x l( ) of the system x f ( x, ( x, )) is loclly exponentilly stble with decy nd oveshoot constnts unifom in. Assumption 3: Thee exist ( h l) ( ) ( h l) ( ) Bsed on the Figue 1, we hve such tht x f ( x, ( x, ˆ sin( t))), q D ˆ k, ( y ) sin( t), l y. h l h q whee D is the fctionl ode Reimnn-Liouville integto 8. B. Stbility of Fctionl Ode Extemum Seeking Contol Let us intoduce new coodintes ˆ h l( ) Then, in the time scle system is ewitten s t, the foementioned dx f ( x, ( x, sin( ))) d 1q D K d L L( h( x) h l( ) ) sin( ) d H H ( h( x) h l( )) whee q D ˆ k ˆ D 1q k Fo the stbility nlysis, we need to feeze x in its equilibium vlue x l( sin( )) Then, we hve 1q D K d L L( v( sin( )) ) sin( ) d H H v( sin( )) whee v( sin( )) h l( sin( )) h l( ) Using ssumption 3, one cn esily conclude v(), v() ( h l) ( ), v() ( h l) ( ). w, using the veging method 9, we hve d d 1q D K L L v( sin( ))sin( ) d H H v( sin( )) d Fist, we need to detemine the vege equilibium, e, e, e (,, ) which stisfies e, cte,, 1 e, e v( sin )sin d, e 1, e v( sin ) d Then e, cte,, 1 e, e v( sin )sin d, e 1, e v( sin ) d Mlek 5 6 th Annul AIAA/USU Confeence on Smll Stellites

6 e, By postulting in the fom e, 3 b1 b O( ), we get v() b, 1 1 v() b v () 8 which implies v() 8 v() e, 3 O These esults in ( ). e, v() 3 O( ). 4 Thus, the equilibium of the vege model is v() 3 e, O( ) 8 v() e,. e, v() 3 O( ) 4 The Jcobin mtix t is J., (,, ) e fo the bove system L e, v( sin( ))sin( ) d L H e, v( sin( )) d H Since J is block-lowe-tingul, it cn be concluded tht it will be Huwitz if nd only if e, v( sin( ))sin( ) d (9) So, fom the pevious pts, one cn esily conclude e, v sin( ) sin( ) d Then, we get v() O( ) det( I J ) LK 3 L v () O ( ) H which poves tht J is Huwitz fo sufficiently smll. This, in tun, implies the equilibium of the vege system is exponentilly stble fo sufficiently smll. SIMULATION RESULTS OF FRACTIONAL ORDER EXTREMUM SEEKING CONTROL A. Simultion Results In this section, the IO-ESC nd FO-ESC e simulted nd comped using the PV model 4, boost DC-DC convete, nd Simulink/Mtlb. Since this lgoithm will be pplied to dynmomete, we will be equied to use longe ise times becuse the dynmomete cnnot espond s quickly nd is theefoe limited by the hdwe. The output of the ESC block is used s the input to the convete to tune its duty cycle (Figue 6). Numeicl simultions e done in two cses: without nd with envionmentl noise. The esults e illustted in Figue 7 nd Figue 8. These simultions e done unde the condition T=5 C, G=1 W/m, nd the extemum seeking contol gin is set to k=5. The noise pplied to the model is unifom noise ~U(-.1,.1). It cn be seen tht in both cses, the FO-ESC conveges to the extemum point fste thn the IO-ESC. It should be noticed tht the pplied extemum seeking scheme pefomnce is stisfctoy egdless of whicheve dmissible noise ffects the system. Figue 6-Block digm of poposed fctionl ode extemum seeking contol system. Mlek 6 6 th Annul AIAA/USU Confeence on Smll Stellites

7 Figue 7-Time esponse of the PV Module without noise when fctionl ode ESC is pplied (q=.95). Figue 9-Time esponses of the PV module fo diffeent integtion odes in fctionl ode ESC. To show the effect of the fctionl integtion ode, the diffeent simultion e done fo constnt bity k=15, while q (ode of the fctionl integto) is chnged in ech level. The esults e shown in Figue 9. It cn be obseved tht by educing q, the speed of convegence of the system towd extemum point is incesed. EXPERIMENTAL RESULTS Figue 8-Time esponse of the PV Module in pesence of noise when fctionl ode ESC is pplied (q=.95). A. Fctionl Hosepowe Dynmomete Since we don t hve the esouces to implement FO- ESC on the FPGA, we hve used nothe test bench to model the nonlineity of the PV pnels nd evlute the FO-ESC lgoithm. This new test bench is the dynmomete. The dynmomete includes DC moto, which is coupled with hysteesis bke, (Figue 11). The nonline behvio of the PV pnels cn be modeled using this hysteesis bek. The bek output toque cn be consideed s output cuent of PV modules. Then the output powe is poduct of this ngul velocity nd the cuent of PV modules. The poposed scheme cn be seen in Figue 1. Without loss of genelity, the DC moto in the dynmomete cn be ppoximted by the following tnsfe function Mlek 7 6 th Annul AIAA/USU Confeence on Smll Stellites

8 Gm 1.5 ( s). 1.1s 1 In this benchmk, we e tying to contol ngul speed of DC moto (which epesent the vege PWM voltge of DC-DC convete) to extct the mximum toque out of the moto, when nonline system, which epesent the PV model, hs been pplied to the bek. In this expeiment, the extemum seeking contol scheme is tested using the Mtlb/Simulink envionment, which uses the WinCon ppliction, to communicte with the Qunse MultiQ3 dt cquisition cd. WinCon is Windows-bsed ppliction tht uns Simulink models in el-time on PC. This bings pid pototyping nd hdwe-in-theloop simultion cpbilities to Simulink models. espectively. It is woth noting tht Simulink utomticlly genetes codes fo Windows tget to dive the dynmomete nd bke vi D/A blocks. It cn be seen tht the poposed ESC scheme cn be esily pplied to the fctionl hosepowe dynmomete s the PV model nd the esults e stisfctoy. Fom the Figue 13 nd Figue 14, it cn be lso noticed tht the convegence speed of FO-ESC is bette thn the IO-ESC which dmits the esults chieved fom numeicl simultion esults in pevious pt. Figue 15 nd Figue 16 illustte tht eduction in the ode of fctionl ode integto cn impove the convegence speed of FO-ESC. Figue 1-Modeling the PV pnel using fctionl hosepowe dynmomete. Figue 1-Simulink model used in the fctionl ode ESC el time expeiments using RTW Windows Tget Figue 11-The fctionl hose powe dynmomete developed t CSOIS 1. The Simulink model used fo the expeiments is shown in Figue 1. This figue shows the hdwe-in-theloop el time simultion models fo intege ode nd fctionl ode extemum seeking scheme, Mlek 8 6 th Annul AIAA/USU Confeence on Smll Stellites

9 Powe(Wtts) Voltge(V) Expeimentl Dt 15 IO ESC FO ESC Time(s) Figue 13-Convegence of PV voltge to extemum point pplying IO-ESC nd FO-ESC (q=.95). Figue 15-Convegence of PV voltge to extemum point pplying diffeent integtion odes in IO- ESC nd FO-ESC. 5 Expeimentl Dt 4 IO ESC FO ESC Time(s) Figue 14-Convegence of PV powe to extemum point pplying IO-ESC nd FO-ESC (q=.95). Figue 16-Convegence of PV powe to extemum point pplying diffeent integtion odes in IO- ESC nd FO-ESC. MPPT TEST CONTROLLER HARDWARE REQUIREMENTS AND CONSTRAINTS Although the cubest is n idel pltfom fo n MPPT bsed EPS, the cubest design equiements, pose specific chllenges to the implementtion. SDL hs designed n EPS hdwe contolle tht is bselined fo the PEARL cubest. This EPS hdwe contolle ws used s the test bed fo lgoithm testing. The Mlek 9 6 th Annul AIAA/USU Confeence on Smll Stellites

10 following equiements e typicl of cubests nd fom the bsis fo this EPS design. Sol Ay 1 Input Size nd Volume Requiements This EPS design ws specified fo 3U cubest. A single cd is llocted fo bttey chge mngement voltge egultion, nd powe distibution. The bttey is not included in this size lloction. The cd size is less thn 1cm on side. The component height is less thn 11.5 mm on the top nd less thn 3mm on the bottom. The design equies two septe chnnels to ccommodte two septe sol y inputs. Ech input is to implement mximum pek powe tcking to mximize the powe output of the sol y. BCR1 Sol Ay Input BCR 3.3V 5.V Switched Output 1 Switched Output 3.3V Regulted 5.V Regulted Powe Requiements The gol of the MPPT EPS is to mximize powe genetion fom the sol y nd t the sme time, minimize the mount of powe consumed to ccomplish this. The use of ult-low powe components nd high efficiency convetes is equisite. The design equiement is to hndle up to 4 wtts input powe ( wtts pe chnnel). The EPS is equied to be gete thn 9% efficient. The quiescent powe dw (no lod) is equied to be less thn mw. EPS Desciption nd Constints The EPS, s designed, includes two sol y inputs tht feed into septe bttey chge egultos (BCR). The BCRs use buck convete topology implemented with cuent mode DC-DC convete. The two convetes e tied togethe t the output whee they connect to the bttey. The bttey is 3S1P lithiumion bttey ted t.5 Amp-hous. Thee e two switched bttey outputs fo powe distibution long with two egulted powe buses of 3.3 volts nd 5 volts, see Figue 17 nd Figue 18. The MPPT chitectue effectively decouples the sol y fom the bttey nd llows fo much moe flexibility in EPS design thn comped to the Diect Enegy Tnsfe (DET). Voltge nd cuent monitos e plced on ech sol y input, the bttey, nd ech of the outputs. An ult-low powe FPGA is used to implement the lgoithm nd contolle. The low powe FPGA is key component. It llows fo minimum powe dissiption by the EPS nd selected due to highe tolence to dition effects ove othe commecilly vilble components. The low powe simple chitectue foces ll lgoithms to use fixed point intege bsed implementtions. This becomes one of the mjo design constints fo this poject. Figue 17 - EPS Electicl Block Digm Figue 18 - EPS Contolle Cd TEST SET UP Figue 19 shows the test equipment setup. The sol y simulto is used to genete the IV cuve fo the hdwe lgoithm tests. An extenl powe supply is used to povide powe to the EPS when the bttey is not connected. Fo consistency ske, most of the testing is done in this configution. A blocking diode is in seies with the extenl powe supply tht inhibits the powe supply fom sinking cuent. In this mnne, it is not consistent with el bttey, s the bttey will both sink nd souce cuent. A fou chnnel electonic lod is used to pply lods t ech of the fou outputs. The lod cn be vied s equied fo ech test. Finlly, commnd, contol, nd monito compute is povided tht llows the EPS pmetes to be configued nd the telemety dt, coming fom the EPS, to be monitoed. Mlek 1 6 th Annul AIAA/USU Confeence on Smll Stellites

11 Powe (W) -Chn SAS Extenl Powe Supply MPPT Test Setup Bttey Bod.5 Ah GSE Compute Commnd & Monitoing MPPT EPS UART 115kbud 4 Chn Electonic Lod Rmp Testing: This test povides n input whee the Imp nd Isc cuent e vied ccoding to mp function. The pupose of this test is to detemine how well ech lgoithm cn tck constnt te input vition. Souce Pulse (Step) Testing: This test pplies n input whee both Imp nd Isc cuents e stepped in one time incement fom low level to high level nd then bck down to low level. The pupose is to see the lgoithm s esponse to the step function input. This test tells us how fst the system will espond to lge petubtions Figue 19 - MPPT EPS Test Setup Tble 1 is the list of test equipment used in the MPPT testing. Othe components wee used t diffeent stges, including digitl multi-metes nd oscilloscopes, fo specific mesuements. Mnufctue Tble 1 - Test Equipment Model Numbe Desciption Agilent E3631 Tiple Output Powe Supply Agilent E436A Modul SAS Minfme Agilent E436 Sol Ay Simulto Module Agilent E436 Sol Ay Simulto Module Chom 6314 Electonic Lod Minfme Chom 631 Dul Chnnel Lod Module Chom 6317 Dul Chnnel Lod Module Dell M9 Lptop Compute + Monito TEST RESULTS AND COMPARISON OF FIXED POINT ESC AND P&O ALGORITHMS The EPS contol hdwe is designed to povide telemety ove seil link. The seil link is un t 115.kbud which llows fo evey smple pocessed by the lgoithm to be output nd collected fo nlysis. The dt pesented in this section is the full bndwidth unfilteed dt. Evey smple is collected nd displyed. Five diffeent types of tests wee pefomed on the test hdwe using both lgoithms. The tests include the following: Stedy Stte: This test ws 3 second smple in time of the EPS powe output with fixed sol y input. The gol of the test is to detemine how well ech lgoithm tcked the pek powe point with no vitions on the input. Lod Pulse Test: This test mintins stedy stte input but vies the output in step function. The lod is stepped fom vlue less thn the pek powe to vlue gete thn the pek powe. The gol is to detemine how well the contolle cn espond to bupt lod vitions. Sinusoidl Testing: This lst test pplied sinusoidl vying input. Both full sine wve nd hlf sine wve wee used. The gol of this test ws to detemine how well the lgoithms cn espond to time vying input consistent with ctul spce flight movements. Stedy Stte Response Results The sol y simulto is configued to epesent single sting sol y with 7 cells in seies. The open cicuit voltge, Voc, is volts; Vmp is volts; Imx powe is.433 mps; Isc is.453 mps. A 3 second smple is tken fo ech chnnel septely nd then fo both chnnels simultneously. The test is epeted using ech lgoithm to enble side by side compison ESC Stedy Stte Response (CH) Time (S) Figue -ESC Stedy Stte Response Mlek 11 6 th Annul AIAA/USU Confeence on Smll Stellites

12 Powe (W) Powe (W) P&O Stedy Stte Response (CH) Time (S) Figue 1- P&O Stedy Stte Response We looked t fou diffeent metics, see Tble. The fist ws Avege Powe. This is simply the men vlue of ll of the smpled dt. The next e the minimum nd the mximum vlues. These vlues e the minimum ecoded powe vlue nd the mximum ecoded powe vlue espectively deliveed by the sol y. The lst vlue is n vege pek to pek vlue. This pmete veges ll of the positive diection pek powe vlues gete thn the men nd then subtcts the vege of ll of the negtive diection peks less thn the men. The diffeence is the vege pk-pk vlue. It is gphiclly epesented by the ed lines in the plot. Fom the dt it is vey ppent tht the ESC lgoithm is out pefoming the P&O lgoithm in the stedy stte. A summy of the othe chnnels nd configution tested, showed the ESC lgoithm to be bette in ech of the test cses fo the stedy stte. The ESC lgoithm ws much less sensitive to chnnel to chnnel hdwe diffeences. Also the ESC lgoithm did not seem to be ffected by simultneous opetion of both chnnels. The pefomnce styed consistent egdless of which chnnels wee ctive nd when. The P&O lgoithm showed moe sensitivity between the chnnel to chnnel hdwe diffeences. Thee lso ppeed some stuctue in the output plots when both chnnels wee opeting togethe suggesting some sot of chnnel to chnnel intection. Tble -ESC Stedy Stte Powe Metics Metic ESC Vlue P&O Vlue Avege Pek-to-Pek.4 wtts.19 wtts Avege Powe wtts wtts Minimum Powe wtts wtts Output Mximum Powe 7.1 wtts 7.93 wtts Output Dynmic Response Results The est of the testing involves eithe dynmic souce input o dynmic lod. The IO-ESC ws implemented without slope seeking contol. It theefoe is expected to hve some decesed pefomnce in the dynmic envionments. This is discussed futhe in ou conclusions section. The following figues, Figue though Figue 5, show the esponse of the lgoithms to fou diffeent dynmic inputs. In ll cses the lod ws set to be gete thn the mximum vilble sol y input powe. This foces the contolle to lwys ty nd contol to the mximum powe point of the input. Both lgoithm esults e plot togethe to llow fo esy compison of diffeences. Fo the mp test, the y is nominlly set to Pmp = 1.65 wtts (mximum powe point) nd then mped up to Pmp = 8.5 wtts. This is done by vying the sol Imp input cuent fom.1 mps to.5 mps t te of 5m pe ms. Both lgoithms tck the mp but the ESC exhibits stutte t the beginning of the mp Rmp Test - Chnnel 1 (Rte = 5m/ms) ESC P&O Time (S) Figue - Rmp Test (Rte = 5m/ms) The input souce step/pulse test is configued by setting the input to nominl 1.65 wtt pek powe point. The souce is then step vi single commnd to 9.87 wtts pek. The plot shows the speed of the esponse to the step input function. Agin, the P&O demonsttes fste esponse to the ising edge of the step. The flling edge is fo ll pcticl puposes the sme. Both lgoithms equie some finite mount of time to eestblish contol fte the negtive step. We should note hee tht the esponse shown in the plot is combintion of the entie system nd not just the lgoithms themselves. The EPS bod hs Mlek 1 6 th Annul AIAA/USU Confeence on Smll Stellites

13 Powe (W) Powe (W) Powe (W) significnt mount of input cpcitnce tht slows the input ise time Souce Pulse/Step Test (Imp = 1 to 6mA) ESC P&O looking like the step test. A smlle mplitude o lge time peiod would hve been moe ppopite. Eithe wy, the P&O lgoithm tcks the input fily well with the exception of the smll spike on the ising edge simil to tht seen on the pulse test. The flling edge looks eltively clen. The ESC lgoithm sees the sme spike on the ising edge. It lso hs the sme slow esponse poblem on the flling edge s well Sinusoidl input esponse (Imp = +/-5mA) Time (S) Figue 3-Souce Pulse/Step Test. Input steps fom 1mA to 6mA. The next plot shows the esults of the full wve sine input. The sol y input is pogmmed to output.1hz sine wve with Imp vied between ±5m (±4.1 wtts). The entie input is offset by 35m to llow swing between 1mA nd 6mA. Agin, the lod is set to vlue gete thn the mximum input powe level to ensue tht the contolle is lwys tying to dive towds the pek powe point. The P&O lgoithm exhibits vey good esponse to this input nd tcks the sol y input vey pecisely. The ESC lgoithm hs moe touble. On the ising edge, the lgoithm is somewht delyed but still esponsive. On the flling edge, we cn see whee the lgoithm loses contol llowing the y to collpse nd then it ecoves nd epets the scenio until the input stts to ise gin. The hdwe configution is n impotnt fcto in this collpse. When the input powe begins to dop, the net effect is to foce the system to the shot cicuit side of the sol y I-V cuve. If the lgoithm does not espond fst enough to thottle bck the lod seen by the y, then the y voltge will collpse down to the bttey voltge. Once thee, the lgoithm cnnot simply thottle bck to the pek powe but the it must thottle ll of the wy bck to the equivlent voltge cuent vlue on the open cicuit side of the I-V cuve. Once thee it cn begin to mp bck up to the new pek point. You cn see this esponse in the flling edge of the sinusoidl cuve. The hlf wve test shows simil esults s both the full wve sine test nd the input step test. The hlf wve mplitude is the sme s tht used in the step test nd the speed of ise is sufficiently fst tht is close to Time (S) Figue 4- Sinusoidl Input. Imp mplitude = +/- 5mA ove 1 second peiod Hlf Sinewve Input (Amplitude Imp= 6mA) ESC P&O Time (S) Figue 5- Hlf wve sine input. Imp Amplitude = 6mA. The peiod is 1 seconds. CONCLUSION In this ppe, A Petub nd Obseve, IO-ESC, nd FO- ESC lgoithms e biefly intoduced. The poposed extemum seeking contol method with both intege ode nd fctionl ode integtos e simulted using Mtlb/Simulink nd the common PV model fo two diffeent cses; In pesence of envionmentl noise nd without noise. Then, using the fctionl hosepowe dynmomete, expeiments wee done to test both extemum seeking lgoithms, fctionl ode Mlek 13 6 th Annul AIAA/USU Confeence on Smll Stellites

14 nd intege ode. In pllel, IO-ESC nd the P&O lgoithms wee expeimentlly tested using PV y simulto nd the PEARL spcecft electicl powe system s the test bench. Fom the expeimentl esults on the dynmomete benchmks, it cn be decled tht the fctionl ode ESC hs bette pefomnce in compison with intege ode ESC. Also the expeimentl esults on the PV y simulto nd EPS test bench hve been discussed in this ppe. As we cn see in these expeiments, in the stedy stte condition, ESC cn extct moe powe fom PV pnels, hs smlle pekpek powe ipple, nd povides gete immunity fo chnnel to chnnel intefeence in compison with P&O contolle. In the dynmic esponse tests, the P&O lgoithm clely outpefoms the IO-ESC lgoithm s pesently implemented. Becuse of time constints, we wee not ble to implement the slope seeking contol potion of the ESC lgoithm nd compe it to the P&O. Obviously; ESC cnnot follow fst slopes nd cnnot stisfy high dynmic esponse MPPT equiements s we cn see in the expeimentl esults. The ESC lgoithm tends to find the extemum point nd t this point the slope constntly is equl to zeo. When we hve slope which is not zeo, like in the mp condition, we need to dd the mount of this slope to the integto of the ESC lgoithm to foce the system to follow this nonzeo slope insted of following the zeo slope. Implementing slope seeking contol nd impoving the mximum powe point tcking in the mp condition will be the focus of follow on wok ssocited with this poject. ACKNOWLEDGMENTS We would like to cknowledge nd thnk the Ai Foce Resech Lbotoy fo poviding the funding fo this esech effot without which it could not hve been possible. We would lso like to thnk the Spce Dynmics Lbotoy nd Uth Stte Univesity fo suppot of time nd othe lbotoy esouces involved in the testing. 3. K. Aiyu nd M. Kstic, Rel Time Optimiztion by Extemum Seeking Contol, Wiley, J. A. Gow, C. D. Mnning Development of photovoltic y model fo use in poweelectonics simultion studies, IEEE Poceedings on Electic Powe Applictions, vol. 146, no., pp. 193-, Mch M. Kstic nd H.H. Wng, Stbility of extemum seeking feedbck fo genel nonline dynmic systems, Automtic, vol. 36, no. 4, pp ,. 6. B. Johnsson, Impoved Models fo DC-DC Convetes, Deptment of Industil Electicl Engineeing nd Automtion, Lund Univesity, S..Mou, A switchecd extemum seeking ppoch to mximum powe point tcking in photovoltic systems, EECS Poject, Apil I. Polubny, Fctionl diffeentil equtions. New Yok: Acdemic Pess, H. K. Khlil, nline systems. Pentice Hll Uppe Sddle Rive, NJ,. 1. Y. Tte, Y.Q. Chen, W. Ren, nd K. Mooe, Fctionl hosepowe dynmomete-a genel pupose hdwe-in-the-loop el-time simultion pltfom fo nonline ontol esech nd eduction, Poc. 45th IEEE Confeence on Decision nd Contol, Sn Diego, 6, pp Refeences 1. S.L. Bunton, C.W. Rowley, S. R. Kulkni, C. Clkson, Mximum powe point tcking fo photovoltic optimiztion using Ripple-Bsed extemum seeking, IEEE Tnsctions On Powe Electonics, Vol. 5, pp , 1.. T. Esm nd P. L. Chpmn, Compison of photovoltic y mximum powe point tcking techniques, IEEE Tnsctions On Enegy Convesion, vol., pp , 7. Mlek 14 6 th Annul AIAA/USU Confeence on Smll Stellites