ala ISSUED NOV 1979 MOSAND SPECIAL COS/MaS 1 st EDITION INTRODUCTION

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2 ala MOSAND SPECAL COS/MaS st EDTON SSUED NOV 979 NTRODUCTON This databook contains data sheets on the SGS-ATES range of products in MaS and COS/MaS technology. The information on each product has been specially presented in order that the performance of the product can be readily evaluated within any required equipment design. The'databook also contains a summary of the processes available in SGS-ATES for the development and production of the products listed.

3 FUNCTONAL NDEX Type Technology Function PB9! MUSC M082 N channel MOS Tone generator 33 M083 N channel MOS Tone generator 33 Moa6 N channel MOS Tone generator 33 M087 P channel MOS Tone generator 37 M08 N channel MOS Single chip organ (solo + accompaniment) 55 M47 P channel MOS 3-bit latch pedal sustain 73 M25 P channel MOS Arpeggio chord and bass accompaniment generator 3 M252 P channel MOS Rhythm generator 2t; M253 P channel MOS Rhythm generator ~ M254 P channel MOS Rhythm generator 4~ M255 P channel MOS Rhythm generator 53 M258 N channel MOS Rhythm generator s] M259 N channel MOS Rhythm generator 59j M738 COS/MOS 7-stage divider 8~ M740 COS/MOS 7-stage divider 8lj M74 COS/MOS 7-stage divider ~ M747 COS/MOS 7-stage divider 8~.~.~~ TV& RADO M054 N channel MOS of 6 decoder M055 N channel MOS of 6 decoder ~ M025 P channel MOS 30-channel remote control receiver 2t M30 P channel MOS 30-channel remote control receiver 22~ M93A N channel MOS Electronic Program Memory M90 N channel MOS 6 key keyboard encoder and latch M9 N channel MOS On-screen tuning scale and band display M06 N channel MOS TV microprocessor interface M24 COS/MOS 30-channel remote control transmitter M024 COS/MOS 30-channel remote control transmitter M92 COS/MOS 4-bit binary 7-segment decoder driver ~ TELECOMMUNCATONS MOO5 P channel MOS 4 channel multiplexer 9,'l MOO6 P channel MOS Counter-controlled 8-channel sequential multiplexer MOO9 P channel MOS 2 channel multiplexer ~ M089 N channel MOS 2x8 cross-point matrix 4~ M75 COS/MOS Touch tone generator 99; j 4 -! "~ -~ :i '. "

4 FUNCTONAL NDEX (continued) Type Technology Function Page MEMORES M20 N channel MOS M20-2 N channel MOS M202A N channel MOS M202AL N channel MOS M236E N channel MOS M36000 N channel MOS,M2708 N channel MOS M2704 N channel MOS M4027 N channel MOS M46 N channel MOS CLOCKS & TMERS M702 COS/MOS M706 COS/MOS M74 COS/MOS M730 COS/MOS M73 COS/MOS M750 COS/MOS M752 COS/MOS M754 COS/MOS SHFT REGSTERS M42 N channel MOS M42A N channel MOS 024 bit non-volatile random access memory 024 bit non-volatile random access memory 024 bit static random access memory 024 bit static random access memory 6384 bit read only memory 64 K-bit read only memory M2708-8K bit (024x8) UV erasable PROM M2704-4K bit (52x8) UV erasable PROM 4096-bit dynamic random access memory 6384-bit dynamic random access memory 6-stage counter 6-stage counter 23-stage counter 23-stage counter 6-stage counter 23-stage counter with intermediate output at the 6th stage 6-stage counter 23-stage counter with intermediate output at the 6th stage Quad 80-bit static sh ift register Quad 80-bit static sh itt register SGS-ATES MOS processes history and summary SGS-ATES entered the MOS market in 969 with the newly developed Planox process. This was followed by development of the P-channel Silicon Gate process in 97 and the N-channel Silicon Gate process in 973. n 976 the company began development of the N-channel process with double polycrystalline silicon which is extremely important for the realization of very high complexity circuits or memories. n 977 SGS-ATES developed electrically programmable read-only memories and in 978 Non-Volatile read and write memories. Concerning COS/MOS technologies, in 974 SGS-ATES put the type A Aluminium Gate Process into production followed in 976 by the type B process with ion implantation. The Low Voltage Aluminium Gate process was developed in 978 and put into production in

5 SGS-A TES MOS processes. P-channel enhancement mode with a P-type polycrystalline silicon gate Threshold voltage:.5 to 2.5V Supply voltages: Vcc= +5V, VGG= -2V Used in static and dynamic 2 (il applications Compatible with bipolar circuits 2. Low threshold N-channel enhancement/depletion mode with an N-type polycrystalline silicon gate Threshold voltage: 0.6 to.2v Supply voltage: Vcc= +5V Used in static and dynamic systems Compatible with bipolar circuits 3. N-channel enhancement/depletion mode with an N-type polycrystalline silicon gate Threshold voltage: 0.8 to.2v with V ss= -5V Supply voltages: Voo= +2V, Vss= -5V, Vcc= 5V Used in static and dynamic systems Compatible with bipolar circuits 4. N-channel enhancement/depletion mode with an N-type polycrystalline silicon gate Threshold voltage: 0.8 to.2v Supply voltages: Voo= +2V, Vcc= 5V Used in static and dynamic systems Compatible with bipolar circuits 5. N-channel enhancement/depletion mode with double N-type polycrystalline silicon gate - Threshold voltage: 0.8 to.2v with Vss= -5V Supply voltages: Voo= + 2V, Vss= -5V, Vcc= 5V - Used for UV erasable and electrically programmable ROMs - Compatible with bipolar circuits 6. N-channel enhancement/depletion mode with double N-type polycrystalline silicon gate Threshold voltage: 0.8 to.2v Supply voltage: Voo= +2V, Vcc= 5V Used for UV erasable and electrically programmable ROMs Compatible with bipolar circuits 7. COS/MaS Aluminium Gate A & B process - Threshold voltage: to 2V - Supply voltage: Voo= +3 to +8V 8. COS/MaS Aluminium gate - low threshold voltage Threshold voltage: 0.5V to V - Supply voltage: V DO =.5 to 5V 6

6 DATA-SHEETS

7 MOS NTEGRATED CRCUTS M CHANNEL MULTPLEXER The M005 is a 4 channel multiplexer constructed on a single monolithic chip using P-channel low threshold silicon gate technology. The device is available in la-lead metal case similar to Jedec TO-lOa. ABSOLUTE MAXMUM RATNGS Vos Drain to source voltage -0 to 0.3 V V GS Gate to source voltage -35 to 0.3 V V GO Gate to drain voltage -25 to 0.3 V T 59 Storage temperature range -65 to 50 C Top Operating temperature range o to 70 C ORDERNG NUMBER: M 005 Tl MECHANCAL DATA Dimensions in mm 9 /79

8 M 005 PN CONNECTONS (top view) SCHEMATC DAGRAM DRAN,------r~----_+~----_~-+ O~ STATC ELECTRCAL CHARACTERSTCS (T amb = 0 to 70 C unless otherwise specified) Values Parameter Test conditions Unit Min. TVp Max. Vi Analog input voltage VGs= -20V VeuLK=0V ± 0 V VTHO Threshold voltage V OS- VGS los- 00 /la Ves= V Ros Drain to source on resistance VGS- -0V los-0ma Ves= n VGS- -20V los-0ma Ves= n GL Gate leakage current VGs= -0V Vos=O Ves= 0 - na 0L Drain leakage current Vos- -5V VGS-O Ves= 0-20 na 0 Drain current V GS- VOS- -5V Ves- O -60 ma, 0

9 M 005 DYNAMC E lectr CAl CHARACTER STCS (T amb= 0 to 70 C unless otherwise specified) Parameter Test conditions Value, Min. Typ. Max. Unit Yls Forward transadmittance Vos= -3V V BS= OV VGS= -0V Cos " Drain to source capacitance Vos= 0 f - MHz V Pp=5mV CGO" Gate to drain capacitance VGO=O f = MHz V Pp=5mV CGS" Gate to source capacitance VGS= 0 f = MHz VPp=5mV Cse" Source to body capacitance Vse= 0 f = MHz V Pp=5mV Coe" Drain to body capacitance VOB-O f - MHz V Pp=5mV ege" Gate to body capacitance VGe- O f - MHz VPp=5mV 'mho pf 2 3 pf 2 3 pf 8 0 pf pf 4 6 pf " This parameter is periodically sampled and not 00% tested. SMALL SGNAL EQUVALENT CRCUT (conditions: VGs= -0V, Vos= -3V, Ves= 0) "" 50 ma GATE CGD cr-.----~----~~~~~--~~--~~ ~~--~--~~dran BODY AND CASE SOURCE SOURCE

10 M 005 Symbol Characteristics Typical values Unit Diodes rgs ro CGS ego CDS CGB COB CSB Y fs All diodes are to be considered perfect diodes Gate to source leakage resistance and diode leakage resistance Dynamic drain resistance Gate to source capacitance Gate to drain capacitance Drain to source capacitance Gate to body capacitance Drain to body capacitance Source to body capacitance Forward transadmittance 0 n 0.5 kn 2 pf 2 pf 0.5 pf 6 pf 40 pf 0 pf "mho "0 (ma) " Drain current vs. drain to source voltage V 7 ~--,/./ / -2SV /, V./ V.)5'/ / r-r- / """ ;...r VGS' -2V V f--'",... - V ~ i "0 ima Drain current VS. drain to source voltage ~ (;' -OV." ) -9' _'---..." '.'." f /" v:' '/ '/, : :-2' o.././ ('..- "0 ima, Drain current VS. source voltage / V i / vgs:vos/ drain to "0 'ma OJ Drain current VS. drain to source voltage (', ) V, YGSC-S~./." V,../ V./,../ 4" /./v V ~ (j.~ V...- '/ V..-' ~ /' :, ~ -2~ / --r-- 2 r S 2

11 005 TYPCAL APPLCATONS Variable gain amplifier with multiplexed inputs ~ ~----~ -< Vo Vi 2()------, Vi 3 r---, Channel 3 o Vi 4 Lr""-----, -r Channel 2 Of '- -r- -r- Channel 4 0>----'- -r- xl Gain 0 L~2 -r- L Gain3 0 Gain4 ---D R4 RS R6 x0 R, xloo R2 x Sample and hold 3

12 005 TYPCAL APPLCATONS(continued) Multiplexing - demultiplexing r <uvo 2 r <ovo 3 4

13 MOS NTEGRATED CRCUT 008 COUNTER-CONTROLLED 8-CHANNEL SEQUENTAL MULTPLEXER LOW ON RESSTANCE LOW CAPACTANCE BETWEEN N/OUT CHANNELS FULLY TTL or DTL COMPATBLE LOW POWER DSSPATON: 70 mw TYP. The MOO6 is a monolithic integrated circuit using low threshold P-channel silicon gate MOS technology. t is supplied in a 6-pin dual in-line plastic or ceramic package. Functionally the device consists of a modulo,..8 counter, sequentially controlling the opening or closing of 8 ana logic switches. Each of the switches is formed by two transistors Tl and T2 with their drains connected together. The closure of each in/out switch occurs on the rising edge of the clock and has a duration of half the clock period. The inputs to the device are: clock input, to drive the counter; reset input, to return the counter to zero; matrix enable, to enable the logic network which decodes the counter states and drives the eight switches shunt enable, which determines whether transistors T2 can switch or not. The eight transistors Tl have their sources connected together and brought out on the "Serial Bus". Similarly the sources of transistors T2 are commoned and brought out on the "Parallel Bus". ABSOLUTE MAXMUM RATNGS VGG* V V* V/a * T 59 Top Source supply voltage Analog input voltage (distortion < 70 db) nput voltage Bus voltage Storage temperature Operating temperature -20 to 0.3 V ±2 V -20 to 0.3 V -20 to 0.3 V -65 to 50.oC o to 70 C * This voltage is with respect to Vss (GND) pin voltage. ORDERNG NUMBERS: MOOS Bl for dual in-line plastic package MOOS 0 for dual in-line ceramic package 5 /"/9

14 008 MECHANCAL DATA (dimensions in mm) Dual in-line plastic package -. ~t-~ RL7.~' -. L.J ' _o.lfi ~ ::: POO-C Dual in-line ceramic package o~.--=;'t. 778 tt _=_~~5n~~~,. <) ~~.:b,, PN CONNECTONS N/OUT ' SERAL BUS PARALLEL BUS VGG VSS RESET MATRX 7 ENABLE CLOCK N/OUT 2 5 N/OUT 3 4 N/OUT 4 3 SHUNT ENABLE 2 N/OUT 5 N/OUT 6 o N/OUT 7 9 N/OUT 8 6

15 M006 LOGC DAGRAM N/OUT! NOUT 2 N/OUTl NOUT 4 N/OUT5 "f OUT 6 N/OUT 7 N/cure PARALLEL 8US L---~~~-4-}~---+~~---}~~--~+-4---~~~--+4--L---~-o, SERAL BUS eloc! ~T [> QO ill> Q. (!i Q' a t t t t t t COUHTEA n TMNG DAGRAM CLOCK RESET SERAl. BUS P~L8US ~T ~~ ~v --GND ""- ENJU L-...Jr ~: GND... GND ~fo.jt N/OUT 2 N/OUT l N/OUT' N/OUT 5 N/OUT 6 N/OUT 7 N/OUT 8 u u u u u u u u u S-H,"t 7

16 TRUTH TABLE (negative logic) To simplify the description of the functional operation of the device this truth table has been compiled assuming the serial and parallel bus terminals as inputs, and the eight in/out terminals as outputs. Closure of the switches T and T2 is controlled by the signals Shunt Enable, Matrix Enable and Reset, and the counter states. S. E. M.E. RESE COUNTER PARALLEL SERAL STATES BUS BUS N/OUT N/OUT 2 N/OUT N/OUT 3 4 N/OUT N/OUT N/OUT N/OUT x X 0 0 COUNTNG X X X Y 0 0 X Y z Y 0 COUNTNG Z Y Z Y o 0 Z Y F F Y/F F Z Z Y/Z Z F F F F Z Z Z Z F F F F Z Z Z Z F F F Y Z Z Z Z F F F F F F F F F F F F F F F F Z Z Z Z Z Z Z Z Z Z Z Z Y Z Z Z For example.. n synchronism with the clock O=Vss =GND X= Don't care F = Floating Y = Digital or analog signal Z = Logic level TMNG AND DYNAMC ELECTRCAL CHARACTERSTCS (V ss V GG = -.5 to -2.5V, T amb = 0 to 70 C unless otherwise specified) 4.75 to 5.25V, Values Parameter Test conditions Unit Min. Typ. Max. Voj>H Clock high voltage V ss-l.5 Vss V Voj>L Clock low voltage VGG 0.4 V Ros Drain to source on resistance 05= 00llA -2V 300 Tl serial N/OUT T2 parallel N/OUT 5V 250 n fel Maximum clock frequency MHz t,ppw Clock pulse width 0.5 ls Shunt enable, matrix enable, reset to high V ss-l.5 VSS V Shunt enable, matrix enable, reset to low VGG 0.4 V C nput capacitance V = Vss f = MHz 6 pf ClO Capacitance between adjacent channels V Pp-5mV f - MHz 0.5 pf 8

17 ~. ~TYPCAL APPLCATONS ~PAM section of 32-channel PCM terminal in transmit mode. (Negative logic) ~ i t, -2V SERAL 8US PARALLEL BUS '5' PARALLEL ous.,. SERAL.us 8 CLOCK 3, MOO6 " NOUl N/OUTl NOUTl N/OUT4 2 N/OUT5 N/OU' '0 N lout 7 N/OUT,8 r - -- SERAL BUS PARALL l au r+--h NOUTS NOUT NOUT, MOO6 N/OUT2 NOUT ] N/OU" N/OUT'5 N/CUllS HC-H8F4049,, ,,, "'A, MAT, '-.J,. NT.. SERAL aus PAAAll L U NOUT" N/OUT,. 3 N/OUlli NOUT 20 MOO6 NOUT 2 N/OUT22 NOUT 23 N/QUrVo TElEPHONE CHANNELS lijl"!;!;r2 "L..!O!l!U~S... _+_+_P.'" OUT "o i!&t\';,l ENABLE 3 L K r+--h -'2V , MOO6 " PARALLEL au NOUTl5 N/DUTZ6 5 " NOU':'2? NOUT 2 2 NOUT 29 4'4 NOUT Xl (TO- THE ANA.OG DGTAL CONYERTER FOR Pl.'" t PC'" CON' RSU)N) RESET '0 N/QUTl' NOUT 32 ",e parallel bus is floating since transistors T2 are hold off by the shunt enable input. The telephone mputs are N/OUT... N/OUT 32. Jhe output is obtained on the "serial bus as a train of pulses on a single line sequentially combining all ~e input signals. rhe 300.n on resistance of T is acceptable in the transmit mode. 9

18 M006 TYPCAL APPLCATONS (continued) PAM section of a 32-channel pem terminal in receive mode. (Negative logic).2v SERAL BUS PARALLEL BUS loc( 5." 3 PARALLEL BUS 52, MOOS "" 53.$V RE T SEAfAL s, aus 55 sa so 50 sn S2 H8C-H8F4049 TAl NT LO " S3 S4 SS T LE'MCN!. C_S OUT S7 5 Sit 50 ~, S' 'M RESET 52 S.. S" S28 CLOCK CL S2 -llv ENABLE 3 ME. RESET 2V,... PAM S S Sit S'" S3 S32 BUS N '_"Ml n reception a train of amplitude modulated pulses on the input bus is demultiplexed into 32 channel outputs S Since a low series resistance is essential the MOOS (RoS/ON :!!! 200) has, been used. 20

19 006 tvpcal APPLCATONS (continued) Block diagram PCM TERMNAL N TRANS"" MODE l : N/OUTl PCtr04 TERMNAL N RECE... E MODE ' PAM PAM, 'N/ruT 32 ~ , ! Timing waveforms refer to a.m. 32-channel PAM telephone system CLOCK,.. CLOCK' jl ~n~ ~n~ ~n~ ~~ MATRX ENABLE' L MATA ENAllLE 2 MATRX ENABLE 3 MATRX ENAllLE 4 L J 5 '2 2

20 ,:MOS NTEGRATED CRCUT M009 ;2 CHANNEL MULTPLEXER ; The M009 is a 2 channel multiplexer constructed on a single monol ithic chip using P-{;hannel low threshold silicon gate technology. The device is available in a-lead metal case similar to Jedec TO-99. ABSOLUTE MAXMUM RATNGS Vos VGS VGO T 59.ToP Drain to source voltage Gate to source voltage Gate to drain voltage Storage temperature range Operating temperature range -0 to to to to 50 o to 70 v V V C C ORDERNG NUMBER: M 009 T MECHAN CAl OAT A Dimensions in mm 27"" i. ~ 'J ~,~ = '~ 23 '/79

21 M009 PN CONNECTONS (top view) SCHEMATC DAGRAM BULK Ne , , L -.l 5, STATC ELECTRCAL CHARACTERSTCS (T amb= 0 to 70 0 e unless otherwise specified) Values Parameter Test conditions Unit Min. Typ. Max. Vi Analog input voltage VGs= -20V V BULK=0V ± 0 V V THO Threshold voltage VOS- V GS los- OO la V BS= S V Ros Drain to source on resistance V GS- -0V 05-0 ma V BS= 0 20 SO n VGS= -20V 05= 0mA V BS= n GL Gate leakage current VGS= -0V VOS=O V BS= 0 - na 0L Drain leakage current V OS- -SV VGS-O V BS= 0-20 na 0 Drain current VGS= VOS= -SV VBS-O -60 ma 24

22 MOOg PVNAMC ELECTRCAL CHARACTERSTCS (T amb= 0 to 70 0 e unless otherwise specified) Parameter Test conditions Values Min. Typ. Max. Unit 'Yfs Forward transadmittance VOS= -3V VBS= OV [Cos" Drain to source capacitance VOS- 0 VPp=5mV 'ego" Gate to drain capacitance VGO-O V PP= 5mV ~GS" Gate to source capacitance VGS= 0 VPp=5mV [<:ss" Source to body capacitance VSB= 0 VPp=5mV lcos" Drain to body capacitance VOB=O r: VPp=5mV. egb Gate to body capacitance VGB-O VPp=5mV,.' 'This parameter is periodically sampled and not 00% tested. ~.,-, ~,, ~ amall SGNAL EQUVALENT CRCUT, iconditions: VGs= -0V, VOS= -3V, VBS= 0) "" 50 rna) VGS= -0V f - MHz f - MHz f = MHz f = MHz f = MHz f - MHz lmho pf 2 3 pf 2 3 pf 8 0 pf 8 0 pf 4 6 pf :6ATE DRAN COB r D CDS BODY AND CASE CGB C5B ';. S0URCE lj--+--_--_- --"_--_-t---t--_-_--usqurce! f;

23 MOD9 Sy,!,bol Characteristics Typical values Unit Diodes rtis ro CGS CGO Cos CGB CDB CSB Y fs All diodes are to be considered perfect diodes Gate to source leakage resistance and diode leakage resistance Dynamic drain resistance Gate to source capacitance Gate to drain capacitance Drain to source capacitance Gate to body capacitance Drain to body capacitance Source to body capacitance Forward transadmittance 0' 0 n 0.5 kn 2 pf 2 pf 0.5 pf 6 pf 40 pf 0 pf "mho " Drain current vs. drain to source voltage _35.'/ V -,,/ v / L J -25' V-! / V "" VGS=-2V V- ---'" k'" Drain current VS. drain to source voltage (~~, r.-,,-m(lj.tttt. _-;YTC_r'-":~;~~~~~L=~V~~ -'0, '(tj -'" V ~ rtf! :::.f--h i -- ~-" :-2 '/ 0' 04 Q. -'0 (m. l.0.0,0 20 Drain current VS. source voltage V vgs:voj L /. drain to "0.. (m. l '0 '0 '0 Drain current VS. drain to source voltage G_UU YGS -5~ ""V / -SY V V V V., V J... v V v-" (/ V,;;.;-- ~ - '/ V V ~ /' ~ r- '""'"""".---'" >--f- -, -" V --r- -~ ~ 26

24 M009 TYPCAL APPLCATONS Variable gain amplifier with multiplexed inputs Vi lr---.. Channell Of ' xl Channel 2 a T T Gainl a T Gain2 L----O s Sample and hold 27

25 MOD9 TYPCAL APPLCATONS (continued) Multiplexing - demultiplexing 5- on Series parallel chopper (low direct voltage amplification) H

26 f _S NTEGRATED CRCUTS r ~ t f OF 6 DECODER l "' SPECFCALLY DESGNED FOR TV APPLCATON MNMZATON OF THE EXTERNAL COMPONENTS. NTERNAL PULL-UP FOR USE WTH LGHT PRESSURE SWTCHES (M054) r OPEN DRAN OUTPUTS FOR TOUCH CONTROL (M055) the M 054, M 055 are monolithic integrated circuits specifically designed to act as interface between 025 (30 channel ultrasonic receiver) and H 580/590 (quad analog switch) in TV applications. The ~utsa,b,c,d,e are driven directly from the corresponding outputs of the M 025.lf G input is high the llrcuits decode the binary combinations from 0 to 5, if G is low the combinations from 6 to 3 are ecoded instead. The M 054 has an internal pull-up circuit on the outputs to minimize the number of Xternal components when light pressure switches are used. The M 055 has open drain outputs for touch ~ntrol applications. The circuits are constructed with N-channel silicon gate technology and are supplied n' a 24-lead dual in-line plastic package. ~OLUTE MAXMUM RATlNGS* Supply voltage nput voltage Oft state output voltage (M 055 type) Total power dissipation Storage temperatu re Operating temperature -0.5 to to to 50 o to 70 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is. a stress rating only and functional operation of the device at these or any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All voltages values are refered to V ss pin voltage. ORDERNG NUMBERS: M 054 B M 055 B V V V W C C.eCHANCAL DATA Dimensions in mm [::::::] 32""". ruoersedes issue dated 9/76 29 /79

27 PN CONNECTONS BLOCK DAGRAM OUT OUT 2 OUT 3 OUT 4 OUT 5 OUT 6 OUT 7 2, 4 5 6, OUT B [ 8 OUT 9 [ 9 OUT 0 [ 0 OUT [ V55 [ 2 S., 24 "00 23 N E 22 N A 2 N B 20 N C 9 N D 8 P N G OUll6 7P 6p 5P 4P OUllS OUT. OUT 3 "p OUT2 '!ll TRUTH TABLE (positive logic) NPUTS M 025 output code ~- E A B C 0 G X X X X X X X X l' OUTPUTS RECOMMENDED OPERATNG CONDTONS Voo V VO(Off) Top Supply voltage, nput voltage Off state output voltage (MOSS type) Operating temperature 7to 9 o to Voo 9 o to 70 V V V C 30

28 STATC ELECTRCAL CHARACTERSTCS (over recommended operating conditions) Values at 25 C Parameter Test conditions Unit Min. Typ. Max. V H High level input A-8-C-O-E nputs V oo-l Voo voltage G nput 3 Voo V V L Low level input A-8-C-O-E nputs 0 Voo-4 voltage V G nput L Low level output current V oo- 7V VOL - 0.4V.6 ma!oh High level output current (M 055 Type) M 054 Type V OD 9V -200 JA VOH= 8V 'O(off) Off state output current (M 054 Type) M 055 Type Voo= 9V VO(off)= 8V JA DO Supply current V oo- 9V All input to Vss 25 ma TYPCAL APPLCATONS Fig. and 2 show a typical application of M 054 and M 055 respectively in a TV remote control system. Fig. - M054 with light pressure switches 3

29 TYPCAL APPLCATONS (continued) Fig. 2 - M055 with direct touch controls o '~~~V -c~ ~--. z ~J)v iil 6 :: """GRAM" PPROGRAM' 2.2 Mn 2.2 "" 32

30 0S NTEGRATED CRCUTS M 082 M 083 M 086 TONE GENERATOR M 082 (30% Duty Cycle) 3 TONE OUTPUTS M 083 (50% Duty Cycle) 3 TONE OUTPUTS M 086 (50% Duty Cycle) 2 TONE OUTPUTS SNGLE POWER SUPPLY WDE SUPPLY VOLTAGE OPERATNG RANGE LOW POWER DSSPATON < 500 mw ~ HGH OUTPUT DRVE CAPABLTY. HGH ACCURACY OF OUTPUT FREQUENCES: ERROR LESS THAN ± 0.069% _ NPUT PROTECTED AGANST STATC CHARGES LOW NTERMODULATON PRELMNARY DATA the M 082, M 083 and M 086 are monolithic tone generators specifically designed for electronic organs. Constructed on a single chip using low threshold N-channel silicon gate technology they are supplied in.6 lead dual in-line plastic package. "BSOLUTE MAXMUM RATNGS' r. ' op stg Voltage on any pin relative to Vss (GND) Operating temperature Storage temperature +20 to -0.3 o to to 50 ~'. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is t a stress rating only and functional operation of the device at these or any other condition above those indicated in, the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DRDE~NG NUMBERS: M M 083 B M 086 B _C.~n"'\CAL DATA Dimensions in mm ~::::::: ~LJ,ne,rse''Jes issue dated /79

31 M082 M 083 M 086 CONNECTON DAGRAMS BLOCK DAGRAM!; ~:, '00 '6 F,3 CLOCK 2 '5 F,,. VSS F2 F'2 M 082 Fll M 083 F'O 3 FJ " F4 " FS F9 '0 F6 Fe F 7 ~ {] -Fll.~ {]_F r ~ {]_F'O ~EJ-{] " LEJ D-~F8 s CLOCK NPUT yoo '6 Fn CLOCK 2 '5 F'O Fll '4 Fe F9 '3 F7 M 086 F6, 2 F4 FS " F2 F3 '0 'SS "-... -G " F6 -~-D-FS EJ D-F4 ~--D-FJ F' N.C. S-2990 Voo is the highest supply voltage VSS is the lowest supply voltage * F is the highest output frequency and its musical equivalent is: C ** For the M 082, M 083 only S-99 U--Fl**. OUTPUT DRVER RECOMMENDED OPERATNG CONDTONS Values Parameter Test conditions Unit Min. Typ. Max, Vss Lowest supply voltage 0 0 V Voo Highest supply voltage V 34

32 M082 M083 M 086 ELECTRCAL CHARACTERSTCS (O C<;Tamb <;50 C;Vss=OV;Voo=+0V to+4vunless otherwise specified) Parameter Test conditions Values Min. Typ. Max. Unit Fig. V L V H nput clock, low nput clock, high t r, tf nput clock ri se and fall times 4.5 MHz 0%to 90% ton, toft nput clock on and off times C nput capacitance 4.5 MHz V OH Output high 0.75 rna VOL Output low 0.70 rna tro. tfo Output rise and fall times 500 pf load ton. to Output duty cycle M 082 DD f Supply current nput clock frequency M 083, M 086 Vss V ss+l V V OD-l Voo V 30 ns ns 5 0 pf Voo-l Voo V 2 VSS VSS+ V ns % rna khz Output unloaded. Fig. nput clock waveform Fig. 2 - Output signal d.c. loading MAX SOURCE CURRENT, 0.75mA Vo '-"-"T""-r---,-i<:-?"<""" MAX 5NK ClJ'lRENT,O,70mA t 8 50URCE v. va S 299] o SNK Vs. Vo 5-299' ~ (OPERATNG AREA) ~ (CURRENT OVERLOAO AREA) 35

33 M082 M083 M 086 Fig.3 - Output loading.4 Voo Voo M 083 s s

34 MOS NTEGRATED CRCUT MOl7 TONE GENERATOR 2 TONE OUTPUTS TTL COMPATBLE HGH ACCURACY OF OUTPUT FREQUENCES: ERROR LESS THAN ± 0.069% LOW MPEDANCE PUSH-PULL OUTPUTS it LOW POWER DSSPATON: < 400 mw NPUT PROTECTED AGANST STATC CHARGES LOW NTERMODULATON The M 087 is a monolithic tone generator specifically designed for electronic organs. Constructed on a single chip using low threshold P-channel silicon gate technology it is supplied in a 6-lead dual in-line plastic package. ABSOLUTE MAXMUM RATNGS Source supply voltage nput voltage Output current (at any pin) Storage temperature Operating temperature This voltage is referred to V ss pin voltage -20 to to to 50 o to 70 v V rna ()RDERNG NUMBER: M 087 B for dual in-line plastic package ~ECHANCAL DATA Dimensions in mm [ [ ~::::::: ~persedes issue dated /76 37 /78

35 M08l CONNECTON DAGRAM V55 CLOCK NPUT f 2 6 fl 5 flo 4 f 8 f 9 f 6 f 5 f 2 fl 3 f 7 2 f 4 "h f 3 0 VOO VGG S-9o BLOCK DAGRAM '-LOC' "NPUT 2 " f6 " " - -' G tlo, EJ EJ--- V---EJ - -EJ-- -EJ-- " (} 0 EJ--- " * f is the highest output frequency and its musical equivalent is : C ** f2 is the lowest output frequency and its musical equivalent is: C #,".- 0 /78 38

36 M087 STATC ELECTRCAL CHARACTERSTCS (positive logic, VGG= Vss -6.5 to -B.75V, Voo=Vss-9 to -0V, Vss= 4.75 to 5.25V, T amb= a to 70 D e unless otherwise specified) Parameter Test conditions Min. Typ. Max. Unit. CLOCK NPUT V H Clock high voltage Vss-O.5 Vss V V L Clock low voltage Vss-6 Vss-4 5 V DATA OUTPUTS VOL Output low voltage L= 0 ma Voo V V OH Output high voltage L= ma V ss-0.5 Vss V LO Output leakage current Vo=VSS-l0V T amb= 25 D C 0 /la POWER DSSPATON GG Supply current T amb = 25 D C 3 ma 00 Supply current T amb- 25 D C 3 6 ma 'DYNAMC ELECTRCAL CHARACTERSTCS (positive logic, VGG=Vss-6.5 to -B.75V, Voo=Vss-9 to -0V, Vss= 4.75 to 5.25V, T amb= a to 70 D e unless otherwise specified) Parameter Test conditions Min. Typ. Max. Unit CLOCK NPUT Clock repetition rate tpw. Pulse width!clock high).. tpw Pulse width!clock low) OAT A OUTPUTS = khz khz 70 ns 50 ns ROH High level output dynamic impedance Vo=Vss 0.5V kh ROL Low level output dynamic impedance,. Measured at 90% of the swing. t Measured at 0% 0 the swing. VO= VOO kh 39

37 M087 TYPCAL APPLCATON f2 40

38 MOS NTEGRATED CRCUT M089 PRELMNARY DATA 2 x 8 CROSS-PONT MATRX VERY LOW ON-RESSTANCE HGH CROSS-TALK AND OFF-STATE-SOLATON SERAL SWTCH ADDRESSNG, MCROPROCESSOR COMPATBLE The M089 2x8 cross-point matrix is realized with 6 n-channel MOS transistors. The device has been specially designed to provide switches with low on-reistance. Cross-talk and off-state-isolation are guaranteed less than -90 dbm. The device is designed for PABX applications and is fully microprocessor compatible. t is available in 6 lead dual-in-line plastic and ceramic packages. ABSOLUTE MAXMUM RATNGS* Supply voltage -0.5 to 7 V nput voltage pins 4, 5, 2, to 7 V VN-VOUT Differential voltage across any disconnected switch 0 V P tot Total power dissipation 640 mw Top Operating temperature range: for plastic o to 70 C for ceramic -40 to 70 C T 5g Storage temperature range -65 to 50 C Stresses above those listed under" Absolute Maxlmum Ratings" may cause permanent damage to the device. This is a.stress rating only and functional operation of the device at these or any other condition above those indicate in the "Recommended operating conditions" section of this specification is not implied. Exposure to absolute maxi mum rating conditions for extended periods may affect device reliability... With respect to Vss (GND) pin. ORDERNG NUMBERS: im089 B for dual -in-line plastic package ;M089 0 for dual-in-line ceramic package :'-'089 F for dual-in-line ceramic package, frit seal 4 /79

39 Moa9 MECHANCAL DATA (dimensions in mm) Dual in-line plastic package ~ '" l-~ _.n ; ~:::::::l M M Dual in-line ceramic packege frit-seal 2~253m.. tejj '6 9, mih ~ LJ Dual in-line ceramic package 0.46 [::::: : 7,4rr\j ~ 0.4"''' PO!,, PN CONNECTONS LOGC DAGRAM NA 6 O. 0, S 0, VOO 4 O. CP 3 Ei El-~r-- E2-~'---_ DATA o. 0' 06 0, 0, DATA 5 2 Ei CP OJ 0, 02 ~ VSS(GNO) N A N 0 B 03 0~ 0, S 336 0, 9 ~ NB, lj60 42

40 M089 'SLOCK DAGRAM ~ - ;) " DEC. r Os O , A B MATRX 08 DECODE N N 0 Yo X2 X, Xo DATA C SHFT REGSTER CP ~ J.J CRCUT DESCRPTON The M089 2x8 cross-point matrix is made up of 6 switches realized with low on-resistance n-channel MOS transistors. A latch maintains each switch in the previous state. Switches are addressed when both enable inputs Ef tnde2 are low. The address is loaded into a 5 bit internal shift register which holds the contents. where Xo to X 2 are used to select of 8 outputs, Yo is to select one of two inputs and 0 defines whether the addressed switch is connected or disconnected. The data bits are loaded on the high to low transition of the CP clock input. The status of the switches is changed on the low to high transition of one or both enable inputs. f more than 5 clock transitions are applied during loading of the shift register, only the last 5 data bits are loaded into the register. 43

41 089 ENABLE NPUTS TRUTH TABLE DATA NPUT TRUTH TABLE T E2 Function Data Switch status L L data load L disconnect l ~ L addressed H connect L ~ switch ~ ~ changed TRUTH TABLE FOR SWTCH SELECTON (positive logic = High, 0 = Low) The table shows the hexadecimal code for the bits Xo Xl X 2 Yo which must be loaded to address the inputs and outputs shown s N A N B F D B E C A For example to address the switch connecting NA to 05 the shift register must be loaded with the address code 0 (7) Yo D Custom options to connect, D = High () o to disconnect, D = Low (0) o 0 There are two possible custom options for the M089 chip. These implement on "all switches reset" function in two ways: Option. The "all switches reset" function could be implemented by an additional data bit in the switch register. The new 6-bit word would be made up as follows. With R low (0) the circuit would function as previously described with R high () all the switches would be disconnected in the low to high transition of one or both of the enable inputs. Option 2. The function could alternatively be implemented by modifying the enable input truth table as follows. T L --.r L H E2 L Function data load L addressed switch -.r changed H all switches disconnected 44

42 M089 ELECTRCAL CHARACTERSTCS (Tamb= 0 to 70 C for M089 B, -40 to 70 C for M089 Fl, 0, Voo= 4V to 6V) Values Parameter Test conditions Unit Min. Typ. Max. RON ON -resi stance Vi (A, S)= 3.5V V O (,S)= 3.75V 25 n Voo= 4V lo(min)= 0 ma 00 Supply current 7 ma Ll nput leakage pins 4,5 2,3 pins,9 Vi = 5V JlA ViA, ViS= 4.5V VOl, Vos=.5V 0.2 JlA pin 0 ViA, Vi8= 6V JlA VOl- VOS=.5V LO Output leakage VOl, VOS= 4.5V pins 2,6,7 0.2 JlA ViA, ViS=.5V 8,0,4 5.6 VOl, Vos= 6V ViA, ViS=.5V JlA V low Logic 0 input level All inputs V V high Logic input level All inputs 4.5 VOO V CT Cross-talk See fig. -90 db 0 Off insulation See fig db fel Maximum clock input frequency MHz T LG Lag time See fig ns TLol Lead time See fig TLD2 50 TWR Write time See fig. 3 3 JlS ~. Clock pulse width See fig JlS ns 45

43 M089 TEST CRCUT Fig. - Crosstalk measurements SAME NTEGRATED CRCUT r ~ , F r---' Y,N (RMS) r , o---'--~l ~W~g~.J ] lyrms 3 KHz. T 25 YDC 2.5VDC :'-6'J.~~~~~ (RMS) OUT L.J. 2.5vDC 2.5VDC v Fig. 2 - Off isolation measureme r---' YN(RMS) LA~,~~~F f(rms) VOUT ~... rv VRMS 3KHz T 2.5YDC 25YDC CT=20 LOG(~)dB Y'N S '0 = 20 LOG (YOUT)dB Y,N 5-336, TMNG DAGRAM Fig.3 nocl CP ENABLE ill ~~ SWTCH PATH PREVOUS STAlUS SHFT REGSTER 'WR 46

44 MOS NTEGRATED CRCUT M 06 TV MCROPROCESSOR NTERFACE.6 PWM D/A CONVERTERS, WTH 64 STEP RESOLUTON, FOR ANALOGUE CONTROLS 3 BT (892 STEP) PULSE WDTH-RATE MULTPLER D/A CONVERTER FOR TUNNG VOLTAGE. BULT N ANALOGUE SWTCH. CRT DSPLAY SECTON BASED ON A 64 x 64 FULLY PROGRAMMABLE MATRX, UNDER SOFTWARE CONTROL, WORKS WTH ANY TV STANDARD OPEN DRAN OUTPUTS RATED UP TO 3.2V MAN 5V POWER SUPPLY (2V USED FOR BAS) STANDARD 40 PN PLASTC PACKAGE The M 06 is a programmable LS device for microprocessor controlled applications in TV and industrial control fields. The M 06 uses state-of-the-art N-Channel MOS Silicon gate technology, with a single +5V power supply and TTL compatible inputs and outputs. A + 2V supply is used for bias of the analogue switch circuit built on the chip. The microprocessor interface includes a single phase clock input, a bidirectional 8 bit system bus, two strobe inputs and an interrupt request output. A total of 7 variable duty cycle output signals are avail able. After simple RC filtering these signals become the analogue outputs of the system. One blanking and three colour outputs are provided to display alphanumeric or graphic data on a CTV screen. Eight general purpose digital outputs are provided with open-drain configuration. The M 06 is available in a standard 40 pin dual-in-line plastic package. ABSOLUTE MAXMUM RATNGS* Voo Supply voltage -0.3 to 7 V V raf -- Reference voltage -0.3 to 7 V VGG Bias voltage -0.3 to 4 V V nput voltage -0.3 to 7 V Vo (off) Off-state output voltage: PO to P6; 00 to to 4 V all other outputs -0.3 to 7 V 0 Output current: all outputs except pins 25, 26, 27, 28 max. 5 ma pins 25, 26, 27, 28 max. 5 ma P tot Total package power dissipation 0.8 W Top Operating temperature 0 to 70 C Tstg Storage temperatu re -65 to 50 C Stresses above those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condition above those indicated in the "Recommended operating conditions"section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All voltage are referred to V SS= V SS2' ORDERNG NUMBER: M 06 Bl 47 4/79

45 M 06 MECHANCAL DATA(dimensions in mm) ~" ~B eo 4B t:::::::'.:::::::j CONNECTON DAGRAM V Q QO 5 36)- vgg P Vref V _ P5-0 f'ou-s P4 _ 30 P3-2 29]_ P P 27 _ - 4 PO )-- ill TA _ ~ 2/4MHz )- RC 0 2J ' Q2 52 Q3 i Q4 54 Q5 il5 Q6 06 Q7 07 R G B BLK int H5 ~ "DO RECOMMENDED OPERATNG CONDTQNS Voo V ref VGG V, VO(Off) 0 Supply voltage Reference voltage Bias voltage nput voltage Output off voltage: PO to P6; QO to Q7 all other outputs Output current: all outputs except pins 25, 26, 27, 28 pins 25, 26, 27, 28 Clock frequency (selectable) Oscillator frequency Resistance of the clock oscillator Capacitance of the clock oscillator Operating temperature 4.5 to to to to Voo max 3.2 maxvoo max 2 max 8 (pin 9atVoo ) 2 (pin 9 at Vss) to 0 0 to 30 o to 70 V V V V V V ma ma MHz MHz MHz kn pf C 48

46 M 06 BLOCK DAGRAM ~ RO 6 ---/ PWM CONVERTER ~po DO 007 R P R2 CO~~E~TER ~ P ~ PWM CONVERTER ~P2 P3 M U L T P L E X E R P4 P5 VGG Vr.f P6 g OPTON 2/4 MHz CRT HS VS R G B BLK VoO NT 8 C V /2 000Q7 49

47 M 06 STATC ELECTRCAL CHARACTERSTCS (Over recommended operating conditions Typ. values are at Tamb = 25 C, V 00= 5V; V Ref= 5V; V GG = 2V) Parameter Test conditions Values Min. Typ. Max. Unit V H nput high voltage All input pins exceqj VOO (Hs-Vs) pins (Hs-Vs) 3 Voo V L nput low voltage All inputs excepts pins ( Hs-Vs)) pins (Hs-Vs) nput leakage current All inputs except V = 0 to 5.5V 0 pin 8 </> nput bias current pin 8 V</> = 5.5V 0 70 VOL Output low voltage All outputs OL=.6mA 0.4 except pins pins OL= 8 ma pin 7 OL = 0.25 ma VOH Output high voltage pin 7 OH= ma V oo-30 Voo-45 O(Off) Leakage current All output except VO(Off)- 5.5V 0 pins pins VO(off)- 3.2V Supply current pins VOO= 5.5V 60 GG Bias current V GG- 3.2V 300 Note: The Vs and Hs inputs have Schmitt-trigger action for accepting slow transition time signals. V V /la /la V V mv mv /la /la ma /la DYNAMC ELECTRCAL CHARACTERSTCS Parameter Test conditions Values Min. Typ. Max. Unit tlo Loading time of the first byturgm the strobe display command (STA and STB both low) 26 tl Loading time of any successive byte from the end of the previous load time see fig. 24 tsetup Setup time 4 thold Hold time 4 50 /ls /ls /ls /ls

48 M 06 ig. <;-r-,6.~ / ----; ;") L 7 -=-~_: ' : ',, DO 007 ~ PESCRPTON ~ l~+~- --t---;-----~ s.tup 'hold ~ - System clock rhe cp input (pin 8) must be connected to the microprocessor clock, or to the clock oscillator pin in the ~se where the microprocessor has a built in clock generator. rhe clock signal can be 2 or 4 MHz. Pin 9 must be connected to V DD if the frequency is 2 MHz, to Vss!fit is 4 MHz. nternal registers load and read operations.,. 06 can be fully programmed by load ing a set of internal registers. fable shows the binary address code and function of each internal register. me loading of each register, as shown by fig. 2, is performed in two steps: in the first phase, the four ~it address code (DO to D3) is sent on the bus, and latched by the ST A strobe signal; in the second phase Jhe bus carries the 6 to 8 bit register content which is transferred to the addressed register by the STB ltrobe signal. When both STA and STB are in the HGH state, the content of the addressed register will be read back ~ the bus. The read operation is not allowed for registers 8 to 2. t.ble - Summary of the internal registers N ADDRESS Number DO of bit Function 0 H H H H 6 Converter n. 0 (PWM) H H H L 6 Converter n. (PWM) 2 H H L H 6 Converter n. 2 (PWM) 3 H H L L 6 Converter n. 3 (PWM) 4 H L H H 6 Converter n. 4 (PWM) 5 H L H L 6 Converter n. 5 (PWM) 6 H L L H 6 Converter n. 6 MSB (PWM) 7 H L L L 7 Converter n. 7 LSB (BRM) 8 L H H H 6 Window upper side position 9 L H H L 6 Window lower side position 0 L H L H 6 Window left side position L H L L 6 Window right side position 2 L L H H 6 CRT display control 3 L L H L S Open drain digital outputs 4 L L L H - Reset (only for testing) '5 L L L L - Not used 5 Table 2-Loading and reading of the internal registers STA STB Function H H the content of the addressed register is read back (except for RS to R2) L H address loading H L data loading L L pattern loading for CRT display

49 M 06 Fig. 2 no 0 53 ADDRESS STA.BLE DATA (LSBl STABLE. D40m ----~ _+---- ( OATA(MSB) STABLE NOTE TMNG S NOT CRTCA.l: EY RY ~p HAS NSTRUCTON CYCLE LARGER THA.N MNMUM SET UP AND HOLD TlME5 F,OR THE SHOWN OPERATON. Df A converters for analogue controls The 6 bit contents of registers 0 to 5, after a pulse-width conversion and external filtering, are used for analogue commands as volume, brightness, colour saturation, contrast, tone and fine tuning. The pulse width modulated output has a fixed period of64 microseconds and variable width. The output is open drain, can be filtered by a simple RC network and can be varied from OV to the reference voltage (3.2V max) in 26 = 64 steps. Tuning voltage Df A converter Registers 6 and 7 may be considered as a single 3 bit register. The corresponding outputs value is normally used as a tuning voltage for a varicap tuner. The conversion uses a double modulation system, in order to minimize the ripple after the filter. The 6 most significant bits (register 6) are converted using the same pulse width modulation technique as registers 0 to 5. The 7 least significant bits (register 7) generate a series of pulses with variable width and frequency (bit rate mu tipl ier). This approach greatly reduces the amplitude of the low frequency components in the output voltage, and allows an easier and more efficient filtering. The converter's output, P6, uses an internal analogue switch, operating in a push-pull mode, and switches a very precise reference voltage, which is connected to the V ref pin. The 0 volt level, in order to minimize the ground noise, is supplied through a dedicated pin V SS2, that is externally connected to ground. A 2V bias voltage must be connected to the V GG pin in order to operate the output stage in the pushpull mode. On screen display The on-screen display interface uses a vertical sync signal applied to the \is input and horizontal sync signal appl ied to the Hs input. A "vertical clock" is internally generated by dividing the line frequency Hs by a number N which defines the height of the matrix element. Assigning to N a value of 4/5/6 the height of the corresponding matrix element becomes 4/5/6 lines. The choice of one of these values of N will adapt the M 06 to display on any video standard. An internal RC oscillator, synchronized by the Hs input, gives a "horizontal clock", whose period 52

50 r ~. M 06 r... t r ~,!DESCRPTON (continued) :, ~efines the width of the matrix element. The frequency must be adjusted in order to have a width equal to /64th of the actual width of the screen. rrhe data to be displayed on the screen is normally contained in a rectangular "window". nside the \4vindow the BLK output generates a blanking signal, thus creating a black rectangular background for he image. Position, height and width of the window are programmable by loading in registers ~ a 6 bit position value of each side of the window. The value is calculated in terms of the number of ~rtical or horizontal clock pulses from an origin. :the origin (0,0) corresponds to the trailing edge of the Vs and Hs pulses and is therefore located in 'the upper left corner of the screen. Jnside the M 06, a dual 64 bit shift register synchronized by the horizontal clock, repeats the same pattern over N lines using the first shift register, while the lp can load the second one with the new pattern to be used in the next lines. Afterwards the new pattern content is transferred in parallel into the first register. The loading of the second shift register is synchronized by the j> clock. This takes 8 sequential bytes, with the timing shown in fig.. The loadin9 time for each byte is 24 microseconds. The loading begins when both STA and STB go LOW. The corresponding state is decoded as a "strobe display" command. f the "strobe display" state is terminated by the JP before th~ internal shift register is completely loaded, the remaining bits are zero-filled. The display control register (2) defines the start and the end of the display function, the combination of the colour outputs enabled (and therefore the colour of the image) and the timing signals used during the load operation. Table 3 shows the function of each bit of the display control register. No timing signals are used if the pattern doesn't change from line to line of the display (vertical or horizontal bands). n this case the pattern can be loaded asynchronously only at the beginning, and will be automatically repeated until the window is completely scanned. The timing signals must be enabled for displaying character, because the line pattern is variable and must be loaded in synchronism with the screen scan. The STA pin, normally used as a strobe input, becomes bidirectional and generates for each frame a single pulse, negative going, and approximately 45 microseconds long, N lines before the beginning of the window. This signal is used by JP to initiate the first load operation. The NT gives a series of pulses for each frame, with a period of N lines, starting N lines before the beginning of the window and stopping N lines before the end of the window. During the STA output pulse no control register loading is permitted and only the "strobe display" state is accepted. rable 3 - CRT display control register (N 2) Bit Function Logic level L Logic leval H 0 Output R (Red) Output B (Blue) 2 Output G (Green) 3 Nr. of lines each dot 4 Timing outputs NT-STA 5 Display control Available with metal option (contact local SGS-ATES sales office). 53 disabled enabled disabled enabled disabled enabled 5 (4*) 6 disabled enabled stop start

51 "MOS N T E G RAT E Del R CUlT M 08 SNGLE CHP ORGAN (SOLO + ACCOMPANMENT) PRELMNARY DATA SMPLE KEY SWTCH REQUREMENTS FOR 6 KEYS, N A MATRX OF 2 x 6 LOW TME REQURED FOR A SCANNNG CYCLE OF 576,usec. ACCEPTANCE OF ALL KEYS PRESSED TWO KEYBOARD FORMATS: 6 KEYS (SOLO)OR KEYS (ACC. + SOLO) WTH POSS BLTY OF AUTOMATC CHORDS OF THE "ACCOMPANMENT" SECTON. TOP OCTAVE SYTHESZER NCORPORATED FOR GENERATON OF 3 "FOOTAGES" MORE THAN ONE CHP CAN BE EMPLOYED WTH SYNCHRONZATON THROUGH THE RESET NPUT SEPARATED ANALOG OUTPUTS (FOR EACH FOOT) FOR "SOLO", "ACC." AND "BASS" SECTONS (SQUARE WAVE 50% D.C.) WTH AVERAGE VALUE CONSTANT NTERNAL ANT-BOUNCE CRCUTS KEY DOWN AND TRGGER OUTPUTS FOR "SOLO", "ACC." AND "BASS" SECTONS SUSTAN FOR THE LAST KEYS RELEASED N THE "SOLO" SECTON (6 OR 37 KEYS) CHOCE OF OPERATNG MODE N "ACC." SECTON - MANUAL,WTH OR WTHOUT MEMORZATON OF THE SELECTED KEYS(FREE CHORDS WTH ALTERNATE BASS) - AUTOMATC, WTH OR WTHOUT MEMORZATON OF THE SELECTED KEY (PRORTY TO THE LEFT FOR AUTOMATC CHORDS AND BASS ARPEGGO),. MULTPLE CHOCE POSSB LlTY ON THE CHORDS N AUTOMATC MODE - MAJOR OR MNOR THRD - WTH OR WTHOUT SEVENTH LOW DSSPATON OF < 600 mw STANDARD SNGLE SUPPLY OF +2V ± 5% NPUTS PROTECTED FROM ELECTROSTATC DSCHARGES The M 08 is realized on a single monolithic silicon chip using N-channel silicon gate technology, t is available in a 40 lead dual in- ine plastic package. ABSOLUTE MAXMUM RATNGS* Sou rce supply vol tage nput voltage Output current (at any pin) Storage temperature Operating temperature -0.3 to to to 50 o to 70 V V ma C C \ Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is i. a stress rating only and functional operation of the device at these or any other condition above those indicated in. the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for ~, extended periods may affect device reliability. [u This voltage is with respect to Vss (GNO pin voltage. RDERNG NUMBERS: M 08 B for dual in-line plastic package 55 /79

52 M 08 MECHANCAL DATA (dimensions in mm) Dual in-line plastic package ~muumrouooi;romro,ui:nnffijl,e.h-~ E::::::: :::::::: :: BLOCK DAGRAM PN CONNECTONS *VSS 00 MeK RESET 39 TCK ath/7th '/5h a3rd ROOT ASS A n C 0 3 F2 NPA 30 T TOA 2 29 F4 lis 3 28 l"'5' KPA 4 27 n KPS 5 26 F 6' 6 25 '8 8' 7 24 F9 4' 8 3 FlO TEST 9 2 FT **'00 0 FT VSS is the lowest supply voltage VOO is the highest supply voltage 56

53 M 08 ~ tgeneral CHARACTERSTCS ~: f The circuit comprises:.,8) 2 pins for clock input: one for the matrix scanning, the other for the incorporated T.O.S.;by connect S ing both the clock inputs to the same matrix scanning clock (000.2 KHz), the three "footages". generated are 6', 8' and 4'. ; b) 6 inputs from the octave bars (keyboard and control scanning (c) 3 multiplexed data inputs for addressing the bass selection. These inputs normally come from the out-, puts of an external memory (negative or positive logic with control inside the chip) ;d) 8 signal outputs divided by section: 3 for the "SOLO" section (6',8',4'),4 for the "ACC." section, (6' or root, 8' or 3rd, 4' or 5th, 8th/7th according to operating mode), for the bass 'e) f) g) 2 outputs for the matrix scanning 5 "trigger" and "key down" outputs: KPS (key pressed "SOLO"), TDS (trigger decay "SOLO"), KPA (key pressed" ACC."), NPA (pitch present in "ACC." outputs), TDB (trigger decay "BASS") respectively. These outputs, in conjunction with an external time constant, allow the formation of the envelope of the sustain and percussion effects. The duration of the trigger pulses is"" 9 msec. input (reset) to synchronize the device or more than one device (with the same keyboard scanning and using a single contact per key). The reset action, provided by an external circuit, is of the "POWER ON RESET" (high active) type and its duration must be "" 0.5 msec. h) TEST pin (in use it must be connected to V DD) j) 2 supply pins.. MATRX ORGANZATON (Keyboard and controls) M 08 Matrix M 08 Octave bar inputs outputs Bl B2 B3 B4 Bs B6 F Cl C2 C3 C4 Cs C6 F2 C # C2# C3# C4 # Cs # 7th OF F 7th ON = s 3rd+/3rd- F4 = 2# 0 3 # 0 4 # 0 5 # Sus!. OFF/Sus!. ON Fs El E2 E3 E4 Es Latch/Latch F6 Fl F2 F3 F4 Fs Man/Auto F7 F # "2# F3# F4# F5# 6/24+37 Fa G G 2 G 3 G4 G 5 Antibounce ON/Antibounce OFF Fg G # G 2# G 3 # G4 # G 5# ROM Low/ROM High FlO Al A2 A3 A4 A Fll Al# A 2 # A3# A4# A5# F2 B B2 B3 B4 B C is the first key on the left, C6 is the last key on the right of the keyboard.. The main feature of this chip is the possibility of formating the keyboard either with 6 keys (only "SOLO" without automatism) or separating it into two sections of 24 and 37 keys respectively ("AC 'COMPAN MENT + SOLO") with the possibility of chord and bass automatic in the first section. 57

54 M 08 B) AUTOMATC The chip recognizes in the "ACC." section only the first on the left of the keys pressed and, according to the setting of the following controls,produces a major or minor chord with or without seventh only the 4' footage but with separated outputs for root, third, fifth and eighth (or seventh if the chord is wi th seve nth). The bass section gives the bass arpeggio among root, third, fourth, fifth, sixth, seventh and eighth with pitch switching dependent on an external ROM (3 bits). n automatic mode the two octaves of the "ACC:' section inside the chip are connected in parallel both for the chord and for the bass; therefore by pressing anyone of the two keys of the same note the chip generates the same chord. The "LATCH" control stores the major chord and the bass pitches (until new keys are pressed); the modification of the chord stored (from major to minor, addition of seventh) is always possible by operating the proper controls: by releasing these controls the chord becomes major again. t is possible to delete the stored pitches both is manual and in "AUTOMATC" mode by a Latch control signal. Once again there are KPA, NPA, and TDB information; however the TDB pulse, which normally appears at each arrival of the ROM codes, does not appear if there are no pitches in the "ACC." (and bass) outputs or, in the case of alternate ba~s (in manual mode) if the codes indicate conditions of indifference. RECOMMENDED OPERATNG CONDTONS Parameter Test cond itions Min. Typ. Max. Unit VSS Lowe" supply voltage 0 0 V.. _.- VD D Highest supply voltage V 58

55 M 08 STATC ELECTRCAL CHARACTERSTCS (Positive Logic,Voo =+2V±5%, Vss= av, T amb = a to 7aoe unless otherwise specified) -,NPUT SGNALS Parameter Test conditions Min. Typ. Max. Unit V H nput high voltage Note Voo- Voo Note Note 3 Voo-2 Voo V L nput low voltage Note VSS V SS + Note 2 Vss Vss+0.6 Note 3 Vss V ss +2 Ll nput leakage current V~+4V T amb - 25<>C 0 V V V V V V 'A LOGC SGNAL OUTPUTS AON Output resistance with respect to Vss AON Output resistance with respect VOUT= Voo to VOO (driver offl V OH Output high voltage V oo-o.4 Voo VOL Output low voltage Vss+0.2 Vss+O.4 l kl! V V POWER DSSPATON.L_O_O S_UP_P y_c_u_rr_e_n_t ~~T_am b 2_5_<>_C ~L- L 30 ANALOG SGNAL OUTPUTS (the external load must be connected to V 00/2) L 4_5 ~~ OH Output current with respect Outputs loaded with Kl! to Voo/2 resistor versus V Do/ 'A OL Output current with respect Outputs loaded with to VS5 resistor versus V 0 0/2 Kl! 'A Note: Aefers only to the clock inputs Note 2: Refers only to the inputs from the external memory. "Note 3 : Refers only to the reset input. 59

56 M 08 FEATURES a) The "6/24+ 37" control chooses the keyboard operating mode, i.e. the whole keyboard dedicated to "SOLO" or 24 keys (dedicated) to "ACCOMPANMENT" and 37 to "SOLO". b) The "Man/Auto" control, which operates only in case of "ACC.+ SOLO", chooses the manual or the automatic accompaniment. c) The "Sust OFF/Sust ON" allows the storage of the "SOLO" section and handles the whole keyboard or 37 keys depending on the operating mode. d) The "Latch/Latch" similarly allows the storage of the "ACC." section and operates in "ACC.+ SOLO" only. e) The "3rd+/3rd-" which operates only in case of "ACC. + SOLO" and" AUTOMATC", changes the automatic chord generated from major to minor or viceversa. f) The "7th OFF/7th ON" adds the seventh to the automatic chord generated. g) The "Antibounce ON/Antibounce OFF" disables the antibounce circuit which is usually enabled. h) The "ROM Low/ROM High" selects between ROMs with return to "" (Low active) or with return to "0" (High active). Usually the chip is enabled for ROMs with return to "" (Low active). "SO LO" Operation n this case the chip recognizes the whole keyboard as "SOLO" and does not read the controls which concern the "ACC. + SOLO" operation. The chip identifies all the keys pressed and transfers to the outputs of each section (24 and 37 keys) the analog sum of corresponding pitches. The outputs are current generators with average value constant, therefore it is sufficient to connect the pins to one load and send the signals on to the filters. n the case of "Sustain OF F" each new key pressed or released is accepted or deleted in a time';;;;; 576 "sec. n the case of "Sustain ON" the chip has a different operation according to whether the new key (keys) is pressed or released: each new key pressed is always accepted in a time';;;;; 576 "sec., whereas each key released is deleted with a delay of 73 msec. and only if there are still keys pressed. n fact, if after the 73 msec. there are no keys pressed, the last key (or keys) released remains stored until new keys are pressed. n this mode it is possible to have Sustain, with external envelope shaping, for the last keys (or key) released. The pitch envelope is controlled by a D.C. signal KPS (any key pressed) and there is also an A.C. signal TDS (trigger decay "SOLO") which provides a pulse whenever a key is pressed. An appropriate antibounce circuit, inside the chip, solves the problems associated with the keyboard contacts. "SOLO + ACCOMPANMENT" Operation n this case the chip identifies the "ACCOMPANMENT" on the first 24 keys on the left, and the "SOLO" on the remaining 37 keys and reads all the controls which concern the "ACC." section. The "SOLO" function is identical to "6 keys" mode, but for the "ACC." section there are two possibilities: A) MANUAL The chip identifies which keys are pressed in the "ACC." section, and transfers to the "ACC~ outputs the analog sum of the corresponding pitches. The "ACC." section is fully independent of the"solo"section and the signals(if there is no "LATCH") remain at the output only while the keys are pressed even if there is "SUSTAN ON". 60

57 [ M 08 f The "BASS" section gives at the bass output an alternating bass between the first on the left and the ~ 'first on the right of the keys pressed in the "ACC." section; the pitch switching timing is dependent on!. an external ROM (3 bits). ~. The "LATCH" control stores the last keys released and the output signals, including the bass output, ~ remain until new keys are pressed. t The TDB (trigger decay "BASS") output gives a pulse corresponding to every output change; there are f also two D.C. signals, KPA (any key pressed accompaniment) and NPA (pitches in output accompani ~ ment) relative only to the "ACC." section. ~ The first of these signals (analogous to KPS) concerns the keyboard and does not consider the ~ "LATCH" condition. r,' The second on the contrary concerns the "ACC." output and considers the "LATCH" condition. BASS TRUTH TABLES, ~EGATVE LOGC External Memory Code C B A Bass Arpeggio Output (Automatic mode) Alternate Bass Output (Manual mode) No change No change 0 Root st on the left 0 3rd -- - a 0 4th ---, 0 5th st on the right, 0 0 6th ---, 0 0 7th a 0 8th --- ~STVE LOGC C External Memory Code B A Bass Arpeggio Output (Automatic mode) Alternate Bass Output (Manual mode) No change No change 0 0 Root st on the left 0 0 3rd th th st on the right 0 6th --- a 7th --- 8th --- 6

58 M 08 DYNAMC ELECTRCAL CHARACTERSTCS Parameter Test conditions MASTER CLOCK NPUT fi nput clock frequency KHz t r, tf nput clock rise and falf time KHz 40 ns 0% to 90% ton. toff nput clock ON and OFF times 000 KHz 500 ns T.O.S. CLOCK NPUT fi nput clock frequency KHz t r tf nput clock rise and fall times KHz 40 ns 0% to 90% ton. toft nput clock ON and OFF times 2000 KHz 250 ns TDS and TDB OUTPUTS ton Pulse duration 000 KHz 9.26 ms t r tf Outputs rise and fall times 000 KHz 00 ns 0%0 90% NPUT CLOCK WAVEFORM on

59 M 08 FREQUENCY RANGE OF EACH OCTAVE (6', 8', 4' footages) ( r B c B C B C l Jc 246, ,2093 8' C B C B C 8 C ~' ,486 B C B C 8 C 8 C B~l- B3 B4 B5 86 ACe. SECTON SOLO SECTON 5 JJ69 CONNECTON OF THE KEYBOARD AND CONTROL SWTCHES st ac T AVE on THE lef T LAST KEY 2nd OCTAVE 3rd OCTAVE 4th OCTAVE Sih OCTAVE! CONTROLS ~t4 L~ t4 Ll Lj U t tj~ OCTAVE BAR ) Ace. SECTON SOLO SECTON (2 octavps = 2J. keys) ( 3 octaves = J7( 36. )keys) ilote: The switch "OPEN" corresponds to "KEY NOT PRESSED" or "CONTROL N THE FRST CONDTON" (see the drawing "MATR X ORGANZATON"),, typcal APPLCATON... "'00 f l' "., Fi TO T2 '0 r ln " j,. 3 f---- L l.. " :: SOLO OUTPUTS ~_ L---o.. '. ' 8t/?h --. ~(.---~- ~ ::::;: OU~~~TS f : a 6'/FlOQl -L-o 8ASS OUTPUT 5 ~ f)!; KPi m 2., f f" --~---j" 63

60 M 08 TMNG DAGRAMS.ES~~ l' ----' 2 -' L ~ L Note: MCK is the master clock input (matrix scanning), <{J, <{J2, <{J3 are internal phases to generate FT -;- FT2. RESET ~ LJ LJ LJ LJ LJ LJ LJ LJ LJ LJ LJ LJ LJ LJ Lr- S-JJ L.J L Note: The matrix scanning starts (after the power on reset) at the second arrival in output of FT (0) from Bl to B6 i~ continuous sequence. 64

61 NTEGRATED CRCUTS M20 M BT - NON VOLATLE RANDOM ACCESS MEMORY PRELMNARY DATA 256 x 4 ORGANZATON, FULLY DECODED OPERATNG MODES: READ, MODFY MODFY MODE PERFORMS SMULTANEOUS WRTNG AND ERASURE ON THE ADDRESSED WORD NPUT LATCHES FOR ADDRESSES AND DATA N OUTPUT DATA LATCHED ACCESS TME: M 20-2: 450 ns - M 20: 700 ns WORD MODFY TME: LESS THAN 00 msec. END OF MODFY OPERATON S NDCATED BY A FLAG (MODFY END) 04 MODFY CYCLES PER WORD DATA RETENTON ONE ORDER OF MAGNTUDE HGHER THAN MNOS TECHNOLOGY N-CHANNEL, S-GATE, DOUBLE POLY-SLCON MOS TECHONOLOGY TL-COMPATBLE, OPEN DRAN OUTPUTS POWER SUPPLY Voo= 2V ± 0%,Vpp= 25V ± 5% LOW POWER CONSUMPTON: 300 mw PEAK POWER FROM V pp (DURNG WRTE OPER ATON ONLY) 350 mw ACTVE POWER FROM Voo STANDBY POWER LESS THAN 00 mw M 20 is a non volatile memory which the user can consider as a RAM with a fast access time and an slower write cycle.the device operates with an address strobe control (AS) and has no limit on the _,,,mum period of AS. The AS control performs the Chip Select (CS) function as well; the device is _-:see!cte!d (standby mode) by a high level on AS. Both read and modify cycles begin on the falling edge if R/W remains true, while AS is active, a read cycle occurs; if, instead, R!W is false while AS is a modify cycle starts. Data on the data bus are latched during the rising edge of R/W, then an incircuitry performs a comparison between "old", and "new" data and, according to the result, or erases or leaves unchanged each single bit of the word. f writing is necessary on one bit and an on another, both operations are performed simultaneously. After the rising edge of R!W, add resdata are latched internally and no external holding is necessary during the modify time. Since time lengthens during the device lige, the "modify end" control, which outputs a high level at of the cycle, can be used to speed up system operations. As long as ME is low the device is indisconnected from buses and controls. The device is available in a-lead dual in-line ceramic (metal seal) and ceramic package (frit seal). MAXMUM RATNGS nput voltage Total power dissipation Storage temperature range Operating temperature range -0.5 to to 50 o to 70 lidersf!df!s issue dated 9/79 M 20 M 20 M 20-2 M 20-2 F for dual in-line ceramic package (frit seal) Dl for dual in-line ceramic package (metal seal) F for dual in-line ceramic package (frit seal) D for dual in-line ceramic package (metal seal) 65 /79

62 M20 M MECHANCAL DATA (dimensions in mm) Dual in-line ceramic package metal-seal ~ ~ ---L.ll~ ~ i 23. ~.. ~ R 7.62 PN CONNECTONS AJ '8 GNO A2 A' AS A7 AD.. 'DO AS '7 'S.. '4 'J " " '0 A4 RW ME DO O. OZ OJ 'pp DC AND OPERATNG CHARACTERSTCS Vpp= 25V ± 5%) Parameter Test conditions Min. Values Typ. Max. Unit 00 Voo supply current ppl Vpp supply current 002 Standby Voo supply current pp2 Standby V pp supply current V H nput high voltage V L nput low voltage VOL Output low voltage L-.6rnA Ll nput load current LO Output leakage current rna 2 rna 0 rna 5 rna V 0.6 V 0.4 V 0 la 0 la 66

63 M20 M ~C CHARACTERSTCS Parameter Min. M 20-2 Max. Min. M 20 Max. Unit tacc Access time from address strobe 450 tasl Address strobe active time 450 tash Address strobe inactive time 60. toff Output buffer turn-off delay 00!s Set-up time 20, th Hold time 80 twr Write time ( ) 2 00 td AS to Am delay (2) (3) (4) : tp Modify pulse width (3) (4) 200 tsw A/W to AS rising edge 200 rtd2, ME turn-on delay 00 otes: 700 ns 700 ns 300 ns 50 ns 40 ns 50 ns 2 00 ms ns 300 ns 300 ns 200 ns U twr max is 2 ms for the first 0 modify cycles and increases to 00 ms according to Figure. n R/W is internally disabled up to to min but can change before to min and even before the falling edge of AS. ~ f td.; td max then DOUT remains floating and there is no conflict between DOUT and DN; in this mode, DN can be stable within tasl min; otherwise it must be ""'ere ttr is the transition time for the data bus. ' t must be tp + to ;;" tasl min' tp toff + ttr + ts ~ig. - Plot of modify time VS. number of modify cycles ~ 0' NLJ04BER Of MODFY CYCLE.S 67

64 .,20., 20-2 TMNG WAVEFORMS Read Cycle ADD tasl k=============~~--,"-n-t;;;- ~,--_... -.L.~ -~ tol x, t ---- o OUT, t OFF. ----, /2 Write Cycle AS ~ ADD =* ~ - ~ ts... th to t? :: i tp._- ; ~ ~, " OOUT ME ':"OFF~ VAllO "'-l -:)., 4- ~ ts STABLE. th -- twr }---/ s- 2974/3 * The first negative edge of AS following the end of a modify cycle must commence at least tash after the positi~ edge of ME.. 68

65 r ~: ftos NTEGRATED CRCUTS M42 M42A ~ r ~ " ptjad SO-BT STATC SHFT REGSTER ~." SNGLE VOLTAGE SUPPLY: Vee = 5V ± 5% ~ DC to 3 MHz OPERATON GUARANTEED FULLY TTL COMPATBLE t.. FULLY DC OPERATON ~. SNGLE LNE CLOCK. ' PN-FOR-PN REPLACEMENT for MK 007P-TMS LOW POWER DSSPATON: 250 mw (TYP.) NPUT GATE PROTECTON " M42A S A HGH SPEED SELECTON the M42 and M42A are quad 80-bit fully DC shift register constructed on a single chip using very low ~reshold N-channel silicon gate technology which allows high speed (3 MHz guaranteed) and fully TTL ompatibility without using any external resistor. ~h of the four 80-bit registers.has an independent input, output and recirculate control. The single iock line is common to all four registers. ~ansferring data into the register is accomplished when the clock is high (logic " ") Shifting of data k:curs when the clock goes low. Output data appears on the negative going edge of the clock. ",en the recirculate line is high, data recirculates, while input is inhibited. When data is entered, the jik:irculate line is at logic "0". ~put data attain the same logic state that was shifted into the register 80 clocks prior. Available in te-ead dual in-line plastic or ceramic package.,. MSOLUTE MAXMUM RATlNGS* Supply voltage nput voltage on any pin Storage temperature range Operating temperature range -0.5 to 7 V -0.5 to 7 V -65 to 50 o to 70 " (.e Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is ~ a stress rating only and functional operation of the device at these or any other condition above those indicate in [.' the "Recommended operating conditions" section of this specification is not implied, Exposure to absolute maxif mum rating conditions for extended periods may affect device reliability. r ; ~RDERNG NUMBERS: 42 B for dual in-line plastic package 42 0 for dual in-line ceramic package 42A B for dual in-line plastic package,42a D for dual in-line ceramic package rsedes issue dated 9/ fl9

66 M42 M42A MECHANCAL DATA (dimensions in mm) Dual in-line plastic package for M42 D and 42A D Dual in-line ceramic package for M42 B and M42A B '... " PN CONNECTONS BLOCK DAGRAM (one of four shown) OUTPUT Vee ~EcrRCUlATE 2 " NPUT 4 NPUT 4 RECRCULATE 4 OUTPUT 2 3 OUTPUT' REe RCUlATE N,C. NPUT 2 CLOCK OUTPUT] 0 NPUT] GND 9 RECRCULATE J CLOC,, o ~ ~ ~ : : NPUT l OUTPU,J : :! RECRCULATE f L J

67 ,.,42 M42A 'TRUTH TABLE (positive logic) Recircu late nput Function "0" "0" "" "" "0" "" "0" "" "0" is written "" is written Recirculate Recirculate "0" = OV, "" = 5V STATC ELECTRCAL CHARACTERSTCS (Vee= 5V ± 5%, otherwise specified) T amb= a to 7aoe unless Parameter Test conditions Values Min. Typ. Max. Unit V H. nput high voltage VL. nput low voltage VOH Output high voltage OH=-OO ia VOL Output low voltage OL=.6mA Ll. nput leakage current cc Supply current Vi = Vee These parameters apply to all inputs including clock,.. Typical values at T amb= 25 C and Vee= 5V, 2 Vee V V 2.4 V 0.4 V 0 ia 48 ma DYNAMC ELECTRCAL CHARACTERSTCS (Vee= 5V ± 5%, Tamb = a to 7aoe unless otherwise specified) Values Parameter Test conditions Unit Min. Typ. Max. f Clock repetition rate 3 MHz ~pwl Clock high pulse width 0 ns ~pwo Clock low pulse width 220 ns trl tf Clock rise and fall time 5 lis tsetup Setup time 00 ns thold Hold time 80 ns tsr Recirculate setup time 00 ns thr Recirculate hold time 80 ns tor, tof Delay time to rise and fall TTL load for M42 type 230 ns CL=0pF for M42A type 60 ns C'R Recirculate input capacitance Vi = OV f = MHz 8 pf CtP Clock capacitance Vcp=OV f = MHz 2 pf 7

68 .42 M42A WAVEFORMS CLOCK.5V.5V 0"0 tpwl tpwo // DATA OUTPUT /.5V RECRCULATE.5V \ L /2 72

69 MOS NTEGRATED CRCUT M47 3-BT LATCH PEDAL SUSTAN PRORTY OF THE FRST LEFT PEDAL PRORTY PEDAL FREQUENCY MEMORZATON TRGGER OUTPUT FOR ENVELOPE CRCUTS CHOCE BETWEEN TWO DFFERENT NPUT FREQUENCES ( MHz or khz) ANT BOUNCE NTERNAL CRCUT ON BOTH TOUCH AND RELEASE STUATON STANDARD POLYPHONC KEYBOARDS P-CHANNEL SLCON GATE PROCESS The M 47 is a monolithic integrated circuit for pedal sustain specifically designed for electronic organs and other musical instruments. Constructed on a single chip using P-channel Silicon Gate technology it is supplied in a 24-iead dual in line plastic package. ABSOLUTE MAXMUM RATNGS* Source supply voltage nput voltage Output current (at any pin) Storage temperature Operating temperature -20 to 0.3 V -20 to 0.3 V 3 ma -65 to 50 C o to 70 C * Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All voltag~ values are referred tovss pin voltage. ORDERNG NUMBER: M 47 B MECHANCAL DATA Dimensions in mm. [::::::::J " ~Supersedes i~sue dated 0/ /78

70 47 CONNECTON DAGRAM BLOCK DAGRAM T2 TJ '55 ". fp O " T 22 4 f2 2 T3 T4 MODE T5 'GG T6 t. T7 Ts TO 0 ill Ti ill "Tii 2 Til S-2 GENERAL CATACTERSTCS The circuit comprises a) 3 pins for input pedals b) clock pin for input frequency c) input for MODE selection d) 5 frequency outputs e) output for trigger sustain (TS) f) output for trigger percussion (TP) g) 2 supply pins DESCRPTON OF OPERATON The first negative front, which is obtained by pressing any key, starts a delay circuit whose duration is a function of the key pressed and varies from 4 to 8 ms in normal mode (with the MODE input at V 55 and f l = 500 khz or with the MODE input at VGG and f l == 2 MHz (note )). f the key is released before this delay time has passed, it will not be memorized. Releasing the key retriggers the delay circuit, and not until the end of the delay will any further keys to the right be accepted, unless the new key was already pressed before the release of the first key then the new key is accepted immediately. Any key to the left will be accepted immediately it is pressed. Re-pressing the same key will output the same frequency but with a jump of phase as the internal counters will be reset to zero. When a pedal is depressed, the corresponding frequency (square wave, 50% of duty cycle) in 5 octaves is present in parallel at the 5 outputs. These outputs remain when the pedal is released, until a new pedal is depressed. When two or more pedals are depressed, only the left one is accepted (corresponding to the lowest, frequency). A TP output pulse is present whenever a pedal with priority is depressed. f the pedal is again depressed, successive TP pulses are generated.. A pulse appears at the TP output if, when two pedals are depressed, the left one is released. The TS output is activated only when one or more pedals are depressed. An internal circuit provides bounce suppression on this output. Note : With MODE at Vss and f l == MHz the time is halved (2 to 4 ms) With MODE at VGG and f l == MHz the time is doubled (8 to 6 ms). MODE OF OPERATON f the MODE input is connected to V 55, the input frequency must be khz. f the MODE input is connected to V GG, the input frequency must be MHz. 74

71 M47 STATC ELECTRCAL CHARACTERSTCS (VGG = -6 to -8V, Vss= OV, T amb = 0 to 70 0 e unless otherwise specified) Parameter Test conditions Min. Typ. Max. Unit V H nput high voltage Vss-l Vss V V L nput low voltage VGG Vss-5 V RON Output resistance Vo=Vss-V to Vss.6 KH 0(0) Output leakage current V=V H, Vo=Vss-l0V T amb= 25 C 0 /la L nput leakage current V=Vss-4V T amb= 25 C 0 /la GG Supply current Tamb= 25 C rna DYNAMC ELECTRCAL CHARACTERSTCS (VGG= -6 to -8V, Vss=OV, T amb:;: 0 to 70 e 0 unless otherwise specified; f l = MHz if MODE input is connected to V GG ; f l = khz if MODE input is connected to V ss ). Parameter Test conditions Min. Typ. Max. Unit Notes to nput frequency "" time 50 ns tla t2a tlb t2b nput frequency positive half period 0.8 /ls -3 nput frequency negative half period 0.8 /ls -3 nput frequency postive half period ns 2-3 nput frequency negative half period ns 2-3 ds Delay time of TS ns 3 tdp Delay time of TP 0 /ls 3 tp Width of TP 0 22 ms 3 Notes: ) With MODE connected to Vss 2) With MODE connected to V GG 3) All these delay and width times are measured at 50% of the swing. 75

72 47 OUTPUT FREQUENCES (Hz) nput ' T T T T T T T T T T T T T ' Outputs 4' 8' 6' E TMNG WAVEFORMS NPUT FREaUENt ( T. '--- J \..._-----/ ~;- TP, ~ ClUTPUT Qfallf t., " n order tq obtain memorization the key must be pressed for more than Tp/2. f the key is pressed twice for a time less than Tp only a single percussion trigger Tp output will be available. 76

73 M47 TYPCAL APPLCATONS Typical application circuit HBF 40" Dr-- DTiO! n L.,..:5.6kl U, "n.q '-"PF ~okn7l V55 MODE -----,. To the t,lle'rs f-+-t ~,,' 22k Circuit for a 25 pedal system using the M 47.2v ---knf j~nf t ~nf T... ' ~-- ~~=====~'=~=-==_~7C~ "v " ---~=~~c. r",c~ '''"OC~'~2 t C'"" 77

74 l-s NTEGRATED CRCUT, l M 90 PRELMNARY DATA ~6 KEY KEYBOARD ENCODER AND LATCH ; ANTBOUNCE AND ANTNOSE CRCUTRY t NTERLOCK PREVENTS NCORRECT SELECTON t OPERATES WTH SNGLE POLE PUSH-BUTTONS t SELECTON OF PROGRAM AT POWER ON MUTNG OUTPUT AVALABLE DURNG PROGRAM CHANGES AND POWER SUPPLY SWTCHNG '- STEP-BY-STEP PROGRAM CHANGE NPUT KEYBOARD LOCKNG.. OUTPUTS DRECTLY COMPATBLE WTH M 93 (ELECTRONC PROGRAM MEMORY), M 92 (7-SEGMENT DECODER DRVER), H 770//2/3 (QUAD ANALOG SWTCHES) The M 90 is a monolithic integrated circuit which automatically scans an up to 6 Key keyboard, gen rating continuous sequential pulses on X outputs and detecting key closure on Y inputs. A key closure is retained as valid when the key remains closed for all the time corresponding to one scan pulse (i.e. when the bounce is over). ~en it occurs an internal flip-flop is set but the key closure is accepted only if it is detected on a ;.cond scan cycle. At this point a 4 bit word corresponding to the key closed is internally latched and a pulse is available on the Muting output. "uring the time this pulse lasts, no other key closure will be recognized. The new output code follows!he Mute signal with a delay. " the timing for the circuits is determined by the clock oscillator whose frequency is externally fixed ~ an RC network. the M 90 also includes a "step-by-step" program change input that, when connected to V ss (GND. ~ances by one the selected channel and a Lock which blocks the circuit on the last selected channel. Jhe circuit is produced in N-channel silicon gate technology and is available in a 8 pin dual in-line ~astic package. ABSOLUTE MAXMUM RATNGS * :Vo;* V VO(Off) Jo :Ptot :Tstg Top Supply voltage nput voltage Off state output voltage (pins ) Output current Total package power dissipation Storage temperature Operating temperatu re -0.5 to 20 V -0.5 to 20 V 20 V 5 ma 500 mw -65 to 25 C o to 70 C, Stresses above those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. This is : a stress rating only and functional operation of the device at these or any other condition above those indicated in ~ the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ~. All voltage are referred to Vss pin voltage. ~RDERNG NUMBER: M 90 B ~ 79 4/79

75 90 MECHANCAL DATA (dimensions in mm) PN CONNECTONS OUTPUTS NPUTS " Xl '8 VSS(GNO) " Voo ",. Po X4 " Pc V,,t" ~PB v, [. 3 Y3 [, ~PA ]MUTE 2 OUTPUT YG [ 8 ' JOSCLlATOR STEP BY-STEP [9 NPUT 0 ~LOC.K NPUT ~- )08 BLOCK DAGRAM >-<>- : y X ') X2.2 HANTlOUNCE AND ANTNOSE X3 3 4 BT ~ ~ >--- AOORESSAlE 4 COUNTER t-- P X4 4 KEVBOARD AND f BUFFERS -- LATCH 5 SCANNER PC ENCODER AND AND DELAV NTERLOCK.r 6... V4 8 t -- V3 7 L V2 6 SUPPLV OSCLLATOR V CONTROL STEP BY 5 TEP>-ly ) LOCK ON/OFF f MUTE ~ ~, ~ 7 Yeo st 47kn.0.8 to 3.S' '55 SolO"~... PC 80

76 M 90 ECOMMENDED OPERATNG CONDTONS 'DO Supply voltage 0.8 to 3.5 V nput voltage o to 3.5 V " ~Ci(Off) Off state output voltage (pins ) max 3.5 V Output current max 2 rna P 'OP Operating temperature o to 70 C t Timing resistor 8 to 47 Kn 't Timing capacitor to 330 nf n-atc ELECTRCAL CHARACTERSTCS (Over recommended operating conditions) ", Values at 25 C Parameter Test conditions Unit Min Typ. Max.. ~H' High level input voltage pins 5, 6, 7, 8, 9,0 3.5 V ~L Low level input voltage pins 5, 6, 7, 8, 9, V JH High level input current Voo~ 3.5V, VH~ 3.5V 0 /'A,. pins 5,6,7,8,9,0, 'L Low level input current Voo= 3.5V, VL~ 0.8V rna, r pins 5,6,7,8,9,0, ~OH High level output voltage Voo~ 0.8V OH~ - rna, 2.4, pin 2! VOO= 0.8V OH= - rna, 4.. pins 3.4,5,6 V ~OL Low level output voltage Voo= 0.8V OL~ 0.8 rna 0.4, pins,2,3,4, it t Voo~ 0.8V OL~ 2 rna, 0.4 ;.. pins 3, 4, 5, 6, i V ~(Off) Output leakage current Voo~ VO(off)~ 3.5V, 20 /,A pins,2,3,4, fo Supply current Voo= 3.5V 8 rna (all inputs and outputs open) ~ 8

77 M 90 TRUTH TABLE Key Connection Output code (positive logic) PA PB PC PO Xl - Y L L L L 2 Xl - Y2 H L L L 3 Xl - Y3 L H L L 4 Xl - Y 4 H H L L 5 X2 - Y L L H L 6 X2 - Y2 H L H L 7 X2 - Y3 L H H L 8 X2 - Y 4 H H H L 9 X3 - Y L L L H 0 X3 - Y2 H L L H X3 - Y3 L H L H 2 X3 - Y 4 H H L H 3 X4 - Y L L H H 4 X4 - Y2 H L H H 5 X4 - Y3 L H H H 6 X4 - Y4 H H H H DESCRPTON Pins, 2, 3, 4-X, X 2, X3, X4 outputs The internal open drain transistors on these outputs are sequentially switched on. - [ TYPCAL X OUTPUT Pins 5, 6, 7, 8-Y, Y2, Y3, Y4 inputs These inputs correspond to the columns of the keyboard matrix. When a key is pushed, one of the ~ output signal is present on one of the 4 rows, putting a low level on the Y input. i An interlock circuit rejects more than one key pressed at the same time.' To increase the noise immunity of the system and to avoid bouncing problems, the key closure is corj side red valid only when it is present for all the time corresponding to the scan pulse. With this systerri spurious noise signals are also rejected.j Another increase in the noise immunity is given by detecting key closure over two consecutive scannillllj cycles..~ 82 4

78 M 90 'DESCRPTON (continued) After the key bounce time, the acceptance time of a command is between 35T and 63T, where T is the period of the clock pu se. When any input is open it is pulled-up to logic H by an integrated MOS load of about 50 Kn and protected by a diode. Voo PULL-LF RES5TOR O.2lfi TYPCAL Y NPUT.8kfi NPUT PAOT. DODE f Pin 9 - Step-by-step program change This input advances by one the previously selected channel every time ti is connedted to ground. This input can be considered as a 7th key and follows all the rules of command acceptance time and partially of interlock. The unput is pulled-up to logic H by an integrated resistor of about 50 Kn ; if the input is not used, it should be connected to Voo. Pin 0 - Lock f this input is connected to Vss (GND) the circuit is locked on the selected channel. f the input is not used, it must be connected to V 00' Pin - RC network (clock oscillator input) An internal clock provides all the timing for the circuits. The frequency of the clock oscillator is controlled by two external components, resistor R t and capacitor Ct. The period of the clock pulse is approximately given by T = RtCt. The oscillator works in the following way: assuming the capacitor C t is discharged, the resistor R t charges the capacitor till an internal threshold is reached. At this point the capacitor is discharged by an internal transistor. Afterwards the internal transistor is switched off and the cycle can restart. With R t= 22 Kn and C t= 39 nf a clock frequency of about 800 Hz is obtained, corresponding to a scan cycle of the keyboard of about 40 ms. n these conditions the mute signal will be present for about 00 ms before the program changing and will last 300 ms. 83

79 M 90 Pin 2 - Mute The mute signal is available as a high level output (source follower transistor). t is present during power ON/OFF and program changes. W~t_ When a command is given the Mute signal and the program information are available in the following way: COMMAND ACCEPTED MUTE PROGR CHANGE PA.PB.PC.PD. 2ST 80T +--.,...-_... :- 2~OJ ~ The Mute signal is not available when the same program is selected again. Pins 3, 4, 5, 6 - PA, PB, PC, PO outputs These static outputs select the program according to the truth table. They interface directly with the inputs of M 93 (Electronic Program Memory), M 92 (7 segment Decoder/Driver), H 770//2/3 (Quad Analog Switches). The program is internally selected at power ON. VOD TVPCAL OUTPUT '-]0" 84

80 0S NTEGRATED CRCUT M 9 ON-SCREEN TUNNG SCALE AND BAND DSPLAY DGTAL TUNNG BAR DSPLAY WTH MNMUM EXTERNAL PRESETS ON-SCREEN DSPLAY OF THE BAND VERTCAL POSTON ON THE SCREEN EXTERNALLY ADJUSTABLE AUTOMATC DSPLAY AT SEARCH COMMAND DESGNED FOR USE WTH THE M93 ELECTRONC PROGRAM MEMORY The M9 is a monolithic integrated circuit designed to display on the screen of the television receiver a 'Variable length strip corresponding to the voltage applied to the varicap tuner. A variable number of rectangles symbolizing the selected band can also be displayed. The circuit operates in conjunction with the M93 Electronic Program Memory, from which it takes the voltage and band information in a digital serial mode. The 7 most significant digits of voltage information coming from the M93 are digitally converted into a 64 step variable pulse width giving either positive and negative polarity outputs for easy and versatile interfacing. The variable length strip is displayed over lines of a half frame picture with nine vertical graduations of 3 lines. The vertical position of the strip can be adjusted with an external potentiometer over the whole screen. The 2 digits of band information determine the number of rectangles appearing on the scre<!n under the ~uning strip. The rectangles are displayed over lines of a half frame picture. Automatic display is provided when the Electronic Program Memory is in the Search Mode; display on command is always possible. :fhe M9 is constructed in N-channel silicon gate technology and is available in a 6 pin dual in-line plastic package. ABSOLUTe MAXMUM RATNGS* Vcc ** Supply voltage -0.3 to 20 V V nput voltage -0.3 to 20 V nput cu rrent -5 ma VO(et!) Off-state output voltage 20 V 0 Output current (except pins 2-3) 5 ma (pins 2-3) 5 ma i»tot Total package power dissipation 500 mw T 5g Storage temperature -65 to 50 C Tep Operating temperature o to 70 C '. Stresses above those listed under" Absolute Maximum Ratings mav cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condition above those indicated in the "Recommended operating conditions" section of this specification is not implied. Exposure to absolute maximum, rating conditions for extended periods may affect device reliability.,. All voltages are with respect to VSS (GND. ORDERNG NUMBERS: M9 B

81 M 9 MECHANCAL DATA (dimensions in mm) 7""" ~ ~ P0C' ( PN CONNECTONS HORrz. 5VNCH. 'f 'ss (GNO) ---- VERTCAL HORZ.5VNCH. 0 POSTON FELD BLANKNG OUT DSPLAY TME /2 CLOCK FREQUENCY OUT 4 VERT. SYNCH. 3 " DSPLAY OUT DSPLAY OUT CLOCK OSCll. VDD BAND DSPLAY ENABLE 0 DATA f FROM CLOCK M 93 latchng TME CONSTANT ~-J2~m BLOCK DAGRAM -;-2 CLOCK 64 STEPS SYNCHRONOUS COUNTER BAR AND BAND OUTPUT DELAY TME JDD2~ HORl. FlYBACK /--_ BAND DSPlAY ENABLE rw , \-- DATA EPM L- ~r_ l-ckepm BlANKNG OUTPUT LATCHNG TME T CONSTANT 86

82 M 9 ~RECOMMENDED OPERATNG CONDTONS Parameter Min. Typ. Max. Voo Supply voltage V 'V nput vo tage 4.5 V Vo (off) Off-state output voltage 4.5 V 0 Output current (all pins except ) * rna (pin 6) 3 ma (pins 2-3) 0 ma f Clock frequency MHz Top Operating temperatu re 0 70 C.f'tot Total package power dissipation 500 mw 'Cg Capacitance at pin pf.c6 Capacitance at pin pf C 5 Capacitance at pin nf C4 Capacitance at pin 4** 0 2 JiF,R4. 5 Resistance at pins Kn * 04 The output current of pin 4 is internally limited. :.. C 4 Values up to 00 JiF are allowed using a Kn resistor in series with pin 4. STATC ELECTRCAL CHARACTERSTCS (over recommended operating conditions)' Typical values are at Tamb = 25 C, Voo= 3V. Values Parameter Test conditions Pins Unit Min. Typ. Max. V L Low level input voltage Voo=.5 to 4.5V V VH High level input voltage Voo=.5 to 4.5V V VOL Low level output voltage Voo=.5V OL=0mA 2-3 V Voo=.5V OL= ma 3 V VT Threshold voltage Voo=.5 to 4.5V V nput current V = 4.5V 0 la 0 (off) Off-state output current Voo = 4.5V la 00 Supply current Voo= 4.5V 25 ma 87

83 M 9 DYNAMC ELECTRCAL CHARACTERSTCS (Tamb= 25 C) Parameter Test conditions Min. Values Typ. Max. Unit ttlh. tthl to Transition time Delay time Pins 2-3 See fig ns 50 ns TYPCAL APPLCATON Fig. EPM M 93 S~S n on - DATA 80n LATCHNG... -c::::r-t--j CONSTANT VERT. HORZ. HORZ. SYNc. SVNC. SVNC. vss-...j...f CLOCK 0 3 M9 VSS (GND) >.5kO OUT FELD BLANKNG WRTE BLANKNG CLOCK / OSCLL. l'cn >t5kn VERTCAL POSTON t DSABLED lljfto-lol-lf ~'n4 kn 200n s ;-]2"" ' 'F O '00)JF Fig.2 Fig.3.2V 3LNE5 PN THE LNE5 CORRE5POND TO A HALF FRAME PN ~lt-'delay!~ - 2 ~< pF,.! ~ S-2:U ~ 88

84 M 9 DESCRPTON Pins,2 - Horizontal synchronization Two Horizontal sync inputs are provided to allow for positive or negative pulses from the TV receiver. Pin is designed to accept a positive pulse de roved from the line flyback through an interface. The circuit is triggered on the negative edge of the incoming pulse. Fig.4-Pinl > 3.5V n TRGGER EDGE <O.8v-- L The negative flyback pulses must be applied to pin 2. n this case the circuit is triggered on the positive edge of the pulse. Fig. 5 - Pin 2 >3.5V -U- < O.8V. TRGGER EDGE The display is delayed for a time corresponding to 32 clock periods after the triggering. With a clock frequency of.8 MHz the delay is 9 ij.sec. When pin is used, pin 2 must be connected to Vss (GND), when using pin 2, pin must be at V DD. Pin 3 - Field blanking output An open drain transistor is disabled during the lines which correspond to the display of the tuning scale and band information. This makes it possible to write the tuning scale and the band identification rectangles,on a dark or alternative colour area. The signal is present for the full line period. Pin 4 - Display time input The display is automatically enabled when the M93 electronic program memory is in the Search mode. The RC network applied to pin 4 determines the time the display will last after a station is found. When identification occurs the capacitor is unclamped and allowed to charg no the external resistor. The display is disabled when an internal threshold is reached. The opposite applies when the capacitor is discharged by connecting this pin to Vss (GND) with an external clamp. f a capacitor> 0 ij.f is used a Kn resistor must be placed in series with pin 4. Pin 5 - /2 frequency clock output The clock frequency divided by two is present on this pin for measurement purposes. To allow this, connect temporarily pin to Vss and pin 2 to V DD. The output is open drain and an external pull-up resistor is needed. f the output is not used it must be connected to V ss. 89

85 M 9 DESCRPTON (continued) Pin 6 - Clock.oscillator input This pin is connected to a RC network as shown in fig.. The clock frequency determines the horizontal width on the screen of the tuning scale, of the rectangles and the distance of the display from the left edge of the screen. Fine adjustment of the clock frequency is obtained by the trimming resistor. Typical clock frequency is.8 MHz. Pin 7 - Voo Pin 8 - Band display enable When this pin is connected to V ss (GND) a band display with the following format is enabled, on command, together with the tuning voltage display. Fig.6 BAND VHF BAND AV - - BAND VHF BAND UHF f this pin is connected to Voo only the tuning voltage will be displayed. Pin 9 - Latching time constant An RC time constant must be applied to this pin to generate the internal latching signal. The content of the internal shift register is transferred to the internal decoding circuit only at the end of the clock burst to avoid noise on the display during data transfer. This is made by integrating the incoming clock bur~t with the RC time constant connected to pin 9 as shown in fig. 7. Fig.7 PN 0 """:J 5TROBE 90

86 M 9 OESCRPTON (continued) ;Pin 0 - Clock input :This pin accepts the burst containing the 5 clock pulses available from the M93. The burst is used to load the serial Data on pin into the internal 5 bit shift register (see fig. 8). Fig. 8 t6:j.69ms REPETTON TME --- -lj.~ j BANO S 3222/2 Pin - Data input This pin accepts the 5 bit serial Data information available from the M 93 EPM. The burst contains 2 bits for band information, 4 bits for program, 8 bits for tllling voltage and bit which indicates if the system is in the Search mode. Pin 2 - nverted video signal output The signals of pin 3 are inverted and presented on this pin to allow easy interfacing in some chroma kits. The output is open drain. Pin 3 - Video signal output The tuning scale and band information video signal is available on this pin, a load resistor is connected between the open drain output transistor and VDD.White level corr"!sponds to di~jble of the internal transistor. Pin 4 - Vertical synchronization The frame flyback pulse must be applied to this pin by means of an interface. The signal must be positive. The circuit is triggered by the negative edge of the pulse. Fig.9 >3.5V <O.BV n TRGGER EDGE s

87 M 9 DESCRPTON (continued) Pin 5 - Vertical position input An internal monostable is triggered by the frame pulse applied on pin 4. The display is allowed at the end of the cycle of the monostable. The RC network applied to this pin gives the time constant of the monostable determin ing the position of the display on the screen. Pin 6 - Vss (GND) All voltages quoted are referred to Pin 6. 92

88 COS/MOS NTEGRATED CRCUT M92 4-BT BNARY 7-SEGMENT DECODER DRVER PRELMNARY DATA 4-BT BNARY CODE NPUT GENERATES TO 6 NUMBERS ON OUTPUT DRECT DRVNG OF AND /2 DGT 7-SEGMENT (COMMON CATHODE) LED DSPLAY WDE SUPPLY VOLTAGE RANGE TTL COMPATBLE NPUTS SMALL QUESCENT SUPPLY CURRENT SPECFCALLY DESGNED FOR TV OR RADO APPLCATONS The M 92 is a monolithic integrated circuit which direct drives a and /2 digit 7-segment LED (common cathode) display to present the numbers to 6. The inputs accept a 4-bit binary code having TTL levels. This device is especially designed to show the program number in TV or radio sets in conjunction with M 90 keyboard encoder, M 30 ultrasonic remote control receiver, M 93 electronic program memory or H 770//2/3 analog switches. All outputs are designed to supply and sink current, except the additional "r" output (pin ) which is designed for a brightness control in a current generator configurations. The circuit is produced in COS/MOS technology and is supplied in a 6-pin dual in-line plastic package. ABSOLUTE MAXMUM RATNGS* Voo** V Vo OH OL P tot T 5g Top Supply voltage nput voltage Output voltage (pin ) Output source current Output sink current (except pin ) Total package power dissipation Storage temperature Operating temperature -0.5 to 6.5 V -0.5 to Voo +0.5 V Voo +0.5 V -25 ma 0 ma 400 mw -65 to 50 C o to 70 C Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condition above those indicate in the "Recommended operating conditions" section of this specification is not implied. Exposure to absolute maxi mum rating conditions for extended periods may affect device reliability. All voltages are with respect to Vss (GNO. ORDERNG NUMBER: M 92 B MECHANCAL DATA Dimensions in mm Supersedes issue dated 0/78 93 /79

89 M92 PN CONNECTONS OUTPUT r 6 Veo 0 5 i NPUTS C 4 n A,lib 9 e B 4 3 ~ 9 nl - A 5 2 ~, OUTPUTS VSS (GND) ~ e OUTPUT. 0 d OUTPUT b 9 e i - -d S TRUTH TABLE NPUTS Number OUTPUTS A B C 0 displayed a b c d e f 9 h i r L L L L L H H L L L L L L H H L L L 2 H H L H H L H L L H L H L L 3 H H H H L L H L L H H H L L 4 L H H L L H H L L H L L H L 5 H L H H L H H L L H H L H L 6 H L H H H H H L L H L H H L 7 H H H L L L L L L H H H H L 8 H H H H H H H L L H L L L H 9 H H H H L H H L L H H L L H 0 H H H H H H L H H H L H L H L H H L L L L H H H H H L H 2 H H L H H L H H H H L L H H 3 H H H H L L H H H H H L H H 4 L H H L L H H H H H L H H H 5 H L H H L H H H H H H H H H 6 H L H H H H H H H H 94 i

90 M92 NPUT CONFGURATON OUTPUT CONFGURATON VDD Vss S-282. Note: pin has not the pull down N-channel transistor. RECOMMENDED OPERATNG CONDTONS Voo V Vo OH OL Top Supply voltage nput voltage Output voltage (pin ) Output source current Output sink current Operating temperature 0.8 to 5 o to Voo Voo max -0 max 0.5 o to 70 V V V ma ma c ELECTRCAL CHARACTERSTCS (over recommended operating conditions) typical values are at T amb= 25 C unless otherwise specified Parameter Test conditions Values Min. Typ. Mal(. VH High level input voltage 3.5 Voo V L Low level input voltage H High level input current Voo= 5V V H= 5V 0 Unit V V la T+ nput current at positive VOO= 5V threshold ~ 200 la VOH High level output voltage OH= -0 ma Voo= 0.8V Vo o-3 Voo= 3V Vo o-2 Voo-3 Voo= 3V, T amb= 70 e 0 Voo-2.5 Voo= 5V Vo o-.5 VOL Low level output voltage Voo= 3V OL= 0.5 ma.5 (except pin ) 00 Supply current Veo= 5V 2 2,4 nput to Vee Outputs open 95 V V V V V ma

91 M92.. APPLCATON NFORMATON Fig. - Light emitting diode readout a - Current generator configuration b - Standard configuration Vss M 92 L~_.. s 2826 r _. --~- i.3v U VOO vs~ A B C: 0 t ~~ b 'Q b. '*, i ~' 80 4W M 92,, g~ h, " ~ _ ; Fig. 2 - Liquid crystal readout Fig. 3 - Fluorescent readout JliL 50", -.~. M92 M 92 ~! ---.L.. FLAMENT.l SUPPLY Fig. 4 - ncandescent redout Fig. 5 - Gas discarge readout M 92.V M 92 96

92 M92 TYPCAL APPLCATONS (continued) Program display with stand-by indication This application is useful in a remote controlled set. The stand-by condition of the set, i.e. when only the remote control is supplied, is shown by two dots.. The program display number is controlled by the same output of the remote control receiver as that which drives the mains relay. Fig.6.)V.8\... M 92 Fig. 7 - M 92 interfacing a b i"'ov f" 0492 MllJO REM. CONT. RECEVER PA PO M92 r' 7 SEGM[Nl ~ ClE.C OQV.!-e"-- T r~ : u2kl'l.i PA OR p p T F"NE TU"NG M 93 (E PM'.lev.)V Q ",.n.. r..0 s nn. L 97

93 DS NTEGRATED CRCUTS t M 93 M 93A ELECTRONC PROGRAM MEMORY ONE CHP SOLUTON NCLUDNG CONTROL AND NON VOLATLE MEMORY FOR 6 PROGRAMS 0YEARS MEMORY RETENTON UNLMTED NUMBERS OF READ CYCLES AUTOMATC AND MANUAL STATON SEARCH EXTERNALLY ADJUSTABLE SEARCH SPEED FNE TUNNG N 8 STEPS, STORABLE FOR EACH PROGRAM SEPARATELY MUTE OUTPUT it 4.43 MHz QUARTZ or LC REFERENCE FREQUENCY The M 93 is a monol ith ic integrated circuit constructed in N-channel sil icon gate technology, designed to control digitally via a D/A converter, with a resolution of 892 steps, a TV or Radio varicap tuner. t also contains a 7 bit x 6 words NVRAM, whose control timing is internally generated, and after having been externally buffered, is returned to the integrated circuit to drive the memory. Each memory word contains information for program, i.e. band (2 bit), tuning voltage (2 bit) and fine tuning offset (3 bit). The circuit is able to operate either in automatic or manual search. The,earch speed is externally con trolled by a simple RC network. n the automatic mode the M93 works in conjunction with the TDA 443, which provides TV station recognition and converts the AFC-S-curve into a digital com mand. This command controls the 3 bit up/down counter in the M93, whose position determines the tuning voltage. A mute output is provided to avoid noise on the audio during automatic search, program change or when the supply voltage is switched on/off. The circuit accepts standard program selection on 4 bus lines. 7-segment program display is possible by using the M92 circuit connected at the same lines. A serial information output is provided to display on the screen, via the M9 integrated circuit, the varicap voltage in the form of a linear tuning bar and the band. The M93 is available in a 28 lead dual in-line plastic package. Two different types are available which differ as specified below. "'93 - Standard type. M93A - As M 93 but the fine tuning is also reset during a manual search. :ORDERNG NUMBERS: M93 B M93A B Lpersedes issue dated 6/79 99 /79

94 93 M 93A. ABSOLUTE MAXMUM RATlNGS* VOO. V002 ** Supply voltages Vpp Memory supply voltage (pin 9) V, nput voltage Vo (off) Off-state output voltage (except pin 4) (pin 4) OL Output current (except pins 5-9) (pins 5-9) OH Output current (pin 27) Ptot Total package power dissipation Tstg Storage temperature Top Operating temperature -0.3 to 20 V -0.3 to 3 V -0.3 to 20 V 20 V 3 V 5 ma 5 ma -5 ma W -25 to 25 C o to 70 C Stresses above those listed under" Absolute Maximum Hatings"may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condition above those indicated in the "Recommended operating conditions" section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All voltages are with respect to Vss (GND) MECHANCAL DATA (dimensions in mm) 52..J PN CONNECTONS \'55 (GND) 8Ar.L StEP 8'' STEP STORE ON PANEL!ONE TUN't.G,:jC FNE TuNNG AUTO SEMCH. p,u,n.up..qown ' NutE., UHF VHF m VHF STOPAFC TEST PN 'pp MEM~'f SUPPLY) ~DD SEARCH SPEEC- ~o. AuTOJrr4A,NUAL '9 FNE TUNNG "6 TEST PN " DATA SURST CLOCK 8lRST TUNNG RECOMMENDED OPERATNG CONDTONS VOO Supply voltage VOO2 Supply voltage Vpp Memory supply voltage (pin 9) V, nput voltage Vo (off) Off-state output voltage (except pin 4) Off-state output voltage (pin 4) OL Output current (except 5-9) (pins 5-9) OH Output current (pin 27) tpd Delay between memory timing and memory supply pulses f Clock frequency twl Fine tuning + pulse width (pin 4) tw2 Fine tuning - pulse width (pin 4) Top Operating temperature Rl2 Search speed resistance (pin 2) Cl2 Search speed capacitor (pin 2) 7 to 9 V 0.8 to 3.5 V 28 to 30 V o to 9 V max. 9 V max. 30 V max. 2.5 ma max. 0 ma max ma max. 5 p.s 4.43 MHz >.8 ms <.7 ms o to 70 C 8 to 330 Kn' max. 00 nf 00

95 M 93 M 93A BLOCK DAGRAM c. -- l. "'" T, l' '8.J:l" OS u LJ-~ ~ ~ r - ' DE'"~ ill..... nt -GJ-- EPM SYSTEM CONFGURATON f'a 5 p.~ ~9 8 'DOl F".~ 0-.~ 0--l F"' (Fl~E: TUN~ _--.s.~oc~. \ voj ~ -- ~-~:c't:'j:. ' > 0- T STORE ~ ~~--~ Aulowarctl slarllm."'ualsaow up VD02~J:.~---- Auto s.. rch start /manu.j slow down s.~~~.:t.o- " Vso hi 93 ELECTRONtC PROGRAo WEMORV ~ ' search VooJ ~voo. ~EO ~- t_f;,ma~auto ~~.l.> -L FAST MANUAL = = MUTE OUTPUT. SJPPLY " OATA' 2J V-F 2, YHF 25~F 26 AV 5.. '.." fo--- (LOC< l AERAL 00. L~~~.t----;:,_",,,;;;,,-Y ATCAL FlYBACK TO CAt NTERFAC.E 0

96 M 93 M 93A STATC ELECTRCAL CHARACTERSTCS (over recommended operating conditions) Typical values are at T amb = 25 C, V D Dl = 8V, V DD2= 2V unless otherwise specified Parameter Pins Test conditions Values Min. Typ. Max. Unit V,L Low level input voltage V,H High level input voltage V DD V DD2- V,M Middle level input V DD2= 0.8V 4,5 7.5 voltage 22 V DD2= 3.5V 5 9 VOL Low level output V DD2= 0.8V 0L= ma 3 voltage 5-9 V DDr 0.8V 0L= 0 ma 6-7 V 002 c 0.8V 0L= ma V 00=7V V DD2= 0.8V 0L= 2.5 ma V OH High level output 27 V DD2= O.8V 0H= - ma 2.4 voltage 0 (0) Output leakage 27 V D02= 3.5V VO(O)= VSS -50 current V DD2= 3.5V VO(O)= 9V Voor 3.5V VO(olf)= 3.5V V[)Ol= 9V V D02= 3.5V V 0(0)= 30V, nput current V, = 0 to 9V Supply current 0 V 00= 9V Supply current 3 V OD2= 3.5V pp Memory supply writing 65 current 9 V, = 30V erasure R, nput resistance See Fig. la V V V V V pa JA ma ma ma Mn 02

97 M 93 M 93 PVNAMC ELECTRCAL CHARACTERSTCS (fclock = 4.43 MHz) Parameter Test conditions Values Min. Typ. Max. Unit fo Fine tuning output repetition rate 0 Fine tuning output duty cycle tw3 Width of erase pulses Pin 4 Pin 9 (see also fig. 9) T3 Period of erase pulses See also fig. 3 and 6 t3 Total time for one erase cycle (about 500 pulses) tw4 Width of write pulses Pin 4 T4 Period of,write pulses See also fig. 2 and 5 t4 Total time for one write cycle about 950 pulses) tws Width of clock pulses Pin 6 TS Period of data and clock pulses Pin 7 See also fig. 8 ts t6 Total time for one display burst (5 pulses) Burst repetition time.t7 Acceptance time of the Pins commands ts Acceptance time of the Pin 20 commands 7305 Hz /8 8/8 5 ls 23 ls 5 ms 5 ls 462 ls 440 ms.3 ls 3.6 ls 54 ls 3.69 ms 3 ms 3.6 ls nput and output configurations All outputs (except the Mute one) have open drain configuration. The Mute output has a source follower. nputs have the following configurations: Fig. a) Pins 2, 3, 28 b) Search speed (pin 2) c) Clock input (pin ) d) Other inputs (pin ) 03

98 M 93 M 93A DESCRPTON The circuit description will be made following both pin sequence and pin function. Pin - Vss (GND) The substrate of the integrated circuit is connected to this pin. t is the reference point for all voltage parameters of the device and must be connected to the lowest potential of the supply voltage, normally ground. Pin 2 - Store/sequential band change input f this input pin is briefly connected to V ss the 2 bits of the digitized tuning voltage, the 2 bits for band selection and the 3 bits of fine tuning information are stored. The command is disabled during search and the execution of the store cycle. The store cycle consists of two operations: at first the old word is cancelled and afterwards the new content is written. f this input pin is briefly connected to V DD, the selected band output changes in the sequence written below, to obtain a step-by-step band selection. VH F UHF VHF AV VHF and so on Pin 3 - Fine tuning +/- (on panel) This input accepts the Fine tuning +/- commands given from the panel. The commands are accepted according to the following rules: nput levels M (input floating) H L Command No command FT + FT- Each command corresponds to one step change; to have more changes the key must be released and the command repeated. Pin 4 - T input (fine tuning +/- from remote control) The Fine tuning +/- commands given from Remote control are applied to this input in the form of a series of positive pulses. Short pulses t(.8 ms) correspond to the FT -command while long pu ses (>.8 ms) correspond to the FT + command. ' This input is compatible with the T output of M 30 Remote control receiver. When the Fine tuning command is gi\en, the duty cycle of the output of pin 9 (Fine tuning output) is changed at the rate of one step every 0.56 sec. f the pulses are present for less than 0.56 sec. step-by-step operation can be obtained. f this input is not used it must be connected to Vss (GND). 04

99 M 93 M 93A t f: tins Program inputs ft,is 4-line bus selects the program according to the truth table given below:, (J Program PA PB PC PO, L L L L 2 H L L L ~.. 3 L H L L 4 H H L L 5 L L H L 6 H L H L 7 L H H L 8 H H H L 9 L L L H 0 H L L H L H L H 2 H H L H 3 L L H H 4 H L H H 5 L H H H 6 H H H H Pin 9 - Vpp - Memory supply A series of pulses is applied to this pin during the store cycle. The timing of these pulses is given by the output of pin 4 and it is different during erase and write cycle as shown in fig. 2 and 3. During a store cycle the old word is at first ca!celled and the new one is written afterwards. Pin 0 - V00 Fig.2 - Memory Erase supply Fig. 3 - Memory Write supply rljljl ~...- 'J " This pin has to be connected to a power supply with the characteristics shown in the recommended operating conditions. Pin - Clock input When the device is used alone the internal oscillator operates with a 4.43 MHz crystal or parallel LC network connected between pin and ground. t can also operate with a single crystal together with Ml30 as shown in fig. 4. Fig.4 ""'30!?.. 05

100 M 93 M 93A Pin 2 - Search speed An external RC network is connected to this pin in order to set the frequerrcy of the internal oscillator which, in turn, sets the scan speed during Search mode. The scan speed can be adjusted over a wide range. The relationship of search speeds between UHF, VHF and AV is a follows: Automatic: FAST UP VHF = the frequency externally fixed FAST UP UHF = AV = /2 FAST UP VHF MEDUM DOWN VHF = /4 FAST UP VHF MEDUM DOWN UHF = AV = /4 FAST UP UHF (/8 FAST UP VHF) SLOW UP VHF = UHF = AV = 67.7 Hz SLOW DOWN VHF = UHF = AV = 8.4 Hz Manual: UP or DOWN UHF = AV = /2 UP or DOWN VHF The manual Fast up or down speed is obtained by changing the frequency of the oscillator. The maximum capacitance which should be connected to this pin is 00 nf. Pin 3 - V002 This pin has to be connected to a power supply with the characteristics indicated in the recommended operating conditions. Pin 4 - Memory write timing output This output gives the timing for the pulses to be applied on pin 9 during the store cycle. The output consists of an open drain transistor. The waveforms are shown in fig. 5 and 6, and are different during erase and write cycle, as already described for pin 9. Fig.5 - Memory Erase Current Fig. 6 - Memory Write Current --lj _~ ----'4 d 06

101 M 93 M 93A On 5 - Digitized tuning voltage output, e output consists of a variable frequency/variable width pulse train which, after filtering, provides the ning voltage to the varicaps, is'signal carries 3 bits of information (only 2 bits however are stored in the memory). 'he output circuit consists of an open drain transistor which offers a low impedance to ground when in ON state. e output waveforms are shown in fig. 7. Fig. 7 r! )--_--.~VARCAP vc VA V. vc DOWN-UP~ Pin 6 - Clock output for external display A burst containing 5 clock pulses is available on this pin. These clock pulses are synchronized with bata nformation as described in fig. 8. Pin 7 - Data information output for external display A 5 bit burst is available on this pin. 'n contains the 8 most significant bits of the digitized tuning voltage. ~bits for band information, 4 bits for program information and bit which indicates whether the system is in the Search mode (both in ilutomatic and manual). The Data nformation is complementary form (see fig. 8). These two outputs (pins 6 and 7) work in connection with the M9 (On screen tuning bar display). When the burst is not transmitted, the output transistor is in the off position. Fig. 8 '6=).69ms - REPETTON TlM( DATA NF~MATON ~--'-----.Jf----'-----'-----' '-----'----'-----'-----'-----'----' ' 07

102 M 93 M 93A Pins Test pins These pins must be connected to Vss (GND). Pin 9 - Fine tuning output Fine tuning information is available on this pin in the form of a square wave having a frequency of 7305 Hz and duty cycle variable in 8 positions as indicated in fig. 9. The voltage generated after filtering is fed to the AFC loop and detunes the receiver by a smalll..f while maintaining the action of the AFC: The Fine tuning function operates as follows: during the search the output is set at mid-range (see fig. 9). (n the M93 only in automatic mode). when the search has been completed it is possible to operate on the Fine tuning +/- commands (pin 3 for Remote control operation or pin 4 for panel operation). The Store command memorizes this information together with the 2 bit tuning voltage and 2 bit band information when a memorized program is recalled it is still possible to act on the Fine tuning commands. Any change in Fine tuning is only memorized by the Store command. Fig.9 FNE TUNNG OUTPUT.... r ~.J '---~r...jr----.ls.j LJ.J LJ *,- MD F,. RANGE!.-22 Pin 20 - Automatic/manual selection This pin is used to change the Search mode. When it is connected to Voo the system operates in Automatic mode; when it is at Vss (GND) the system works manually. The change Auto-manual or viceversa can be made at every time without precluding the right operation of the system. Pin 22 - Stop/ate input This pin is used only in automatic search mode. When the EPM is manual operation this pin is internally disabled. The Stop/afc is also internally disabled during any program change for the time the Mute signal lasts. This input can have three different levels: high (H), middle (M), low (L). The middle level, unlike the other three level inputs of the circuit, is not internally generated and has to be externally determined according to the recommended operating conditions. f this input is not used it has to be connected to Vss (GND) or to V

103 M 93 M 93A ( ~.h hee input has two different functions depending on whether the system is in the search or in normal pperation (AFC control). ~ Search mode: after depressing the Search start key, the transitions and levels of the signals coming J~~: :::p~i~e~ a ~~l;t:~~~e~a:~::~s r~~:~~~~~.o the search function and determine when the search The circuit operates with the following sequence (see fig. 0 for reference and explanation of pin 2 t for speed definition): (, - after pressing the search start key the search occurs in the Fast up mode t 2 -,. L 3 - subsequent transitions on pin 22 Stop/afc input are ignored during the first 5 search steps. After that the first M-H transition on the input preceded by at least one M-L transition will set the search into the Medium down (fast up/4) mode. The acceptance delay of 5 search steps has been introduced to avoid the condition where the system could stop on the previous station (for example in the case the search start command has been given just before an AFC control command). the next M-L transition will switch the search to Slow up speed (67.7 Hz). At this point the system is in normal AFC operation. Fig Automatic station capture diagram J," MHz FAST UP VHF bands: the fate e5te,naliv fijled UHF/AV bands./2 the VHF band rate NORMAL AFe POSTON MEDUM DOWN,4 F-AST UPSEARCHSPEED 33.4MH;r SEARCH DRECTON, TRAS... 'TTER 'DENTFCATON SEARCH SlART i- ~ >38.8MHz SLOW UP 5J=67Hz ~ i HO..R~ AF( OPERATON STOP Me threshold 38.BMHz /, / -J. _ - + ~, 09

104 M 93 M 93A B) AFC operation: when a station is perfectly tuned, the input signal coming from TDA 443 is at middle level. f the tuning moves lower than the threshold (below 38.9 MHz), the pin 22 goes low and the 3 bit internal counter is moved with Slow up speed to determine an increasing of the varicap voltage. When a detuning occurs in the opposite direction the input will go high and the tuning voltage is de creased with Slow down speed (8.4 Hz). The increase or decrease of the tuning voltage is stopped as soon as the input returns to M level. Therefore during normal operation pin 22 acts as AFC control command. C) Recall from memory: when the circuit is in automatic operation mode and a pre-memorized program is recalled from Memory, a fixed value of 8 steps (::= 3.2 mv) is subtracted from the tuning voltage. This corresponds to a detuning of about 0.6 MHz (UHF) and of 0.3 MHz in VHF into that part of the F response curve which corresponds to the fully transmitted sideband. At this point the AFC operation takes over as described in point B) above and the exact tuning is reached in about 0.2 sec. Due to this feature the AFC capture ratio will be increased and the requirements for stability of the tuner, of the reference voltage sources and of stability of the Df A converter are less severe. n manual operation mode the memory content is instead read without any change. Pins Band drive outputs The information for band selection is present on these outputs, consisting of open drain transistors, one of which, in connection with the selected band, is conducting (see fig. ). The relations between pins and bands are as follows: Pin 23 = VHF Pin 24 = VHF Pin 25 = UHF Pin 26 = AV Fig. Pin 27 - Mute output A source follower transistor is provided to give a high level output during mute function. The mute is present in the following cases: during automatic search. The mute is present 0 msec before the start of the search. during any program change for 320 msec. The mute is active 0 msec before the program change takes place. when the supply voltage V 002 is applied, for about 320 msec. when the supply voltage V 002 is removed. 0

105 M 93 M 93A ~n 28 - A) Automatic operation: search start : B) Manual operation: up/down search ~is input is a three level one, i.e. it is normally in the middle level and the above mentioned functions jll'e activated when it is connected to V DD2 or to GN D. the input is kept at a voltage corresponding to about the half of the supply voltage by an internal divider tnade with two resistors of about Mohm., ~) Automatic operation ~: When the pin 28 is briefly connected to GND the search starts on the bands VHF -UHF which are scanned in sequence. f it is connected to V DD2 the search is made on band VHF and AV.,. f the key is kept pushed, another search can start only by releasing the key and connecting it again.to GND or V DD2. f a Search start command is given while the system is already in search operation, the search is immediately stopped and after restarted on the new group of selected bands; the band where the system will search is that which has the same search speed of the previous one. During the search the tuning voltage is always changing from lower to higher voltage levels. The search is automatically stopped when the first station is found. The search is also stopped whenever a program change command is given. When the upper limit of the tuning voltage is reached, the search restarts from the lower limit of another band after 20 msec of temporary stop. The search speed is determined by the RC network connected to pin 2. Manual operation When the input is connected to V DD2 the content of the internal counter is changed in such a way to, have an increasing of the varicap voltage. f the input is connected to GN D the varicap voltage is decreased. The search speed is determined by the RC network applied on pin 2. ~ast/low search speed is possible by changing the value of the same RC network (see fig. 2). ih manual operation the search is always made in the same band. ~ inhibit of the search is provided when the lower or the upper limits of the varicap voltage are reached. Step-by-step band selection is possible by temporarily connecting pin 2 to V DD2. Fig. 2 V002 -C MANUAL, FAST F")? L-- 2 S-3225

106 M 93 M 93A GENERAL NFORMATON Command acceptance rules ) When a manual command at pin 2, 3, 28 is given, an internal counter is immediately started. The command is accepted only after about 3 msec. of its continuous presence. f the command disappears before (for example in consequence of contact bouncing), the counter is immediately reset. When a command has been accepted, no other manual command is accepted until the previous command has been released. 2) Program change commands are immediately accepted and if the circuit is in the automatic search position, the search is stopped. Manual commands given during the execution of the program change are r:lot accepted except the automatic search start command. This one is internally stored and executed at the end of the program change. 3) During the store cycle only the program change and the search start commands are accepted and executed at the end of the cycle. The other commands are ignored. 2

107 ~s NTEGRATED CRCUT '25. ~PEGGO, CHORD AND BASS ACCOMPANMENT GENERATOR,.. ~ CHOCE OF OPERATNG MODE: ~ AUTOMATC WTH MEMORZATON OF THE SELECTED KEY - SEMAUTOMATC WTH MEMORZATON OF THE SELECTED KEYS - SEMAUTOMATC WTHOUT MEMORZATON OF THE SELECTED KEYS SMPLE KEY SWTCH REQUREMENTS (24 NOTE KEYBOARD WTH ONE SWTCH PER KEY) NTERNAL ANT-BOUNCE CRCUTS THREE OUTPUTS FOR THE ARPEGGOS f ANALOG OUTPUT FOR CHORDS BASS OUTPUT (AUTOMATC OR ALTERNATE) ~. TRGGER OUTPUTS FOR PERCUSSON EFFECT ON BOTH ARPEGGO AND BASS SECTONS - MULTPLE CHOCE POSSBLTY ON THE CHORDS N AUTOMATC MODE: MAJOR OR MNOR THRD - FFTH OR DMNSHED FFTH - SXTH OR SEVENTH f LOW DSSPATON: <400 mv TYP. STANDARD SUPPLES (+ 5V AND - 2V) ~. NPUTS PROTECTED FROM ELECTROSTATC DSCHARGE he M 25 is realized on a single monolithic silicon chip using low threshold P-channel silicon gate MOS tchnology. t is available in a 40-ead ceramic or plastic package. ~OLUTE MAXMUM RATNGS Source supply voltage n put vo tage Ol,ltput current (at any pin) Storage temperature Operating temperature -20 to 0.3 V -20 to 0.3 V 3 rna -65 to 50 c o to 70 c This voltage is with respect to Vss pin voltage RDERNG NUMBERS: M 25 B AC for dual in-line plastic package i M 25 D AC for dual in-line ceramic package 3 3/78

108 . 25 MECHANCAL DATA (dimensions in mm) M25 B AC R 5.24 i M 25 0 AC E:} 4.es ma~ C--- -_ :-=J, ~ ~ [::::::::::::::::::: i 0 0 ~i -~~ CONNECTON DAGRAM BLOCK DAGRAM vss OUT CHORD VGG OUT ARPEGGO 2 * 4/5 5th/5 th - EXT./ NT. OUT ARPEGGO 3 6/LATCH OUT ARPEGGO 78 TOB OUT BASS TOA T T3 F24 F3 T 2T24 T2T4 F23 F4 TlT23 T3/T5 F22 F5 T0/T22 T4T6 F2 F6 T9/T 2 T5T7 F20 F7 T BT20 T6/TB F9 F8 T7T9 FJ F24 ]< ' 3'''. 6t~ f 7~ NPUT." CRCU T SELECTON 'ND L,2 nd l, DVDERS 3'''L,4"'l AND TOP 5 h /5h COMMAND EXT.flHT. RECOGNTON htultplexe FOR AUTOMATC LOGC AND NOTE GENERATOR FOR ARPEGGO CHORD AND BASS 'D' OUT AAfJEGG!O.:t' ARPEGGO' OUT AAPEGGKJ OUT otce OUT lass 'DO *AUTOMATC MODE/MANUAL, AUTOMATC BASS/ALTERNATNG RESET AUT. MAN. AUT.ALTER.RESET 06 LATCH

109 M 25 'GENERAL CHARACTERSTCS,l"he circuit comprises: ia) 2 pins for input frequencies lb) 2 inputs from the keyboard with the possibility to provide the control of two octaves (in semiauto, matic modes only) by multiplexing the two octaves. n automatic mode the second octave repeats the first kl 4 multiplexed data inputs for addressing the internal selection circuits. These inputs are normally com ~. ing from the outputs of an external memory fdl 5 signal outputs: arpeggio, arpeggio 2, arpeggio 3, bass and chord respectively ~) 2 trigger outputs: arpeggio (TDA), and bass (TDB), respectively. These outputs, in conjunction with an external time-constant, allow the formation of the envelope of the arpeggio and bass notes. The duration of the trigger pulses is equivalent to one period of the external memory clock line tfl 3 inputs for mode selection ~) 2 supply pins.!m 25 is normally used in conjunction with an external self-scanning ROM (such as the M or 4) which performs the selection of the various notes in the arpeggio/chord/bass accompaniment. 'AUTOMATC OPERATON When a number of keys in the two available octaves are played, the lowest key is taken as a reference by the circuit and this note is memorized internally. When the lowest key played changes, the memory is :erased and the new information from the keyboard is now fed into the circuit and memorized. When all 'Jhe keys are released the last "update" is held in the memory and is only changed when a different lowest 'by is played. f keys in the upper octave only are played then the two octaves act in parallel. The memofized key by means of the internal multiplexer selects the corresponding tonic and all the other notes programmed for arpeggio, chord and bass accompaniment in the correct relationship of intervals. nternal dividers provide all the octaves we need as shown in the tables below. By means of the external j:ommands it is possible to choose between major third and minor third, between fifth and diminished fifth and between sixth and seventh. To reset the key memorized at the end of a piece played the automa ~ic signal must be interrupted for a moment while none of the keys on the two available octaves is played. "RPEGGO TRUTH TABLE (positive logic) EXTERNAL SELECT 6th SELECT 7th MEMORY CODE ARP. ARP. ARP. ARP. ARP. ARP. TONC 3rd 5th TONC 3rd 5th 0 3 rd 5th TONC x 2 3rd 5th 7th 0 5th TONC x 2 3 rd x 2 5th 7th 3rd x th - - 7th TONC x 2 3 rd x 2 5th X 2 7th 3rd x 2 5th X rd x 2 5th x 2 TONC x 4 3 rd x 2 5th x 2 TONC x th x 2 TONC x 4 3rd x 4 5th x 2 TONC x 4 3rd x th x th x TONC x4 3rd x 4 5th x 4 TONC x 4 3rd x 4 5th x rd x 4 5th x 4 TONC x 8 3 rd x 4 5th x 4 7th x 4 '0 0 5th x 4 TONC x 8 3 rd x 8 5th X 4 7th x 4 3rd x th X th X TONC x 8 3 rd x 8 5th X 8 7th x 4 3 rd x 8 5th X rd x 8 5th X 8 TONC x 8 3rd x 8 5th X 8 7th X th x 8 TONC x 8 3 rd x 8 5th X 8 6th X 8 3 rd x No Change No Change No Change No Change No Change No Change VERY MPORTANT NOTE: TON C is the input note, corresponding to the selected key, divided by 6. :srd is the correct third corresponding to this TONC. And so on. 5

110 M25 BASS and CHORD TRUTH TABLES (positive logic) EXTERNAL MEMORY CODE AUTOMATC BASS 2nd/2 0 8ve /2 0 9th/ th or 7th/2 0 Sth/ rd/2 0 0 TONC/ NO CHANGE "NO CHANGE" is interpreted as an in struction to sustain the previous notes until new information is presented. EXTERN. MEMORY CODE 0 0 EXTERNAL MEMORY CODE ALTERNATE BASS - 0 TONC/2 0 Sth/2 0 0 NO CHANGE SELECT 6th CHORD SELECT 7th TON C +3rd +Sth TONC +3rd +Sth +7th NO CHANGE NO CHANGE SEMAUTOMATC OPERATON WTH MEMORZATON OF THE KEYS When any number of keys are played within the two available octaves they are memorized and sent to an internal recognition circuit which selects the lowest four keys, the top key played and their respective frequencies. This information is updated every time a different group of keys is played. Between the playing of two groups of keys there must be a pause during which none of the keys is down, otherwise the new group of keys is memorized without the previous group being cancelled. Again the keys recognized can be extended to more octaves by means of the internal divider. The following are positive logic truth tables showing the actual keys, instead of the notes.top is the first key from the right(the top key playedt. L the lowest key played, and 2L" the second lowest and so on. The relationship between keys and input frequencies is as follows: L in the first octave to the left represents corresponding input note divided by 6, while in the second octave it is divided by 8. And so on. To erase the memorization at the end of a piece played it is necessary to select "automatic" for a moment and then return to semiautomatic while none of the keys is played. The trigger signals, TDA and TDB, are sent out only if 3 or more keys are played. ARPEGG 0 TRUTH TABLE (positive logic) EXTERNAL MEMORY CODE MEANNG OF THE CODES OS ARP. ARP. ARP. L 2nd L 3rd L 0 2nd L 3 rd L Lx2 0 3 rd L Lx2 2nd Lx th L Lx2 2nd Lx 2 3rd Lx nd Lx 2 3 rd Lx 2 Lx rd Lx 2 Lx4 2nd Lx th Lx Lx4 2nd Lx 4 3rd Lx nd Lx 4 3 rd Lx 4 Lx rd Lx 4 Lx8 2nd Lx th Lx Lx8 2nd Lx 8 3rd Lx nd Lx 8 3 rd Lx 8 Lx rd Lx 8 Lx8 2nd Lx NO CHANGE NO CHANGE NO CHANGE, 6

111 25 BASS and CHORD TRUTH TABLES (positive logic) EXTERNAL MEMORY AUTOMATC BASS ALTERNATE BASS CODE OUTPUT OUTPUT oa EXTERN. MEMORY CODE 0 CHORD OUTPUT TWO ave BE LOW TOP - 0 L - 0 ONE ave BELOW TOP ONE ave BELOW 4th L - 0 ONE ave BELOW 3rd L ONE ave BELOW 2nd L ONE ave BELOW L 0 0 ONE ave BELOW L ONE ave BELOW TOP NO CHANGE NO CHANGE L +2nd L +3rd L +4th L 0 NO CHANGE "NO CHANGE" is interpreted as an instruction to sustain the previous notes until a new information is presented. SEMAUTOMATC OPERATON WTHOUT MEMORZATON OF THE KEYS This method of operation is the same as the previous one except that the keys are not memorized. CHARACTERSTCS COMMON TO ALL 3 MODES OF OPERATON The signals from the keyboards, those from the external memory and those for selecting the mode of operation have to be multiplexed into the M 25 since the number of pins available is not enough. The method used to differentiate between the two distinct commands applied to the multiplexed input pins is as follows: two anti-phase pulse trains are generated internally from the highest note in the upper octave (pin 32). These two pulse trains are used to separate the input information during the "" and "0" status ""of F24. With AUTOMATC mode and EXTERNAL command selected the four frequencies of the highest octave can be made available at pins 2,3,4 and 5 as the a x tonic, a x major 3rd or a x minor 3rd, a x 5th or a x diminished 5th and 8 x 6th or a x 7th. Likewise in semiautomatic mode, the L x 8,2nd x 8, 3rd x 8, 4th x 8 notes selected appear at the respective pins. These signals give the designer considerable flexibility in the formation of accompaniments not directly produced by the M 25 itself. EXTERNAL MODE OUTPUTS PN N AUTOMATC MODE SEM AUTOM. xl a x Jrd L Tl is the key farthest to the left of the keyboard. For "L" see SEMAUTOMATC OPERATON WTH MEMORZATON OF THE KEYS. n the external mode the four frequencies of the highest octave appear at pi ns 2. J. 4 and 5 as shown in the table. 2 J 4 5 ax TONC a x FFTH DMNSHED FFTH a x MAJOR THRD OR MNOR THRD a x SXTH OR SEVENTH a x 2nd L a x 4th L STATC ELECTRCAL CHARACTERSTCS (positive logic, VGG= - to -3V, VSS= 4.75 to 5.25V, T amb = 0 to 70 C unless otherwise specified) NPUT SGNALS Parameter Test conditions Min. Typ. Max. Unit V'H nput high voltage note Vss-2.5 Vss V note 2 Vss-l Vss V V'L nput low voltage note VGG Vss-6 V note 2 VGG Vss-4 V Ll nput leakage current Vj=Vss-4V T amb = 25 C 0 JA 7

112 25 STATC ELECTRCAL CHARACTERSTCS (continued) Parameter OUTPUT SGNALS RON VOH Output resistance Output high voltage 0 (0) Output leakage current POWER DSSPATON GG Supply current CHORD OUTPUT SGNAL bov o RL Ro Vo Variation in output voltage (for each note) External resistance connected between the output and V GG Output dynam ic resistance Output voltage when no note is present Note : Refers only to the F3 - F24 inputs Note 2: Refers to the other inputs With the exception of the chord output Vo=Vss-l to Vss 0 = ma Test conditions V, -V'H Vo-Vss-l0V T amb= 25 C T amb = 25 C RL =5kil RL =5kil Min. Typ. Max. Unit il Vss 0.5 Vss V 0 la ma.5 2 V 5 kil 0 Mil VGG+B VGG V DYNAMC ELECTRCAL CHARACTERSTCS (positive logic VGG= - to -3V. VSS= 4.75 to 5.25V. Tamb= 0 to 70 C unless otherwise specified) f, High input frequency (F 24) tl t2 t3 t4 t5 t6 Delay time of the internal phases Length of the internal phases Parameter Set-up time between data N and F24 Hold time between F24 and data N Delay time between falling edge of external memory code and TDA or TDB Delay time of the internal strobe pulse t, Length of the internal strobe pulse T T2 Period of external code pulses Return to zero or no significant external code T is the period of F24 with duty-cycle of 50% All the times are measured at 50% of the swing Min. Typ. Max. Unit 4 2 khz ls ls 0 T/4 ls 30 T/4 ls lo5t 2.5T ls T 2T ls T2 ls 3T ls 2T ls 8

113 '. of)... no.. Output voltage vs. external supply voltage (VEXT-VSS) 's, '. r;m r::-~n -...! Lal0kO... [.u.u YGG YSS.. 7V V. (mv) '00 Output voltage vs. supply voltage (VGG-Vss), '. ~ -- '00 RL.5Q lo.n = $ln VOO-VSS (-V) RO (leo),.& ' Output dynamic resistance vs. output voltage. +-+j oo-"'ss"-l~ ' Y.L 7V 'j~'ov ll 'L h...-u:: ~ J. 0 Yo (V) With the exception of the chord output TMNG WAVEFORMS (positive logic) nternal phases (f/> and f/> 2) and timing for data inputs T MAV CHANGE MUlTPLEXED... uttplexed DATA N nternal strobe, internal code and TOA or TOB as a function of the external code EXTERNAL CODE " '5 NTERNAL CODE ~' ~ -J' TO... or TOB ARPEGGO or BASS OUT 9

114 .25 TYPCAL APPLCATON _,T. 22,,~." ffiii VSS VSS L"'" 3..0 :,nf.e u 9 kn ~ '0' kj\ 3O~ _,Tl 5n 28~ ~~ 26~ ~.. T2 r 24~ ':' """ F24A 22kO 'OkJ\ V Be207 22~ M087 _,. Tl4 5n '00 20 rill--- S6A ~ TONE,.nl ~" 8,.,~T2 rf-!-- GENERA'CJl,. 6 rfl--- '>,T24 5kft " rf-l-- 2~ ", 0~ GENERATOR 36 ~ 3":.," rog l!illn -2V :.. 7~ ~~. SkO RP.l EXT. " " ~, 5". """ RR J', 'S'".L'o,AUT. BASS 38, ARP.J Skil J', ALTER.8ASS M 25.sv RESET MAH. sko Skll ec206 AUT. o.~ ~ o.l~~ tkn.. TOA "kjl ktl LATCH BelO? ;, " 'C ' LArCH -2V 'SS 8 TO. 820n t:" TSO J 0' 07 ~ SOkn " ~ ~ kn 22 7 kn r M 252 0' '50kJl kn M 253 ~ii:'o"f ~ M 254* 02 2 [ 5kO EXTERNAL ~ MEr.«lRY 0'.50kJl ~-: ~ 4 'y' ~.kn : : '50,," 'GG." :~: leon 0' 0', JJ~pF 22kO 22kO un::!: ~ :.6. Yolum. r- 'D "'" BASS "kjl 22kQ 22kO 22kO OUT =E 47nF tonf +onf (to P' CHORD t8kjl 22"" ~, 'Okn~ ±,onf l00ko ~, L_L!.Q_J Yo'.O<J\ Y ':::l Be20? 07 _.) '00 All dio ar.'n94a or similar F'hotot'.EA00rf'slstor MORRCA -,2V!o-U~72 For this application a version of the M 254 with standard memory content S available both for nterfacing with the M 25 and for driving 4 instrument simulators (8 rhythms) Ordering numbel is M 254 AD. 20

115 k.os NTEGRATED CRCUT M252 RHYTHM GENERATOR,. LOW POWER DSSPATON: < 20 mw DRVES 8 COUND GENERATORS (NSTRUMENTS) 5 PROGRAMMABLE RHYTHMS (NOT AVALABLE N COMBNATON) MASK PROGRAMMABLE RESET COUNTS: 24 or 32 DOWN BEAT OUTPUT EXTERNAL RESET OPEN DRAN OUTPUTS STANDARD MUSC CONTENT AVALABLE TECHNCAL NOTE NO 3 AVALABLE FOR FULL NFORMATON The M252 is a monolithic rhythm generator specifically designed for electronic organs and other musical nstruments. Constructed on a single chip using low threshold P-channel silicon gate technology it is supplied in a l6-lead dual in-line plastic package. ABSOLUTE MAXMUM RATNGS* Source supply voltage nput voltage Output current (at any pin) Storage temperature Operating temperature -20 to to to 50 o to 70 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condition above those indicate in the "Recommended operating conditions" section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. This voltage is with respect to V ss pin Voltage. ORDERNG NUMBERS: M252 B XX for dual in-line plastic package M252 B AA and AD for standard music content V V ma C C MECHANCAL DATA Dimensions in mm ~ Q~ ~::::::: M252 8XX SuDersedes issue dated 3/77 2 /79

116 M252 CONNECTON DAGRAMS Standard content configuration M252 8 AA Standard content configuration M252 8 AD,NPUT 4 ~ NPUT 2 [ NPUT Z NPUT 4 NPUl2 NPUT a.. ~ NPUT bur PUT " OUTPUT 4 OUTPUT J ~ OUTPUT] OUTPUT 6 " OUTPUT 2 OUTPUT 5 OUTPUT EXTERNAL RESET,.. 0 OOWN -BEAT CLOCK VG. Vss ::t... ~~ ",0 [ 2 MARACAS [l ~ ~ SHORT CVMBALS [... ""' LONG n> CYMBALS [ ~~ CONGA DRUM [. EXTERNAL RESET/ 'OOWN-BEAT '" CLOCK [. 5 inpdt""i. low BONGO HGH BONGO." SNARE DRUM OR CLAVES BASS ORU,", 0 V.G, VSS ~ ~ 0 ~ ~ NPUT B,. inpui cow BELL. low... 0 LONG CYMBALS,... o. CL.tNES SHOAT CYMBAlS 2 HGH HAT EXT. RESET,.. 0 OOWN BEAT CLOCK HGH BONGO SNARE DRla4 or CONGA OAl.lllll MSSDAU -00 Ys.!o-Ot/4 s.o> 2 S-""'tt This output must be con'lected so as to drive the "snare drum" when the rhythms from to 9 (see rhythm selection) are selected, and the "claves' when the rhythms from 0 to 5 (see rhythm selection) are selected. This pin generates a down-beat trigger which can be used to drive an external lamp to indicate the first beat of the first bar of each rhythm. This output must be connected so as to drive the "long cymbals' when the rhythms number,3,4,2 and 4 are generated, and the "claves" when the rhythms number 5, 8, 9, 0, and 3 are generated. This output must be connected so as to drive the "snare drum" when the rhythms number,3,4,6,7,9,2,4 and 5 are generated, and the "conga drum" when the rhythms number 5, 8,0, and 3 are generated. RHYTHM SELECTON The following binary code must be generated to select each rhythm (positive logic) RHYTHM CODE STANDARD STANDARD NPUT 8 NPUT 4 NPUT 2 NPUT CONTENT-AA CONTENT-AD 0 Waltz 3/4 Waltz 3/4 2 0 Jazz Waltz 3/4 Tango 2/ Tango 2/4 March 2/4 4 0 March 2/4 Swing 4/ Swing 4/4 Mambo 4/ Foxtrot 4/4 Slow Rock 6/ Slow Rock 6/8 Beat 4/4 8 0 Pop Rock 4/4 Samba 4/ Shuffle 2/4 Bossa Nova 4/ Mambo 4/4 Cha Cha 4/ Beguine 4/4 Rhumba 4/ Cha Cha 4/4 Beguine 4/ Bajon 4/4 Bajon 4/ Samba 4/4 Foxtrot 4/ Bossa Nova 4/4 Shuffle 2/4 No selected rhythm 22

117 M252 BLOCK DAGRAM 3840 BTS MATRX MULTPLEXER 24 STAGE RHYTHM DETECT~ OCM'N BEAT (DB) STATC ELECTRCAL CHARACTERSTCS (positive logic, VGG= -.4 to -2.6V, Vss= 4.75 to 5.25V, T amb= 0 to 70 C unless otherwise specified) CLOCK NPUT V H Clock high voltage V L Clock low voltage Values Parameter Test conditions Unit Min. Typ. Max.... DATA NPUTS (ln NS) VH nput high voltage Vss-.5 Vss V V L nput low voltage V GG V ss-4. V Ll nput leakage current Vj V ss-0v T amb- 25 C 0 /la EXTERNAL RESET V H nput high voltage VSS-.5 VSS V LV L nput low voltage L VGG Vss-4. V RN nternal resistance to V GG Vo - V ss-5v Kn DATA OUTPUTS RON Output resistance (ON state) Vo - Vss- to Vss n VOH Output high voltage L = rna Vss-0.5 Vss V LO Output leakage current Vj- V H Vo - V ss-0v 0 /la T amb= 25 C POWER DSSPATON Supply current 7 5 rna 23

118 M252 v, (mv) ''0 20 '0 '0 Output voltage vs. external supply voltage (VEXT-VSS) -" " 6 Vc,r. v[u 2 k V, (mv) 50C '00, '00 Output voltage vs. supply voltage (VGG-Vss ) r----- ~ y~~ '0 " -co -. :--EJ- RL o5ko lokn lsko '''" 2 3 S 6 7 "GG -'ss (. v) O' Output dynamic resistance vs. output voltage r- C..l~3 vgg-vss~ l'v/,/-'" A 'f'" /. /h /b ::::;;F="'" -- DYNAMC ELECTRCAL CHARACTERSTCS (positive logic VGG= -.4 to -2.6V, Vss= 4.75 to 5.25V, T amb= 0 to 70 C unless otherwise specified) Parameter Test conditions Min. CLOCK NPUT Values Unit TVp Max. Clock repetition rate DC 00 khz. tpw Pulse width 5 LS tr ** Rise time 00 LS tf* * Fall time 00 LS EXTERNAL RESET Pulse width 5 Measured at 50% 0 the swing. Measured between 0% and 90% 0 the swing. 24

119 .-r- -.~ M252 TMNG WAVEFORMS (positive logic) n.,, BT seauence'-'-----''--''-.:;n..:..!.l_-'-' -'_---'_--L_----'~_'_; : 32 CLOCK NPUT EXTERNAL RESET OUTPUT SGNAL EXTERNAL NSTRUMENT DOWN-BEAT.,, -oll ~_tpw 'ow ~r---ll ~:,, L:,,, L- ~ ~ ~ ~------~\HU~--~~~~~ ~,, ~ ~r----l~ ~: ~ ', NSTRUMENT BEATS VERSUS RHYTHM PROGRAM EXTER CLOCK z o >= u w a: a Count to 32 ''''ote: n these timing waveforms it has been assumed. for example, that in the truth table bits n + and 2 have Ot been programmed i.e. the musical instrument has not been intraduced. All the other bits have been pro grammed for the intraduction of the instruments. f TRUTH TABLE (Rhythm program) 0 U T P U T U U U T T T P P P U U U T T T X ~ U U U T T T P P P U U U T T T ~O ~~ - i,><; ~ ~ -F t-. ~ ::8:... c EXTERNAL DEVCE OUTPUT SGNALS RESET 0 G U U U U U U U U U T T T T T T T T T P E-g P P P P P P P P U ~" U U U U U U U U -.0 T >- T T T T T T T T 8 :> a: ~"' C ft""a- j;><... X r,- L- -- t-.~ t-... X L- t--~- t- X, '- f-~- ~ ~ ~- x f- -- X -g ~ ,... r - t- :- 5< ~ t-jo ~- _. ~ --- '- '- i ~ r-- - > ',,-t- ~ ',i-t-- - X f"-. '- f- - - ~~ --t- ~'~_.- -, r-~ X _._-.. - _. - 7 X -- L- -_. ~ 8 l-.- - i , r-! L-,' <' X 4- - f--. ~ '- ~8~ -- - ~- r- -. ~ - -fa- :-ii 32 lx X ~- -~ - c l- --- r-... f..": ~ ~: NSTRUMENT 8EATS* N N N N N N N N S S S S S S S S T T T T T T T T R R R. R R R. R R f~f+++~~++-f~down -H-+t-++-l~t+c8 EA T t+'h~++ GNAL ~ ~ > DOWN BEAT The lowering of the music signals depends on the ntrinsic decay time of the sound generator and not on the length of the enable pulses. Each beat can therefore last for more than one elementary time. 25 ~ ~ >

120 M252 TYPCAL APPLCATONS Figure shows the typical application of the M252 (AA) and M252 (AD). With two M252 devices it is possible to increase the number of rhythms or the number of instruments available, or the number of elementary times, as shown in figures 2, 3 and 4 respectively. The use of a memory matrix allows the customer complete flexibility, since modification of the memory is quick and relatively cheap. Fig. - Rhythm system (standard contents) a) M252 AA AHYTH"" CODES '~~~~--~~+-~H EXTERNAL RESET DOWN-BEAT S-'fJJJ/2 b) M252 AD ~-. o ~--- cow BELL " a M252 AD 5 5" 26

121 M252 TYPCAL APPLCATONS (continued) fig.2 - ncrease in number of rhythms (positive logic) Fig. 3 - ncrease in number of instruments EXTERNAL r---;::===+=+=+=+==t L.::===:fE~ss 8 ~ NSTRUMENTS NSTRUMENTS s-,m/j Fig. 4 - ncreasing the number of elementary times r--- VSS VARABLE CLOCK GENERATOR i S lmq /2 HBF Q ~ic'=~ 0 0 EXTERNAL Vs RESET c:::j lookn DOWN-BEAT 5 CLOCK M252 ~~~~ ~ f NSTRUMENTS NPUTS EXlER. ClOCK RESET M252 2 ' 5-lOn/, r Note: The total number of elementary times is given by the sum of the elementary times of the individual devices. 27

122 M252 CRCUT FOR CHANGNG THE NUMBER OF ELEMENTARY TMES DOWN - BEAT 'ss (DB) [j===~~=!=j~n~st~r~um~e~n~t~6 inputl input" M [ NSTRUMENT 5 NPUT inpuf NSTRUMENT 4 3r-----r-~~'N~ST~R~U~ME~N~T=3~ NSTRUMENT VARABLE CLOCK GENERATOR RESET - To obtain a required number of elementary times "N" simply put a cross in the "N + " position of the column which now represents the reset output, rather than the 8th instrument. The DB output can be used as down-beat because it apperas at the beginning of each measure. Since the pulse is only 2-3s long it must, however, be stretched and buffered to enable it to drive a lamp. Full information on the use of the M252 in electronic organs and other applications will be found in Technical Note no. 3 available on request. COMPLETNG THE TRUTH TABLE The ROM truth table has been organized in 32 rows which represent elementary times and 20 columns (5 groups of 8) where each group represents a rhythm which has as its disposition 8 programmable instruments. To programme each rhythm one indicates (with a cross) in the appropriate boxes the timing for each beat required for each instrument. Each cross corresponds to a beat of the indicated instrument or, in logic terms, to the presence of a "" level (positive logic) at the output. The absence of a cross indicates that the corresponding instrument is not used in that part of the rhythm. Table and 2 show the standard music content programmed into M252 AA and M252 AD respectively. 28

123 ," M252 if ABLE (M252 AA) COUNT FOR 32 ~ L! 2 ~l5.~l.2.~ X ~ A~YTHM 2 ~ lhm l..!.l3.:i4s67~ l!l2j~ ~l2.~l.2.~ L>< X H-'C '~H.V AH rhm 5 ~ ~~~~~~~ ~~~~~~~~ ~ ~ ~~~~~ ~~~~~lrl~l~ ~ ~~ ~ ~ ~~~ ~, ~,;';'WW ~~~~;~~~ ~ ~ ~!~~!! W.~W i i ; ;; ;.!! ~ T ~l T!!!! ; ~ ~ ; l ~ ~ ~ ~~~ U llll ~ ~ lw lr ; L~ 3 5 Jltl~ ~ x ~ ~ ~ ~ _X }}""""" oj jlili:ij:::j:, """" """'; LX. -g::~ r- r f- A~_.- X.."..':C HM b A rhm AH' HM" HH' HM-"- ~ ~ COUNT FOR 32 X X :X 29

124 252 RHYTHM RHYTHM 2 RHYTHM 3 RHYTHM 4 RHYTHM o ( u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u U COUNT T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T FOR P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P 32 U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T X X X X X X X X X X X X X X X X X 2 3 X X X X X X X X 5 X X X X X X X X X X X X 6 7 X X X X X X X X X 8 9 X X X X X X X X X X X X X X X X X X X X 2 3 X X X X X X X X X X X X X X X 4 5 X X X X X X X X X X X X X X 6 7 X X X X X X X X X X X X X X 8 9 X X X P.- ~. - X X X X X 20 -?(. _. 2 X ~r-:: XX 22..!-x- f~-r- -' f~ X X.X X X 23 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 30 X X X X X X X X X X X 2 TABLE 2(M252 AD) COUNT FOR 32 RHYT~~~L TZ: RH' THM 2 (TANGO) RH' THM 3 (MAQCH) RHYTHM 4 (SWNG) RH' THM 5 (MAMBO) ~ ~~ fr~ ~ ~ ~~ ~ ~ ~~ ~~ ~ ~ ~ ~~~ ~~ ~~ ~~'~ ~~ ~ ~~ ~~ ~~~~ ~ ~.;; ~. ;;;. ~~~. ~ ~~. ~~. ~. ~ ~ W;, ~.~ ;.~ ~~.~. ~~ ~ ;,;, ;; ;;; ~.~ ~~!~ ~ ~~~ ~~ ~ ~ ~~ ~~ ~ ~ ~ ~~~ ~~ ~~ ~~ ~ ~~ ~ ~! ~~lq il:ii4 5 sl7a lli:i4567a l' i:i 455 7a '2 :i s7 X x X X X 'X X x X x X x X X X X' X X J _.- X X. X X_ X i x ~'' X X... f--,-, ~Xl. :, x '~ :.--( f-- - _. - m......_... X X ' i-rt.- X 30 x

125 M252 HYTHM b <JV\'l ~ r C~'!~ 'HM ',,~ HH' 'HMO_~ RH' 'HM" 'OU>O"-"'l>"_A,' ~-'!:!"'~ 0 ~H" CH.' ~ ~~ ~ ~,~? ~~W?????? ~~!~ ~~~???~ ~ ~?~?? ~~~~i~l~ ~~ ~~~;~i;!~ln~~~~~i~~~ ~ ~,! ~, ;, ;, ~ ~, ~ ;,~;,~,iww ';;i:!:,i:l: 32 :. ~~ T ~lllulul~~~~!~~~ flt3-hll2~w~j!~lil'j ~~!~~!~! ~~~~i!i!! ~~!~!i!! '2!34s~2 ~ ' S 6 ~l! ', 2 3 _ j~ l! 2~ ~ XX x X X X : X X X X X ~ L.c t-'-- _+'..x..x X..x..x..x i~, X LX..i '-X --, LX~ f~ x ~~ ~~ x X Lx l!<. X LX L". COUNT FOR ~' 't,-- f--~ '.. i';,.!!..,- '--"-,A Li<., '_;_ X i- LX, - f:: 'j'r ~-,,: "x ~j- 'x' t- ' txtx r- "x,. X, i- A, ~,,_ -,,- ~_x ~.-J fx-t-- J <~: X ;X.X i x- x X xl-, x ~, A t- trl.;. -"-"- t x Lx f- tx' i----:x--; _~lx t-- 'Y??i?: j X - r.8±:l L"-'-"i+-""X LX LX '//iii jx x xg- ~)('j:i. X X - f4"-3,: LX,- :~~-)((~'X xl x,,/"',)i: trr lx t-,- tr-- i.n ~' t---.i. x ± hlil~ffi,-,+x t -- -x~= r--.l LX i, j.ll t-- t- 32 A THM,4F( ;- RHYTH 'UN 'HYTH ' S, RH fm' "", ra( HYTH" ", ls UF :lmlrm,: ~~!~~ ~??~ ~ ~~?~??~ ~~~??~?? ~ r~ f~ ~ ~? ~? ~T~!~T T T ~Y ~ ':' ~~ ~~~! ' 2 ~ ~ Y ll'l ~ Y J..3.l4.~~28, 2 3 l_ s ~28 ' tl~j~8, lli S 7 8, S x x L)(..x X x X X X X X x X 6 X COUNT FOR ; ;.;;~, ;~,lt ;/;,W, ;, ;j;, t t ~H;,~, ~,;,~, t W;, WV ~, t ; ; ; ;, ; ~~ ~ LX x_ t--- Xf"- " ~,~ ~Xt)( e-.- ''::' -- --"-,",,- t- LX LX L~ -r-t-- -"- --- X lk- x --- x --'X tx' t _~x,~ LX LX ;,, l( LX i X x '- -" ~- -,- x;x ~ r- "" xi" x r~l- - " X...jx -i- t-- -~ --..x-t-- "-- r x -r-- i,:",;",;",;"""",:" --!-- -x' tx ll -- -r l- LX 3 rx: - r' ' --t- tx_ - t - "- -, t- fx t- itt, ii': ri.l

126 NTEGRATED CRCUTS M253 LOW POWER DSSPATON: < 20 mw DRVES 8 SOUND GENERATORS (NSTRUMENTS) 2 PROGRAMMABLE RHYTHMS (ALSO AVALABLE N COMBNATON) MASK PROGRAMMABLE RESET COUNTS: 24 or 32 DOWN BEAT OUTPUT EXTERNAL RESET OPEN DRAN OUTPUT STANDARD MUSC CONTENT AVALABLE TECHNCAL NOTE NO 3 AVALABLE FOR FULL NFORMATON M253 is a monolithic rhythm generator specifically designed for electronic organs and other musical on a single chip using low threshold P-channel silicon gate technology it is supplied in a dual in-line plastic package. LUTE MAXMUM RATNGS* Source supply voltage nput voltage Output current (at any pin) Storage temperature range Operating temperature range -20 to 0.3 V -20 to 0.3 V 3 rna -65 to 50 C o to 70 C Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condition above those indicate in the "Recommended operating conditions" section of this specification is not implied. Exposure to absolute maxii; mum rating conditions foe extended periods may affect device reliability. ~ This voltage is with respect to V SS pin voltage. trderng NUMBERS: M253 B XX for dual in-line plastic package M253 B AA and AC for standard music content MECHANCAL DATA Dimensions in mm E ) t - M253 B XX 33 /79

127 M253 CONNECTOR DAGRAMS Standard content configura tion M253 B AA '55 CLOCK NPUT CLOCK NPUT '55 ';s " EXTERNAL RESET! E)(TERNAL RESET 'GG DOWN-BEAT 'GG 23 'GG DOWN-BEAT. OUTPUT \ OUTPUT, BASS 5(lECTQN " ' H'GH-HAT LOW BONGO C,~ARE DRUM LONG CYMBALS r or OUTPUT 2 OUTPUT ORU. 0 CO"'GA DRUM Standard content configuration M253 B AC CLOCK 'f)ut EXTERNAL RESET DOWN_BEAT. ~i OUTPUT l OUTPUT, '~BA5S ~ SNARE DRUM,,, SHORl CVoBALS ~ LONG. CYMBALS ~ OUTPUT 4 " SHORT C'fto48AlS ~ e: OR CLAVES or CLAVES ~~ " BOSSA NOVA 44.,p BEGUNE " SAMBA 4/4 TANGO RHUMBA '" '", eha em... CH' CHA,. '" "p " ~ BEGUNE,. SWNG '0 BOSSA NOV" "p RUMBA J4,.uMBO SAMBA '" "p U ROell POP 44 SLOW ROCK BEAT '" " " "p NPUT 9.. OCH OUTPUT, ~ A HGH BONGO iiiplit NPUT 2 TANGO 2/4 NPUT 2 NPUT WALTZ inp'ij"fj" inputi5 SN..FFLE NPUT 4 " " NPUT 5 NPUT 8 SlOW ROCK ~ NPUT '7 SWNG $-WJ~/' ---- MARACAS ~ ~ ".OW FlON,,Q COW BELL -. This output allows the muscian to obtain a "basso alternato" accompaniment using two notes of his choice, This output must be connected so as to drive the "snare drum" when the rhythms corresponding to pins 7, 8, 9, 0,, 2 and 3 are generated, and the "claves" when the rhythms corresponding to pins 4, 5, 6, 7 and 8 are generated. t can also be used to modulate a chord played on the organ. This pin generates a down-beat trigger which can be used to drive an external lamp to indicate the first beat of the first bar of each rhythm. This output must be connected so as to drive the "snare drum" when the rhythms corresponding to pins 7,9,0" 2, 3, 5 and 8 are generated, and the "conga drum" when the rhythms corresponding to pins, 4, 6 and 7 are generated. This output must be connected so as to drive the "long cymbals" when the rhythms corresponding to pins 7, 9, 0 and 8 are generated, and the "claver" when the rhythms corresponding to pins, 4, 5, 6 and 7 are generated. BLOCK DAGRAM 3072 BTS MATRX MUL TlPlEXER 'EXTERNAL RESET RESET LOGC DOWN BEAT (DB) '------~ ~------~ o 34 NPUTS 6 2

128 253 f)tatc ELECTRCAL CHARACTERSTCS(positive logic, VGG= -.4 to -2.6V, Vss=4.75 to 5.25V, T amb = 0 to 70 c e unless otherwise specified) Parameter CLOCK NPUT VH Clock high voltage "V L Clock low voltage Test conditions Values Min. Typ. Max. Unit Vss-.5 Vss V VGG V ss-4 V DATA NPUTS (ln... N2) VH nput high voltage VL nput low voltage Ll nput leakage current ~XTERNAL RESET V H nput high voltage V L nput low voltage RN nternal resistance to V GG Vi = V ss-0v T amb= 25 C Va = V SS-5V V ss-.5 Vss V VGG V ss-4. V 0!LA Vss-.5 Vss V VGG V s s-4 V k.l bata OUTPUTS RON Output resistance (ON state) V OH Output high voltage LO Output leakage current Va = Vss- to VSS L = ma V i - V H Va - V SS-0V T amb= 25 C V ss-o 5 Vss V 0!LA POWER DSSPATON GG Supply current T amb= 25 C 7 5 rna Output voltage vs. external supply voltage (VExrVss) ~S "0 _ ~ " "ctg "UT ~.~ L =0; '0 'GG - 'ss;.,7' v. (my) '00 Output voltage vs. supply voltage (VGG-Vss ) G_'",, ~ -t L S'A, '" RL 50 Oka StO <u, Output dynamic resistance vs. output voltage ~ ~~ 00-V55 '8VL c. '~7.7V / ), /'6' ~ 2 ) 35

129 M253 DYNAMC ELECTRCAL CHARACTERSTCS (positive logic, VGG= -.4 to -2.6V, Vss= 4.75 to 5.25V, T amb= 0 to 70 e 0 unless otherwise specified) CLOCK NPUT Parameter Test conditions Min. Values TVp. Max. Unit f Clock repetition rate DC tpw * Pulse width 5 00 khz ls t("'* tf** Rise time Fall time 00 ls 00 ls EXTERNAL RESET tpw Pulse width 5 * Measured at 50% of the swing. * * Measured between 0% and 90% of the swing ls TMNG WAVEFORMS (positive logic) n.2 BT SEaUENCE"--::--~~n::-,-:,:---T"---'----.:--'r--:;--ril!! 32 CLOC~ NPUT EXTERNAL RESET OUTPUT SGNAL ~ ~~~ ~ :u-u-u- ' ': rlj ~~f:u~int -A~~ ~~A~-~\~~~-----~~ ~ DOWN -BEAT ~r--l~ ~ ~ 5-029/3 Note: n these timing waveforms it has been assumed, for example, that in the truth table bits n + and 2 have not been programmed i.e. the musical instrument has not been introduced. All the other bits have been programmed for the introduction of the instrument. 36

130 M253 NSTRUMENT BEATS VERSUS RHYTHM PROGRAM btter TRUTH TABLE EXTE RNAL DEVCE OUTPUT SGNALS!LOCK Rhvthm program RESET U U U U U U U U U U U U U U U Count U N T T T T T T T T T T T T T T T T to S P P P P P P P P P P P P P P P P T 32 U U U U U U U U U U U U U U U U R. T T T T T T T T T T T T T T T T X ex: Lt--~ 2 X l'= 3 LiX "- 4 L2S, l"- 5 X, X [2<; '- L'-: r-: X - X Lt:... -l~ l- X l':- -~}-t--i4 - 's, 6 X l"- l~ 8 9, 20 r-f X 2 X X X... "-," X '- t--: 25 4 X X ~ '- 26 r a- r-- -, 29 X ~ 30 X X, '-'- ~ 32, NSTRUMENT BEATS. N N N N S S S S T T T T R. R. R. R N N S S T T R. R. N S T R. 6 7,8 > OWN EAT GNAL ~ DOWN BEAT The lowering of the music signals depends on the intrinsic decay time of the sound generator and not on the length of the enable pulses_ Each beat can therefore last for more than one elementary time_ 37

131 M253 TYPCAL APPLCATONS Figure shows the typical application of the M253 (AA) and M253 (AC). With two M253 devices it is possible to increase the number of rhythms or the number of instruments available, or the number of elementary times, as shown in figures 2, 3 and 4 respectively. The use of a memory matrix allows the customer comple'te flexibility, since modification of the memory is quick and relatively cheap. Fig. - Rhythm ststem (standard contents) a) M253 AA v.. OQWN(OB) BEAT EXTERNAL lite (T 'Or r '"-~-~----'" M 253 AA " f ---~-----OVGG.. 22 ",--.. " j. ~-,,, +-- t" BASS SELECTON,s " ko kn kn L- - --t ~~... f 'fizz {)'GG 5-043/3 b) M253 AC DO'RN BEAT (OB) 9 ~ EXTERNAl ----~t-~:- ~~ ~-* '0, M253 " AC " " '0 " " 38

132 M 253 -'TYPCAL APPLCATONS (continued) Fig.2 -ncrease in number of rhythms ExTERNAL RESET V5S ----<f' Fig. 3 - ncrease in number of instruments EXTERNAL VSS~' OOWN.. ~_l-_~==~==========~---~ BEAT (08) VTHMS l' 2 3 RHYTHMS 24 DOWN BEAT (08) ~:~~~ (~OCK -~_---'~+_-- CLOCt\, ~~~~~ M253 M253 2 NSTRUMENTS NSTRUMENTS NSTRUMENTS S-0./3 The rhythms may be selected from both devices simultaneously. Fig. 4 - ncreasing the number of elementary times, Vss VARABLE CLOCK GENERATOR Mfl /2 Q HBF rck=~ T, '/0 EXTERNAL RESET c::::j OOkfl ----<0 Vss To OWN-BEAT -- CLOCK M253 ~~~~ NSTRUMENTS t 8 2 NPUTS EllER CLOCK RESEl '.L nf Note: The total number of elementary times is given by the sum of the elementary times of the individual devices. 39

133 M 253 CRCUT FOR CHANGNG THE NUMBER OF ELEMENTARY TMES "SS l ~-+----i---; NSTRUMENT 7 NSTRUMENT 6 ~ <>-t NSTRUMENT 5 NSTRUMENT 4 l ,------i-i'nstrument 3 VARABLE CLOCK GENERATOR RESET- To obtain a required number of elementary times "N" simply put a cross in the "N + " position of the column which now represents the reset output, rather than the 8th instrument. The DB output can be used as down-beat because it appears at the beginning of each measure. Since the pulse is only 2-3 /J-S long it must, however, be stretched and buffered to enable it to drive a lamp. Full information on the use of the M253 in electronic organs and other applications will be found in Technical Note no. 3 available on request. COMPLETNG THE TRUTH TABLE The ROM truth table has been organized in 32 rows which represent elementary times and 96 columns (2 groups of 8) where each group represents a rhythm which has at its disposition 8 programmable instruments_ To programme each rhythm one indicates (with a cross) in the appropriate boxes the timing for each beat required for each instrument. Each cross corresponds to a beat of the indicated instrument or, in logic terms, to the presence of a " level (positive logic) at the output. The absence of a cross indicates that the corresponding instrument is not used in that part of the rhythm. Table and 2 show the standard music content programmed into M253 AA and M253 AC respectively. 40

134 253 ['r, (M253 AA) R HM R HM R HM RHYTHM. RiYTHM 5 COUNT FOR 32 xx X x x xx x:x X X X x X X X X X X X X X -f--, f- -f- - -~:::t+=hn - r-r-:-l!_"-' f-t h;xct,-+--l' --r-,- --lx-f- -.,-+-,', X x. X'-t-r-- f- -X Xl,--._.:.::""":l-= EE~~+-LE"t--Ht---.k _ ;;.. " COUNT FOR ' U T P U T X RHYTHM 6 RHYTHM 7 RHYTHM 8 RHYTHM 9 RHYTHM o U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T P P P P P P P P P P P P P P P P P P P D P P P P P P P P P P P P P P P P P P P U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T G X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X x..x Lx X Lx X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X ----, X X X._~ X X.X,.::: X X f-- X '-'- 'x f- XX-.. - X,L,~ X_ X,~,X X --c-- t-- t-- --f-, - f- ' t--f- X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Xt-- _L X X X X X X ~H- X X X X X X X X X X X X X X X X X X X X X X X X X X X X 4

135 M253 RHYTHM o U U U U U U U U U COUNT T T T T T T T T T FOR P P P P P P P P P 32 U U U U U U U U U T T T T T T T T T X X X 2 3 X X 5 X X X 6 7 X X 8 9 X X X X X X X 2 X 3 X X. 5 X X X X 6 7 X X X 8 9 X X X P.X 22 f-r- 23 X X X 2' 25 X X X X X X X 28 X 29 X X X 30 X X 32 RHYTHM U U U U U U U T T T T T T T P P P P P P P U U U U U U U T T T T T T T X X X X X X X X X X X X X X X X X X X X X. r-.~ xx --f--- X X X X X X X X X X X X X TABLE 2 (M253 AC) COUNT FOR 32 X X x X X X X X X X X X X X X X X. X 2 X 42

136 M 253 RHYTHM 6,OW ROCK RHYTHM 7 (BEAT RHYTHM B (SAMBA) RH' THM SA NOVA) THM C <A- CH ~~~~ ~~ ~ ~ ~ ~ ~ ~ ~' ~ ~ ~~ ~ ~ ~~ ~ ~ ~~ ~~ lele ~ ~~ ~~ ~~ ~ e ~le COUNT! TT - W tlt FOR d ; tl~ 32 ~ ~~~ ~ ~ ~ i i, ~~ ~ ~:~ ~ ' ' ' ~ ~ f W: B 2 3, 5 i 7 s i j 45 s 7 8 i iilj 4 5 s ; 8 iii j 4 s s i 8, x x x x ' x x x x x xix x x x x xix xix x x * ~ ~! ~ ~, ~ ~ ~ ~ ~ ~ ~ ~ tl~ ~ ~ ~ ~ m ~~ ~ ~~ m x x ~ ~, x x x X : x X 'x x X >\ x x - XX,,+--,-,- - tx f-x_ -- x- -- fl<x x "- x ~ x x_ ~_x,- '-x - X x x :x x x x x x x x x x x ---,- ix RHYTHM (RUMBA) RHYTHM 2 (BEGUNE) o U U U U U U U U U U U U U U U U COUNT T T T T T T T T T T T T T T T T FOR P P P P P P P P P P P P P P P P 32 U u U u u u U 'J U U U U U U U U T T T T T T T T T T T T T T T T 2 3, , X X X X X X x 2 3 x x x x x X 4 X 5 x X 6 7 X X X X X X 8 X X X X X X X X x. 2 X 3 X X X X X 5 X X X 6 7 X X X X X 8 9 X X X X X X 20 X 2 X X X x 22 X X x x x x X 23 2' 25 x x X X X X X 28 X X X 30 X X X.. 43

137 DS NTEGRATED CRCUT r i M254 RHYTHM GENERATOR it DRVES 2 SOUND GENERATORS (NSTRUMENTS) OR SOME NSTRUMENTS AND M 25 OR M 08 5 BT COUNTER it 8 RHYTHMS PER NSTRUMENT, EXTERNAL RESET the M 254 is a monolithic rhythm generator specifically designed for electronic organs and other musical nstruments. Constructed on a single chip using P-channel silicon gate technology. it is supplied in a,4-lead dual in-line plastic package. i t [MJSOLUTE MAXMUM RATNGS*, GG** Source supply voltage -20 to 0.3 V fl." nput voltage -20 to 0.3 V to Output current (at any pin) 3 ma r 59 Storage temperature -65 to 50 C fop Operating temperature 0 to 70 C i* Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is ;. a stre"s rating only and functional operation of the device at these or any other condition above those indicated in r the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for t' extended periods may affect device reliability.,. All voltages value are referred to V ss pin voltage. " " RDERNG NUMBERS: M 254 XX for dual in-line plastic package " M 254 B AD for standard music content M 254 B AM for standard music content HANCAL DATA Dimensions in mm ~ $' T. llil. ~-ll't ~,..ct.t _ ~ +.2:5~!LiL Q.'&L _ t::::::] _. ]J.?~:... ~, ~-J52~- J.UJoer.~ecJ,e,~ issue dated /76 45 /79

138 M254 CONNECTON DAGRAMS M 254 B AM Standard M 254 B AD Standard content configuration content configu ration " CLOC( NPUT '55 EUfRNAl " '55 [ ClOC", NPUT E.llTERNAL 'GG 3 2l ELRfSET '00 2l RE Sf T 'GG RESET OUTPUT 22 8A<,5 DRU~ OUTPUT 2 BASS DRUM TRGGER (HOROS BAC,S ALTERNAT " (LOOl NPUT '" " :. 55 (00' OUTPUT 2 SNAPE SlRU~ OUTPUT (LAVES 00 CLAVE 5 OUTPUT J 0 OUTPUT 0 Hft;H BONGO SHORT 4 CVt.48A l 5 OUTPUT 4 OUTPUT, LOW BONGO (,OW 80N('0 S " TRGGER '. OUTPUT S OUTPUT SNARE DRUM DOWN BfAT CHORDS "., OUTPUT i OUTPUT 7 CYMBALS BRUSH " WALTZ DSCO WAl T SLOW ROCK "., '0. 7 POL"'''' BOOGE TANGO RUlrl4aA, "P ',p B' TANGO SLOW ROC( "... NG SA...., B5 BOSSA NOVA SAMBA BE AT BOSSA NOVA " "p " " " * This output must be connected so as to drive the "snare drum" when the rhythms corresponding to pins 9, la,,2 and 6 are generated, and the "claves when the rhythms corresponding to pins 3, 4 and 5 are generated. 2 to S drive the corresponding inputs of the M 25. ** These outputs must be connected so as to drive the bass switching inputs A, B, C of the M los. BLOCK DAGRAM TMNG WAVEFORMS (positive logic) Output words versus external reset CLOC( N- '5 " secuence :~::~~::::~~:::J:::J:::J:::: OuTPut WORD NTERNAL COUNTNG CONTROL NTERNAL , RESET S_U,,-.., -----~--- i '' 'j' ' ~"';,',:',' M., ~ EHE< "... "E~E 46 Output words versus internal reset CLOCK N '5 ETERNAL , ~ESET., SEQUENCE :~:J::~:::J~2:J:::::::::r::= OUTPUT WORD $-4' * External gating allows resetting of the variable clock generator to ensure that the beat starts exactly at the right moment. ** i=..... S; in this timing waveform it has been assumed that in the truth table all bits have been programmed.

139 M254 DEVCE DESCRPTON The M 254 contains a ROM which can drive 2 sound generators (instruments) with a se leetion of 8 r'hythms for each generator. An external clock drives a phase generator which produces complementary Dutputs, these signals are then divided-by-2, to produce the signals to enable the output buffers and ~ive a 5-stage binary counter. The outputs of the counter are decoded,being the 32 rows of the memory matrix which has 04 columns. The 04 columns are divided into 3 groups of 8. A multiplexer is used such that any number of columns in the 3 groups can be selected from to 8. Of the 3 groups in the memory matrix, 2 have buffered putputs via an enabling circuit (the enabling conditions being CS = "0" and at least one multiplex input at logic " "). The 3th group in the matrix controls the internal reset which is synchronised with the counter and!jdntrols the counting sequence. STATC ELECTRCAL CHARACTERSTCS (positive logic, VGG= GND; Vss= 4 to 8V; Tamb= a to 70 C unless otherwise specified) CLOCK NPUT Parameter Test conditions Min. Typ. Max. Unit VH Clock high voltage Vss-l V VL Clock low voltage Vss-l0 V DATA NPUTS ( ) VH nput high voltage Vss-l V VL nput low voltage Vss-l0 V Ll nput leakage current Vj=Vss-4V Tarnb= 25 C 0 /LA DATA OUTPUTS RON Output resistance (ON state) Vo=Vss-2V 2 kn.'oh Output high current Vss= 8V 00 p.a POWER DSSPATON GG Supply current VGG=Vss-8V Tarnb= 25 C 0 rna 47

140 M254 DYNAMC ELECTRCAL CHARACTERSTCS (positive logic, VGG= GND; Vss= 4 to 8V; T amb= 0 to 70 C unless otherwise specified) CLOCK NPUT Parameter Test conditions Min. Typ. Max. Unit f Clock repetition rate DC 00 khz tpw* td Pulse width Pulse delay Duty cycle = 50% 5 '5 5 '5 t r tf** Rise time Fall time T amb= 25 C 5 '5 5 'S Measured at 50% of the swing Measu red between 0% and 90% of the swi n9 TYPCAL APPLCATONS Figure shows the typical application of the M 254 AD. Figure 2 shows the typical application of the M 254 AM. With two M 254 devices it is possible to increase the number of rhythms or the number of instruments available, as shown in figures 3 and 4 respectively. Fig. - Rhythm and accompaniment system (standard contents). M 254 AD Fig. 2 - Rhythm and accompaniment system (standard contents). M 254 AM " - '... ~ f r ".. ~ t t t t ~ f ~ l f.. t- ~ ~ 48 j

141 M254!TYPCAL APPLCATONS (continued),. ~i ncrease in number of rhythms Fig.4 - ncrease in number of instruments ~ ~. ~~VGG('~~~ r;;:;;;.;-;;;-;l ;.,.'""S, " ~. 8 _G,!RHYTHMS NSTRUMENTS. " NSTRUMENTS RHVTHMS NSTRUMENTS COMPLETNG THE TRUTH TABLE lj"he ROM truth table has been organized in 32 rows which represent the elementary times and 04 tolumns., lrhe first 8 groups of 2 columns represent the rhythms which have 2 programmable outputs. The timing for the beats required for each instrument is programmed by crossing the appropriate box. The 9th group of 8 columns represents the COUNTNG control information which specifies the num ber of elementary times in a given rhythm. Jf count N is crossed for rhythm X this rhythm will have N elementary times. f the counting control 'column for a particular rhythm does not contain a cross that rhythm will have 32 elementary times. Table and 2 show the truth tables of the M 254 AD and M 254 AM, standard contents, respectively. t can be seen that in the table the rhythms and 8 and in the table 2 the rhythms,6 and 7, have 24 elementary times. 49

142 M254 M 254 AD (standard) RHYTHM WAL TZ RHYTHM2TA",G() RHYTHM 3_'SWNG COUNT FOR 32 L L 4 6.X 2- 'L 2-2-,.X_ ll...ll ix' x, x x '4_X_.-r"'- ',-- x L X x :x X,... P'- -.X L ~ RHYTHM 4 (BEAT) RHYTHM 5 (BOSSA NOVA) RHYTHM 6 (SAMBA) COUNT FOR 32 x_+_~_ x ~.~ X X X x x 50

143 --"-- M254 ~ ~ ~!~ n~ RHYTHM 7 RUMBA RHYTHM B SLOW ROCK) COUNTNG CONTROL COUNT FOR P 'p P P P 32 U UUUiU ~noo!~~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ : ~ : : : R: : : T ~ ~ : ~ ~ ~ ~. ~ ~ ~ ~ ; ;~ ; ~ ; ; ; ; ~~ ~ ~ : T T T T T T u u H ' H ~ ~! ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ; B ~,~o " i ~ : 6 7 B 9 ~ " ~2 2 ~l~ B ~ i'~ 2 X X X 4 ' X. X X -X 'X X X 2(l.-,-.' ~. _ L. X --"- X ',X X x -t " ~ - -, P'-t+ -r:::.-t-- --f-- ; _ ~r--- ~ c _., i--4x- j-!'-,-,"-.---,"- - ~.-. ~ :. x x x x x X 'x X X X t-- X x - -- ;.- 'xe- p~~_.. '.X -- X J,, x; '~.-- 'i-~.x X r f-- 26,,""'" '.. 28 '!'."!. r: 32 -r-' i? / " :.",.,., t--,n -..-,.. T ;, M 254 AM (standard) RHYTHM WALTZ) RHYTHM 2 (POLKA) RHYTHM 3 (TANGO) ;:r- t----f-:o:-r::o:-t::o-t::ot-'::'oto::--r-o::ct:oo=r:oc'r=o--.-::o--.::o +::-OTo::-ro:-r:o::-'r::o:T':oo-i: l'-=o:t=:o:t::'i-0", 0=-0 CO -0 CO m.: U U U U U U U U U U U U U U U U U U U U O U u lu u u u u u u u u u u u u U COUNT T T T T T T T T T T T T T T T T T T T T T T' T T T T T T T T T T T T T T FOR P P P P P P P P P P P P P P P P P P P P P P p p p p p P: p p p p p p p p 32 U U U U U U U U U U U U U U U U U U,U U U U U U U U U UU U U U U U U U T T T T T T T T T T T T T T T T T TiT TT T T T T T T TT T T T T T T T ' 8 9 0, t----:~98 _ "X+_+-' X" 'x x --tx X ~-t -X'.. x X x -f-x t--f~-!;-' _ px+_t-xq "x xt~ '4r:X "l-t--h--t---t t-----i~~i----t-x"-+-t----t-;;x+, -- x x x -+)(+'+XrX~ t ~+_ h x x tx---xf-x 4 5

144 M254 COUNT FOR RHYTHM 4 (BOSSA NOVA) o oro U U U U U U U U U U U T T T T T T T T T T T P P P P P P P P P P P U U U U U U U U U U U T T T T T T T T T T T X X X X X X x X X X X x x x x x X X X X X X X X X X X X X X X x X x X X X X x RHYTHM 5 (SAMBA) o 0 o U U U U U U U U U U U U U U U T T T T T T T T T T T T T T T P P P P P P P P P P P P P P P U U U U U U U U U U U U U U U T T T T T T T T T T T T T T T X X X X X X X X X x x x x X X X X X X X X X X X X X X X -+f t- -t++ x x x x X x x x X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X x x x x x x x x x X RHYTHM 6 (SLOW ROCK) o 0 o U U U U U U U U U U T T T T T T T T T T P P P P P P P P P P U U U U U U U U U U T T T T T T T T T T X X X X x x X X X X X X -- - x X x x x x X X X X X X X x X X _ --- ~ X X X - e- COUNT FOR 32 RHYTHM 7 (BOOGE) uuuuuuuuuuu TTTTTTTTTTT ppppppppppp UUUUUUUUUUU TTTTTTTTTTT x x x X x RHYTHM 8 (DSCO) UUUUUUUUUUUUUUU TTTTTTTTTTTTTTT pppppp ppppppp pp UUUUUU UUUUUUUUU TTTTTTTTTTTTTTT x x x x x x x x x 6 x x 7 X X X X XX x x x x 8 X 9 X x X X X X x x x COUNTNG CONTROL o UUUUUUUUUU TTTTTTTTTT pppppppppp UUUUUUUUUU TTTTTTTTTT

145 MDS NTEGRATED CRCUT RHYTHM GENERATOR ~ NTERNAL TEMPO OSCLLATOR, 6 PROGRAMMABLE RHYTHMS i DRVES 5 SOUND GENERATORS MASK PROGRAMMABLE RESET COUNTS: 2 or 6 DOWN BEAT OUTPUT EXTERNAL RESET LOW POWER DSSPATON: < 00 mw PN-TO-PN COMPATBLE WTH MM 587 PUSH-PULL OR OPEN DRAN OUTPUTS AVA LABLE STANDARD CONTENT AVALABLE,"he M 255 is a monolithic rhythm generator specifically designed for electronic organs and other musical nstruments. Constructed on a single chip using P-channel silicon gate technology it is supplied in a 6-lead dual in-line plastic package. f_ "BSOLUTE MAXMUM RATNGS* ". ** "GG V,"" fo ", rstg roil Source supply voltage nput voltage Output current for down beat (pin 3) Output current (at other pins) Storage temperature Operating temperature -20 to 0.3 V -20 to 0.3 V 20 ma 3 ma -65 to 50 C o to 70 C Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.... All voltages value are referred to V ss pin voltage. DRDERNG NUMBERS: M 255 Bl XX for dual in-line plastic package M 255 BlAB for standard music content MECHANCAL DATA Dimensions in mm ij ::::::: Blnerse,de.~ issue dated / /78

146 255 CONNECTON DAGRAMS RESET 6 ~RHYTHM 4 TEMPO CONTROL 5 ~RHVTHM 5 DOWN BEAT J 4 ~RHYTHM Standard content configuration M255B-AB RESET TEMPO CONTROL DOWN BEAT,. COUNTRY WESTERN 5 LATN,. TANGO VGG ] OUT VGG.3 ~CHORD TRGGER VSS 2 OUT 4 RHYTHM OUT RHYTHM 0 OUT 2 RHYTHM OUT VSS WALTZ BEAT SWNG / ~ FFTH SHORT ~ CYMBALS 0~ SNARE DRUM, BASS DRUM FUNDAMENTAL S 888 '!. 889/ BLOCK DAG RAM SELECTON BETWEEN 3/4 AND4/4 RHYTHMS DOWN BEAT OUTPUT 480 BT ROM OUTPUT LOGC A'O BUFFER TRGGER OUTPUTS RHYTHM NPUTS

147 GENERAL CHARACTERSTCS The M 255 circuit comprises: a) One pin for tempo control. The external network employs a capacitor and two resistors: one fixed and the other variable. h) Six pins for rhythm selection. nternal pull-down is provided for all inputs. Rhythms are selected by connecting to V ss the corresponding inputs. C) One pin for external reset. The reset is applied when pin is connected to V GG' During normal operation pin is connected to Vss. d) Five output pins. The following options are available: - push-pull outputs - open drain outputs - trigger outputs (no external pulse shaping required) - continuous outputs - active high or active low outputs. : Full details concerning these options are given later. e) Low impedance down beat output through which a LED can be driven. ') 2 supply pins.,operaton "hen the power supply is connected to the V GG pin, the internal oscillator starts driving the counter ~d strobe generator. As long as no rhythm is selected no signal can flow from the output section. The,output signal is present when one or more rhythms are selected. The internal counter has a 6 state (i.e. 6 elementary times) cycle and an internal reset signal is generated when the sixteenth state is decoded. ~hythms with a 3/4 time originate the internal reset when the 2th state is decoded. The down beat output is synchronized with the counter state and its duration equals that of one elementary time. :Rhythms with 8 or 6 elementary times are also programmable, in which case they are written twice in the ROM. The associated down beat signal can flow either every 8 (6) or every 6 (2) elementary times ilccording to the option chosen. When the external reset is applied the counter is reset to state and the Oscillator and strobe generator are stopped. The down beat output is ON during the entire external reset :ondition since the first elementary time is decoded. For the same reason the content of the first elementary time is immediately available on the outputs as soon as the external reset is removed. The trigger <rutputs are pulse shaped and their width equals /32 of one elementary time. Pulse width is proportional ~ clock period but always remains /32 of a beat time. The clock frequency can be controlled by the external Mohm potentiometer; the control range is greater than one decade. PROGRAMMNG THE OPTONS :rile five outputs of the M 255 may have different options which must be specified together with the flom truth table. This can be done as shown in the table below: ~ine T: i ~' 2 3 OUT. OUT. 2 OUT. 3 OUT.4 OUT. 5 Continuous or Trigger Output T T C T T Open drain or Push Pull Posit. or Negat. Trigger Edge Trigger: The output is in the form of a pulse whose width equals /32 of one elementary time. The pulse can be either positive or negative going according to the option chosen in line 3. 55

148 ' C Continuous. No pulse shaping is provided and the output goes high or low according to line 3 choice for the duration of one elementary time. f such an output is selected in two or more consecutive elementary times it will stay continuously high (low). o Open drain output. P Push-pull output. + The output is normally at V GG and goes high when active. The output is normally at V S5 and goes low when active. The following constraints must be observed: ) Only one of the five outputs may be continuous (C); the other four must be trigger (T). 2) f the open drain solution is used all outputs must be open drain (0). 3) f the push-pull solution is used all outputs labelled T must be push-pull (P) and the one labelled C must be open drain (0). The down beat signal can be programmed to occur either every S (6) or every 6 (2) elementary times. The choice is made as shown in the example below: Down beat X 6 (2) S (6) n this case the down beat signal occurs every S (6) elementary times irrespective of the fact that there might be some x6 or x 2 rhythms. STATC ELECTRCAL CHARACTERSTCS(Positive logic, VGG= -.5± 20%, Vss=+5 ± 20%, Tamb = 0 to 70 c C unless otherwise specified) Parameter Test conditions Min. Typ. Max. Unit RHYTHM AND RESET NPUTS VH High voltage Vss- Vss V VL Low voltage VGG Vss-4 V NSTRUMENT OUTPUTS Open Drain configuration RON Output resistance (ON state) RL=0K n VOH Output high voltage RL= 0 K Vss-0.3 Vss V LO Output leakage current VEXT.RES.= VH -0 la Tamb= 25 cc Push-Pull configuration RON Output resistance at high output OH= - ma. Vo= VOH level [VOL Output low voltage Capacitive load VSs-5.2 Vss-7.5 V VOH Output high voltage Capacitive load Vss-0.6 V RC nput: this input oscillates between two negative levels whose value depends on the supply voltage level. With VGG= -7 and Vss= OV, V RC low= -S.7V and V RC high= -3.2V. This input is protected, like the others, from electrical discharges. 56

149 M'255 STATC ELECTRCAL CHARACTERSTCS (continued) Parameter Test conditions Min. Typ. Max. Unit DOWN BEAT OUTPUT RN nternal resistance to VGG Vo=Vss-5V k! RON Output resistance (ON statel Vo-Vss-O.5V ! VOH Output high voltage Capacitive load Vss.. O.6 V [VOL Output low voltage Capacitive load V ss-7.7 Vss-0.7 V f PoWER DSSPATON ;GG Supply current Tamb= 25 C 0 (pin 3)= ma DYNAMC ELECTRCAL CHARACTERSTCS (Positive logic VGG= -.5 ± 20%, 5 ± 20%, t.mb= 0 to 70 0 e unless otherwise specified) Parameter Test conditions Min. Typ. Max. Unit rrempo CONTROL (RC Minimum tempo C to Vss= 6800 pf R to VGG=.05 M! 2.5" Hz Maximum tempo C to V ss pf R to VGG= 47 K! 35" Hz,. These values depend on power supply voltages and temperature. PERCENTAGE VARATONS of MAX. and MN. TEMPO DUE TO VGG and TEMPE ~ATURE CHANGES Parameter T est conditions Min. Typ. Max. Max. tempo variation due to V GG change VSS-VGG from 3 to 20V 4% 6% :Min. tempo variation due to V GG change VSS-VGG from 3 to 20V 4% 6%. Max. tempo variation due to temperature T from 25 C to 70 C 2% 3% change.min. tempo variation due to temperature T from 25 C to 70 C 2% 3% r,change '. 57

150 '255 TYPCAL APPLCATON FOR M 255 B-AB '! r~~ " 0 '! ~ ~f "0,, 'FE.0 '''~ '- [.0 [ "*, 6 ' ' kl ' ' '" "'",----, - ~~OO~ i 6 M255 B-AB 9 i... t t t t TRGGER FOR NSTRUMENTS ~~ 0 V55 COMPLETNG THE TRUTH TABLE The ROM truth table has been organized in 6 rows which represent the elementary times and 30 columns (6 groups of 5). The timing for the beats required for each instrument is programmed by crossing the appropriate box. The options for outputs and down beat must also be filled in as explained. Table shows the content and the options programmed in the M 255 B l-ab standard content. TRUTH TABLE of M 255 B-AB (standard content) RHYTHM RHYTHM 2 RHYTHM 3 RHYTHM 4 RHYTHM 5 RHYTHM 6 X x x x x x x x x xix x x x X 2 X x X x 3 X x><-~ ~_ x x x ~ x x xxx x xx xxxx x _~ x x x x x x x x x ~ x x x _K x x x 2 X xx xix x xx x xx xlx,xxx 8 X X X 9 X x x x. x x x x x x x X 0 x x x x x x x x x x x X x x x x x x x 2. x x x x x x x x :!i;jjjjjj;i!r;;)'i_i,j;~ x x ~ x ~ ~ x x X 5 ibn/ii/sr; x x } x x x x x x x x 6:::-::,::}{c{xr?:: x x x x~:: x x x x --""!i0"- on the Outputs (2 8 (i),or rigger Output Down beat X ~n drain or push-pull Positive or Negative Trigger Edge

151 NTEGRATED CRCUTS M258 M259 PRELMNARY DATA 6 PROGRAMMABLE RHYTHMS (CODED FOR THE M258; ALSO AVALABLE N COMB NATON FOR THE M259 6 OUTPUTS (2 SECTONS BY 8) MASK PROGRAMMABLE RESET COUNTS (24 or 32) DOWN BEAT OUT SYNC OUT EXTERNAL RESET TWO CHP SELECTS (CS, CS2) FOR SEPARATE TRSTATE CONDTON OF THE TWO OUT PUT SECTONS NTERNAL PULL-UP ON THE NPUTS OPEN DRAN OUTPUTS WTH RETURN TO "" STATUS CHOCE BETWEEN RETURN TO "" OR NOT ON 8 OUTPUTS (OUT,2,3,4,9,0,,2) SEPARATELY ONLY ONE POWER SUPPLY (+5V) VERY LOW POWER CONSUMPTON (50 mw TYP.) M258, M259 are monolithic rhythm generators specifically designed for electronic organs and other instruments. on a single chip using MOS N-channel silicon gate technology, they are suppl ied in a 28 lead (M258) or 40 lead for (M259) dual in-line plastic package. ~".tl lr.t"rl ~SOLUTE MAXMUM RATNGS* Source supply voltage nput voltage Output current (at any pin) Output voltage Storage temperature range Operating temperature range -0.3 to to to + 25 o to 70 V V ma V C C "Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is,- a stress rating only and functional operation of the device at these or any other condition above those indicate in ; the "Recommended operating conditions" section of this specification is not implied. Exposure to absolute maxi mum rating conditions for extended periods may affect device reliability. r* All voltages are with respect to Vss (GNDi.»RDERNG NUMBERS: M258 Bl for dual in-line plastic package M259 Bl for dual in-line plastic package 59 /79

152 M258 M 259 MECHANCAL DATA (dimensions in mm) Dual in-line plastic package (28 lead) Dual in-line plastic package (40 lead) ~EEF _4~' ~~M O~ L::: ::::::: :::::~ CONNECTON DAGRAMS v DD 28 VDD GND 27 CLOCK OUTPUT *26 RESET/SYNC. OUTPUT 9 25 OUTPUT 6 OUTPUT2 **24 DOWN BEAT OUTPUT OUTPUT 8 NPUT 22 OUTPUT 5 OUTPUT 3 M258 2 OUTPUT 7 NPUT 2 20 NPUT 4 OUTPUT" 0 9 NPUT 3 OUTPUT 4 8 OUTPUT 4 OUTPUT OUTPUT 6 CS 3 6 OUTPUT3 CS U'fiiJfS S#3375 CS enables the outputs 0 to 08 CS2 enables the outputs 09 to 6 VDD 40 VDD GND 39 CLOCK NPUT 38 NPUT 6 NPUT 2 37 TNi>ufii OUTPUT 5 * 36 RESET SYNC. 0iJ'i'50T ffiiTlJ OUTPUT2 ** 34 DOWN 8En OUTPUT Ufiiiifi NPUT J 32 'OiJfPUTii NPUT 4 0 M UiPiiT"7 NPiifi4. OUTPUT3 30 " NPUT NPUTt3' OUTPUT" 3 28 NPUT,z NPUT 'inpufii OUTPUT iJfPiiii4 OUTPUT NPUTO NPUT lifPU'i NPUT 'inputi C iiiPuTii C iufjijf This is a bidirectional pin. Used as an input it allows the chip reset; used as an output it can reset other devices This pin generates a down beat trigger which can be used to drive an external lamp to indicate the first beat of the first bar of each rhythm. - 60

153 0- M258 M 259 ESET AND DOWN BEAT TMNG WAVEFORMS (POSTVE LOGC) ELEMENTARY TMES EXTERNAL RESET (USE D AS AN OUTPUT) 3 32 u DOWN BEAT S-l]'77{ LOCK DAGRAM logc '" J.:l--D- MC'L:J.Q L. o:tl ~ HlooO DEffC'. o D --.. ~ --'' ': ( n the M259 the rhythm selections enter the chip already decoded) ~HYTHM, SE LECTON (for M258 only) 6 Rhvthm iii4 N3 iii2 Ni - 2,, 0 3, 0 4,, 0 0 5, 0 6, 0 0 7, , 0 0, D , 0 D '3 0 0,, '4 0 0, 0,

154 STATC ELECTRCAL CHARACTERSTCS(positil!!! logic, Voo= 4.75 to 5.25V, T amb= Oto 70 C unless otherwise specified) - Parameter Test conditions Values Min. Typ. Max. Unit CLOCK NPUT V H V L Clock high voltage Clock low voltage DATA NPUTS (lnl to iii4) V H nput high voltage 2.4 Voo V V L nput low voltage V RN nternal resistance to Voo V=OV Voo= 5V Kn OL(*) nput load current V = V L -50 /JA EXT. RESET V H nput high voltage 4.5 Voo V V L nput low voltage 0.5 V ROFF nternal resistance to Voo (inactive sync! Vo=O Voo=5V Kn RON nternal resistance to Voo Vo=lV Voo= 4.75V n (active sync). OUTPUTS (Oi. Down beat) RON nput internal pull-up Vo=lV n VOL nput internal pull-up Source current = rna V LO Vo= 2V T amb= 25 C 0 /JA POWER DSSPATON Supply current T amb= 25 C 30 ma (*) The "High Level ' is clamped by the internal pull-up

155 M258 M259 DYNAMC ELECTRCAL CHARACTERSTCS (positive logic, V DD= 4.75 to 5.25V,,T amb = 0 to 70 0 e unless otherwise specified) Parameter CLOCK NPUT f Clock repetition rate tw Pulse width tr Rise time tf Fall time Test condistions Values Min. Typ. Max. Unit DC 00 KHz Measured at 50% of the swing 5 ls Measured between 0% and 90% of the swing Measured between 0% and 90% of the swing 00 ls 00 ls EXT. RESET Pulse width te R Clock delay with respect to reset TMNG WAVEFORMS BT SEQUENCE n STOP 32 CLOCK EXTERNAL RESET OUT SGNAL WTH RETURN TO.. " OUT SGNAL WTHOUT RETURN TO"" EX TERNAL NOSE GENERATOR SYNC. DOWN BEAT ~ ~L.. ~ U "---_... r

156 M 258 M 259 Note : This additional pulse, to reset the outputs without return to " ", can be obtained by using a clock generator as shown in the following diagram: P-----J~ e Loe K ~ ~--~--~~ RESET/SYNC. s- ]3':'8 Ext. Reset/Sync. is a bidirectional pin. Used as an input it can reset the circuit as shown in the timing diagram and used as an output it can drive the reset of other devices. Using the clock generator shown in the above figure, when the switch is closed asynchronous with respect to the clock, it is possible to have to two cases (see the following diagrams); in both the cases the output reset can be obtained by CS and CS2. CLOCK EXTERNAL RESET (0) L--+:_" (b) L- :, OJ(WTHOUT RETURN TO''''') -----!.,, : ' i T ---v------, ,~.: J T 5-)]79 n both the cases the delay T (in the outputs without return to "") is defined through the constant R C ~ 0 ijsec. 64

157 ~ M258 M259 NSTRUMENT BEATS VERSUS RHYTHM PROGRAM TRUTH TABLE EXTERNAL DEVCE OUTPUT RESE T SGNALS NSTRUMENT BEATS SYNC. DOWN BEAT 8 9, 0 0 U U T T 5.* X X X X X [X 0 0 U U w T T '" u 0...J ~!, 5 :: - > :: 0 a: w r...j m z '" w - '" ~ :: l- > :: a: i i : -' 0", '" 0 0",o", > >»» "' '". ' N S T R 5 r-- -;;~ -:;~ i --.~ : :i > r-. ---~ r---< f------~ ----' ~ f------< 0 >.> i ~ f- i! i i *OUTWTHOUT RETURN TO"'''-**OUT5WTH RETURN TO"'" 5.]]5)/ Note: The outputs 0 to 08 are enabled by CS; the outputs 09 to 6 are enabled by CS2. The outputs 0 to 04 and 09 to 2 are programmable separately without return to "". 65

158 i ~. reos/mos N T E G RAT E D C R CU T M702 L ~ STAGE COUNTER '. LOW QUESCENT POWER DSSPATON WDE SUPPLY VOLTAGE RANGE: 3to 5V '. HGH NOSE MMUNTY: 45%of Vee (TYP.) c. NPUTS FULLY PROTECTED NVERTER AVALABLTY N CRYSTAL OSCLLATOR MPLEMENTATON FOR TMNG APPLCATONS The M (extended temperature range) and M 702 0/B (intermediate temperature range) are l6-stage binary countes constructed with COS/MOS technology in a single monolithic chip. The devices may be used as timing circuits the chips consists of 6-flip-flop, input inverter for use in a cristal oscillator, and an output buffer capable of driving standard stepping motors. The device is available in 8-lead dual in-line miniature plastic package and 8-lead metal-can. ABSOLUTE MAXMUM RATNGS * Supply voltage nput voltage (at any pin) Total power dissipation (per package) Storage temperature Operating temperature: for 02 type for 0/B type -0.5 to to Voo to to to 85 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. This voltage value are referred to V ss pin voltage. V V mw C C C ORDERNG NUMBERS: M for TO-99 metal can M for TO-99 metal can M 702 B for dual in-line plastic package MECHANCAL DATA Dimensions in mm TO-99 metal can Dual in-line plastic package H bd 67 /79

159 M702 CONNECTON DAGRAMS Voo Voo 7 NVERTER 6 NVERTER V55 NC 0;, _052 LOGC BLOCK DAGRAM F/F F/F ~ F/F 6 :' RECOMMENDED OPERATNG CONDTONS Voo Supply voltage: for general applications for crystal oscillator in clock applications nput voltage Operating temperature: for 02 type for 0/B types 68 3 to 5 7 to 5 o to Vee -55 to to 85 V V V C C

160 M702 STATC ELECTRCAL CHARACTERSTCS (Over recommended operating conditions) D2 type (extended temperature range) Paramatar Tast conditions Valuas ~-, ~ ---- Vo Voo -55 C 25 C 25 C (V (V) Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. L Quiescent sup ply current VOH Output high voltage 0= VOL Output low 5 0.Q voltage 0= V NH Noise immunity VNL Noise immunity ON Output drive cur , 8 rent N-channel ~OP Output drive cur rent P-channel ' H.. L nput leak.current Any input 5 ± ± 0-5 ± ± D/B types (intermediate temperature range) Unit /la V V V V rna rna /la Paramatar Tast conditions Vo Voo (V) (V) Valuas._--_ C 25 C 85 C Unit Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. il Quiescent sup ply current VOH Output high voltage 0H= VOL Output low 5 0.Q voltage 0L= VNH Noise immunity VNL Noise immunity ON Output drive cur rent N-channel lop Output drive cu, rent P-channel jh.l nput leak.curren Any input 5 ± ± 0-5 ± ± /la V V V V rna rna /la 69

161 M702 DYNAMC ELECTRCAL CHARACTERSTCS (T amb= 25 C, C L = 5 pf, typical temperature coefficient for all Voo= 0.3%/oC values, all input rise and fall time = 20 ns) T est conditions Values Parameter Voo M70202 M7020/8 Unit r----- (V Min. Typ. Max. Min. Typ. Max. twh, Minimum input twl pulse width ns t r, nput clock rise and tf fall time f max Maximum clock frequency MHz C nput capacitance Any input 5 5 pf ls TYPCAL APPLCATONS Digital equipment in which ultra-low dissipation and/or operation using a battery source are primary design requirements. Accurate timing from a crystal oscillator for timing applications such as wall clocks, table clocks, automobile clocks, and digital timing references in any circuit requiring accurately timed outputs. Driving miniature synchronous motors, stepping motors, or external bipolar transistors in push-pull fashion.. Electronic watch application circuit 70

162 :OS/MOS NTEGRATED CRCUT M706, PRELMNARY DATA e-stage COUNTER LOW QUESCENT POWER DSSPATON.~ WDE SUPPLY VOLTAGE RANGE: 3 to 6V ~ FULLY PROTECTED NPUTS NVERTER AVALABLTY N CRSTAL OSCLLATOR MPLEMENTATON FOR TMNG t APPLCA non irhe M 706 is a 6-stage binary counter constructed with COS/MOS technology on a single mono lithic chip. The device may be used as timing circuit. t consists of 6 flip-flop~. input inverter for use in crystal oscillator and two output buffers providing push-pull bridge operation. The device is available n a-lead minidip. ~BSOLUTE MAXMUM RATNGS* U ",cc ~!'tot Tstg :rop Supply voltage nput voltage (at any pin) Total power dissipation (per package) Storage temperature Operating temperature -0.5 to 6 V -0.5 to Vco +0.5 V 200 mw -65 to 50 C -40 to 85 C ',. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is s stress rating only and functional operation of the device at these or any other condition above those indicated in, the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. This voltage is with respect to Vss (GND) pin voltage., ORDERNG NUMBER: M 706 B ~ECHANCAL DATA f Dimensions in mm Tf!~l A M ~~~ Q4S :,~ i ~ 7.6_~ 8 7 /79

163 M706 CONNECTON DAGRAM NC OUTPUT 2 8 ~ 7 ] q, NVERTER [ 3 6 NVERTER NC [ 4 S LOGC BLOCK DAGRAM FF X F/F L FF 2 n..rl 6 NVERTER vss6s L..._--' X X DUTY CYCLE =50"0 Jl..Jl.. RECOMMENDED OPERATNG CONDTONS Supply voltage: for general applications for crystal oscillator in clock application nput voltage Operating temperature 72 3 to 5 7 to 5 Oto Voo -40 to 85 v V V C

164 . M706 TATC ELECTRCAL CHARACTERSTCS (over recommended operating conditions) Parameter Test conditions Values at 25 0 C VO (V Voo(V Min. Typ. Max. Unit l... Quiescent supply current VOH High output voltage = V VOL Low output voltage = V ON Output drive current N-channel lop Output drive current P-channel /la ma ma l. TYPCAL APPLCATON ~igital equipment in which ultra-low dissipation and/or operation using a battery source are primary itesign requirements. Accurate timing from a crystal oscillator for timing applications such as wall clocks, table clocks, automobile blocks, and digital timing references in any circuit requiring accurately timed outputs. priving miniature synchronous motors, stepping motors, or external bipolar transistors in push-pull fashion. NC 8 220n + M J ! NC 73

165 SMOS N T E G RAT E D G R G U T 74 PRELMNARY DATA LOW QUESCENT POWER DSSPATON WDE SUPPLY VOLTAGE RANGE: 3 to 5V HGH NOSE MMUNTY: 45% of Voo (TYP.) inputs FULLY PROTECTED OUTPUT WAVEFORMS SHAPED for a 25% DUTY CYCLE ~ the M74 (standard temperature range) is 23-stage binary counter constructed with MOS-P channel ~ N-channel enhancement mode devices in a single monolithic chip. The device may be used as ',' ing circuit. t consist of 23 flip-flops, two output buffers, providing push-pull operation one zener iode providing transient protection at - OV, and input inverters for use in a crystal oscillator. The, vice is available in 4-lead dual in-line plastic or ceramic package. s ~, ~BSOLUTE MAXMUM RATNGS* Supply voltage nput voltage (at any pin) Total power dissipation (per package, including zener diode) Storage temperature Operating temperature -0.5 to 5 V Vss';;;; Vi';;;; Voo 200 mw -65 to 50 C -40 to 85 C.'. Stresses above those listed under "Absolute Maximum Ratings' may cause permanent damage to the device. This is ;c a stress rating only and functional operation of the device at these or any other condition above those indicate in " the "Recommended operating conditions" section of this specification is not implied. Exposure to absolute maxi!" mum rating conditions for extended periods may affect device reliability. '~' With respect to Vss (GND) pin, ORDERNG NUMBERS: M74 D for dual in-line ceramic package frit seal M74 B for dual in-line plastic package MECHANCAL DATA Djmensions in mm Dual in-line ceramic package, frit seal Dual in-line plastic package 0 ' ".,, Suoersedes issue dated 4/75 75 /79

166 74 PN CONNECTONS LOGC DAGRAM NC 4 NC 8 OUTPUT 2 3 Yoo Yss OUTPUT 5 NC NC 2 NC Ne OSCLLATOR 0 NYERrER OUTPUT OSCLLAJOA NYERTER NPUT OUTPUT 2 STAGE 9,ov----~ 4 5 ZENER CATHODE 5-00 BLOCK DAGRAM and OUTPUT WAVEFORMS 0.~." PN 3 Yeo PN 3 Yss PN 4 -ZENER i RECOMMENDED OPERATNG CONDTONS Supply voltage: for general applications for oscillator starting nput voltage Operating temperature 3 to 5 6 to 5 Voo to Vss -40 to 85 v V 9/79 76

167 M 74 STATC ELECTRCAL CHARACTERSTCS (over recommended operating conditions) Parameter Test conditions Vo Voo (V (V Values -4O"C 25 C 85 C Unit Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. L Quiescent supply current /la 5 V OH Output high voltage 0= a V VOL Output low a voltage 0=0 0 "b V VNH Noise immunity V VNL Noise immunity V ON Output drive cur rent N-channel ma lop Output drive cur rent P-channel ma V z Zener voltage z=00/la 0.5 V z =0mA.2 H.L nput leakage curt 0 pa DYNAMC ELECTRCAL CHARACTERSTCS (T amb= 25 C. CL = 5 pf. typical temperature coefficient for all V DO values is 0.3%;oC. all input rise and fall time = 20 ns. Values Parameter Test conditions Unit Voo (V Min. Typ. Max. t r tf nput clock rise and fall time /ls 'fel Maximum clock input frequency MHz C nput capacitance Any input 5 pf 77

168 74 TYPCAL APPLCATONS Digital equipment in which ultra-low dissipation and/or operation using a battery source are primary design requirements. Accurate timing from a crystal oscillator for timing applications such as wall clocks, table clocks, automobile clocks, and digital timing references in any circuit requiring accurately timed outputs. Driving miniature synchronous motors, stepping motors, or external bipolar transistors in push-pull fashion. Voo ~ o n 78

169 ~/MOS NTEGRATED CRCUT ~ M730 PRELMNARY DATA ~-STAGE COUNTER ~ LOW QUESCENT POWER DSSPATON WDE SUPPLY VOLTAGE RANGE: 3 to 7V FULLY PROTECTED NPUTS.. NVERTER AVALABLTY FOR CRYSTAL OSCLLATOR TMNG APPLCATON ADJUSTABLE FREQUENCY DVDER N 27 STEPS it TEST OUTPUT AVALABLE MOTOR DRVE STAGE OUTPUT the M730 (standard temperature range is a 23 stage binary counter in COS/MOS technology in a single monolithic chip. An inverter is available for crystal oscillator application in which the function of the trimmer capacitor has been taken over by the variable frequency divider comprised in the C and used to let the correct output frequency. For th is purpose, seven adjustment terminals are provided on the M730: they are used to set the divider ratio to the required value with an accuracy of 0-6. The adjustable frequency divider has been designed in such a way that the maximum output frequency is set when all adjustment terminals are either open-circuit or connected to pin 4.lf one or more adjustment terminals are grounded (taken to pin 3, the output frequency decreases. The by-four-divided oscillator frequency may be checked at a separate test output (pin 8 non-reactive with resp"ct to the oscillator. Based on this check the output frequency and consequently the accuracy of the clock may be adjusted at the ter minal to 7 by means of the variable frequency divider. With an oscillator frequency of MHz, the series-connected push-pull output stage supplies a symmetrical square wave signal with a pulse duty factor of 0.5 and a repetition frequency of 0.5 Hz if the variable frequency divider is set to its medium value. The device is available in 4 lead dual in-line plastic or ceramic package. ABSOLUTE MAXMUM RATNGS'" Vee ** Supply voltage -0.3 to +7 V Output current 60 ma P tot Power dissipation at T amb = 25 C 200 mw Top Operating temperature range -40 to +85 C T stg Storage temperature range -55 to + 25 C, Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condition above those indicate in the "Recommended operating conditions" section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All voltages are with respect to VSS (GND). ORDERNG NUMBERS: M730 B for dual in-line plastic package M730 D for dual in-line ceramic package frit seal 79 /79

170 M730 MECHANCAL DATA (dimensions in mm) Dual in-line ceramic package frit seal ~ -~q 0", 2.5" [:::::! M M 7..,md. ~ lo."m,. Dual in-line plastic package PN CONNECTONS BLOCK DAGRAM and OUTPUT WAVEFORM '00 FREQUENCY AOJJSTMENT NPUTS " ~ 'ss 20 Nt OUTPUT 0 OSC. NPUT 9 Osc., OUTPUT e ~ TEST OUTPUT RECOMMENDED OPERATNG CONDTONS Voo Supply voltage: for general applications 3 to 6.5 for oscillator starting 6 to 6.5 Vi nput voltage VootoVss Output current 40 Top Operating temperature -40 to V V V ma C

171 M730 STATC ELECTRCAL CHARACTERSTCS (over recommended operating conditions) Test cond itions Values Parameter -4O"C 25 C 85 C Unit Vo Vaa (V (V Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. VOH Output high voltage OH= 0 V 2 ~ VOL Output low voltage 0L= 0 V : DN Output drive current N-channel DP Output drive current P-channel ON Current consump. 0= O 2 3 ma ma ma.. At quartz frequency of Hz. DYNAMC ELECTRCAL CHARACTERSTCS (T amb= 25 C, quartz frequency Hz) Test conditions Value. Parameter Vaa (V M730 D type M730 B type Unit Min. Typ. Max. Min. Typ. Max. ft Frequency test output Hz f a Output frequency Hz lifo Range output ~ frequency 2 ± 2 ± 2 ppm adjustment Ro Output resistance RL = 300n n to At the centre position of the variable divider. 8

172 M730 APPLCATON CRCUT 4 20n tv ~o "'-. 2..,..-, 4 M730 -, ~ ~ - --m~ ---l 4T!i482Hz 700}JF ~ 6V,-3335 f 82

173 COS/MOS NTEGRATED CRCUT M73 PRELMNARY DATA,6-STAGE COUNTER LOW QUESCENT POWER DSSPATON WDE SUPPLY VOLTAGE RANGE: 3 to 7V ~ FULLY PROTECTED NPUTS NVERTER AVALABLTY FOR CRYSTAL OSCLLATOR TMNG APPLCATON ADJUSTABLE FREQUENCY DVDER N 27 STEPS TEST OUTPUT AVALABLE MOTOR DRVE STAGE OUTPUT The M73 (standard temperature range) is a 6 stage binary counter in COS/MOS technology in a single monolithic chip. An inverter is available for crystal oscillator application in which the function of the trimmer capacitor has been taken over by the variable frequency divider comprised in the C and used to set the correct output frequency. For this purpose seven adjustment terminals are provided on the M73: they are used to set the divider ratio to the required value with an accuracy of 0-6. The adjustable frequency divider has been designed in such a way that the maximum output frequency is set when all adjustment terminals are either open-circuit or connected to pin 4. f one or more adjustment terminals are grounded (taken to pin 3), the output frequency decreases. The by-four-divided oscillator frequency may be checked at a separate test output (pin 8) non-reactive with respect to the oscillator. With an oscillator frequency of MHz, the series-connected push-pull output stage supplies a symmetrical square wave signal with a pulse duty factor of 0.5 and a repetition frequency of 64 Hz if the variable frequency divider is set to its medium valu:!. The device is available in 4 lead dual in-line plastic or ceramic package. ABSOLUTE MAXMUM RATNGS* Voo -- Supply voltage -0.3 to +7 V Output current 60 ma Ptot Power dissipation at T amb= 25 C 200 mw Top Operating temperature range -40 to +85 C T 5g Storage temperature range -55 to + 25 C Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condition above those indicate in the "Recommended operating conditions" section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All voltages are with respect to V ss (GND l. ORDERNG NUMBERS: M73 B M73 D for dual in-line plastic package for dual in--line ceramic package frit seal 83 79

174 M73 MECHANCAL DATA (dimensions in mm) for dual in-line ceramic package, frit seal 7.4=' --. ~tr~t ~!~~~ 046 -~ 5.24 f::::::: 20-'" D.4 m " for dual in-line plastic package r---- :::::: PN CONNECTONS BLOCK DAGRAM and OUTPUT WAVEFORM lj Vss FREQUENCY AOJJSTMENT NPUTS " NC OUTPUT 0 esc. NPUT 9 OSC. OUTPUT 6 TEST OUTPUT RECOMMENDED OPERATNG CONDTONS Voo Supply voltage: for general applications 3 to 6.5 V for oscillator starting 6 to 6.5 V Vi nput voltage Voo to Vss V Output current 40 rna Top Operating temperature -40 to +85 C 84

175 M73 rstatc ELECTRCAL CHARACTERSTCS (over recommended operating conditions) ~, Test conditions Values Parameter -40"C 25 C 85 C Vo Voo, (V) (V) l'". Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. i i,; VOH Output high voltage 0H= r VOL Output low voltage 0L= ON Output drive current N-channel < lop Output drive current P-channel i! ON Current consump. 0= O' 2 3 Unit V V ma ma ma ~~ At quartz frequency of Hz. )VNAMC ELECTRCAL CHARACTERSTCS (T amb = 25 C, quartz frequency Hz), Test conditions Values, Parameter ~T Frequency test, output ~o V oo (V) M730 M73 B Unit Min. Typ. Max. Min. Typ. Max Hz.~-- -- Output frequency Hz ;llfo Range output i-fo frequency 2,2. 2 ppm \ adjustment ~o Output resistance RL = 300n n t At the centre position of the variable divider. 85

176 M73 APPLCATON CRCUT 20n 4 tv 3 6V 2 4 M Hz 8 S-334/ 86

177 COS/MOS NTEGRATED CRCUTS.738/ /.747 PRELMNARY DATA 7-ST AGE DVDER LOW POWER DSSPATON it LOW OUTPUT MPEDANCE ON BOTH HGH AND LOW STATE WDE SUPPLY VOLTAGE RANGE: 5to 5V HGH NOSE MMUNTY NPUTS FULLY PROTECTED The M738/M740/M74/M747 are integrated circuits constructed in COS/MOS technology for use as frequency dividers in electronic organs. All the devices consist of 7 stages of binary division connected to ~ive five divider blocks for the M74/M747 and four divider blocks for the M738/M740. The information transfer occurs on the positive going edge of the clock, for M740 and M747, and the negative going edge Df the clock for M738/M74, and each output features a symmetrical impedance buffer (300n typo at Vao= 0Vl. They are available in 4 lead dual in-line plastic package. ABSOLUTE MAXMUM RATNGS* Supply voltage nput voltage (at any pin) Total power dissipation (per package) Storage temperature Operating temperature -0.5 to to V DD to to 85 ; Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for l extended periods may affect device reliability. ~. All voltages values are refered to V ss pin voltage. V V mw C C PRDERNG NUMBERS: M 7XX B for dual in-line plastic package CAl DATA Dimensions in mm ~~.,ijlh:~ ~ L '\ ::::::l 20""". 87 /79

178 M738/M740 M74/ M747 CONNECTON DAGRAMS For M74/M747 'ss N 4 our 3 OUT 2 N J 2 ~ OUT J N S ~ QU T 4 N 6 0~ OUT S N 7 9 ~ OUT 6 ""00 B ~ au T 7 For M738/M740 Yoo [ 4 Ne N [ 2 3 N 4 OUT ( 3 2 OUT 7 OUT 2 [ 4 OUT 6 OUT 3 [ 5 0 N J N 2 [ 6 OUT' [ 7 9 OUT ~ e RECOMMENDED OPERATNG CONDTONS Parameter Voo(V Min. Typ. Max. Unit Voo V Top tw Supply voltage nput voltage Operating temperature Width of clock pulse (high or lowl 5 5 V -0.5 Voo+0.5 V C ns 88

179 M738/M740 M74/ M747 JyATC ELECTRCAL CHARACTERSTCS fvpical values are at T amb = 25 C (over recomended operating conditions) Parametar Test conditions va Voo i (V (V Values, C 25 C 85 C Unit Min_ Typ. Max. Min. TYP.j Max. ~~YP. r~:;!lccl Quiescent supply Vj~Vool 5 i current 0 i 0 : /la 5 i 50 50,2000 VOH High level output , 4.95 \/Oitage j ; V. : : 'VOL Low level output : 0.0! 0.05 \/Oitage 0 : 0.0! 0.0, 0.05 V ~ tilli i ma _6 2_5.55 i ~OL Output drive ! current N-channel OH Output drive ~l current P-channel i ma ; 'L nput current Vj~O : /la H, nput current Vj-Voo' 5 /la ~YNAMC ELECTRCAL CHARACTERSTCS (T amb= 25 C) Parameter Test conditions Values Voo(V) Min. Typ. Max. Unit tplh' ~PHL Propagation delay time from inputs to: division stage outputs ns C 2 division L =5pF on all outputs stage outputs see timing diagra", division stage outputs ns ns ~TLH. THL f max Output transition time Maximum toggle frequency CL=5pF on all outputs ns MHz Cross talk immunity level 70 db /C nput capacitance 5 pf Send a frequency of 20 khz to input V charge output VOl with 5 kn and 5 pf. measure the level of the 0 khz frequency present at all outputs. Cross talk level = 20 log VOl (0 khzl Vox (0 khzl With the exception of VOl. the output where the 0kHz signal is greatest is Vox. This operation is repeated for all the inputs. 89

180 .738/ /.747 TMNG DAGRAM For M740/M747 NPUT ONE DVSON STAGE OUT TWO OVSO",N STAGE OUT S-672 For M738/M74 NPUT ONE DVSON STAGE OUT TWO DVSON STAGE OUT THREE DVSON ~ """, STAGE OU T 5-677/ 90

181 SMOS NTEGRATED CRCUT M750 PRELMNARY DATA STAGE COUNTER WTH NTERMEDATE OUTPUT AT THE 6th STAGE LOW QUESCENT POWER DSSPATON, WDE SUPPLY VOLTAGE RANGE: 3 to 7V.FULL Y PROTECTED NPUTS NVERTER AVALABLTY FOR CRYSTAL OSCLLATOR TMNG APPLCATON ADJUSTABLE FREQUENCY DVDER N 27 STEPS TEST OUTPUT AVA LAB LE MOTOR DRVE BRDGE CONFGURATON OUTPUT e M750 is a 23 stage binary counter in COS/MOS technology in a single monolithic chip. An inverter _ available for crystal oscillator application in which the function of the trimmer capacitor has been - en over by the variable frequency divider comprised in the C and used to set the correct output uency. For this purpose seven adjustment terminals are provided on the M750: they are used to set divider ratio to the required value with an accuracy of 0-6. The adjustable frequency divider has n designed in such a way that the maximum output frequency is set when all adjustment terminals e either open-circuit or connected to pin 6. f one or more adjustment terminals are grounded (taken.. pin 4), the output frequency decreases. With an oscillator frequency of 4:9482 MHz the bridge figuration outputs supply two symmetrical square wave signals whose frequency is 0.5 Hz; the pulse.. ty factor is 0.5 and their relative delay is of half period. The intermediate output provides a 64 Hz nal with pulse duty cycle of 50%. The by-four-divided oscillator frequency may be checked at a arate test output (pin 9) non-reactive with respect to the oscillator. The device is available in 6 lead al in-line plastic or ceram ic package. RATNGS* ** Supply voltage -0.3 to +7 V Output current 30 ma tot Power dissipation at T amb = 25 C 200 mw op Operating temperature range -40 to +85 C r stg Storage temperature range -55 to + 25 C Stresses above those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. This is._ a stress rating only and functional operation of the device at these or any other condition above those indicated in J the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for t extended periods may affect device reliability. ~. All voltages values are refered to V ss pin voltage. r! ~ ~. ~DERNG NUMBERS: M750 B for dual in-line plastic package! M750 D for dual in-line ceramic package frit seal F t 9 /79

182 M750 MECHANCAL DATA (dimension in mm) For dual in-line ceramic package, frit seal 7.4max., E2O"'U. i,. r ; ~ ~ For dual in-line plastic package ~ Pool-C [:::::: PN CONNECTONS BLOCK DAGRAM and OUTPUT WAVEFORM NTERMEDATE OUTPUT FREQUENCY AOJUSTMENT NPUTS S " " " " ", '00 Nt '.s OUTAll OUTPUT DSC. NPUT OSC.OUTPUT TEST OUTPUT OO~6 RECOMMENDED OPERATNG CONDTONS Voo Supply voltage: for general applications for oscillator starting nput voltage Output load resistance between pin 2 and 3 Operating temperature 92 3 to to 6.5 Voo to Vss to +85 v V V n c

183 J' M750 rratc ELECTRCAL CHARACTERSTCS (over recommended operating conditions) Test conditions Values Parameter Vo (V) VDD (V) -40 C 25"C 85 C Unit Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. 'OH Output high voltage 0H= 0 V tol Output low 6 0.Q voltage 0L=0 V !DN Output drive pin current N-chan [Dp Output drive pin current P-chan ron Current 0= O' 2 3 rna consumption feat quartz frequency of Hz. ~ '. rna rna ~YNAMC ELECTRCAL CHARACTERSTCS (T amb= 25 C, quartz frequency Hz) " Test conditions Values - Parameter M7500 M7508 Unit VDD (V) Min. Typ. Max. Min. Typ. Max. rr Frequency test Hz output Output frequency Hz '0" tlfo Range output 7;;- 2 ± 2 ± 2 ppm frequency adjustment ~o Total bridge output resistance RL = 300n n t. At the centre position of the variable divider. 93

184 M750 APPLCATON CRCUT 64 Hz OUT 560n 6 +v 2 5 NC A M750 M " "'Lr"

185 f f tos/mos NTEGRATED CRCUT M 75 f ~OUCH TONE GENERATOR f' 2.5 to 5V SUPPLY :. NTERNAL PULL-UP WTH DODE PROTECTON ON ALL NPUTS,. ON CHP CRYSTAL CONTROLLED OSCLLATOR: MHz NTERNAL CAPACTORS FOR THE CRYSTAL OSCLLATOR LOW HARMONC DSTORTON HGH BAND TONES PRE-EMPHASS PRELMNARY DATA The M75 can provide all tone frequency pairs required for the Touch Tone Dialling System. The output :frequencies are obtained from an internal crystal controlled oscillator whose frequency is reduced in two,independent programmable counters. The dividing ratio is controlled by the selected key. The circuit is ~o be used with 4 x 4 matrix keyboard which generates 4 rows and 4 columns input signals in a 2 by 8 p>ntacts closed to ground format. f two or more keys are activated simultaneously no-illegal tones are Rnt on the line; if only one contact per each key is grounded, the selected column or row tone is gener.ated. An internal buffer is provided to achieve a 2 pole low-pass active filter requiring only 4 external,passive components. The filtered output tone must be adequately interfaced to the telephone line. The device can be supplied in plastic or ceramic 6 pin dual in-line package. ABSOLUTE MAXMUM RATNGS* V DO - V :r op T stg P tot Supply voltage nput voltage Operating temperature range Storage temperature range Power dissipation -0.5 to V DD to V DD to to v V C C mw Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condition above those indicate in the "Recommended operating conditions" section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All voltages are refered to V 55 pin voltage. ORDERNG NUMBERS: M75 B M75 D for dual in-line plastic package for dual in-line ceramic package 95 /79

186 M 75 MECHANCAL DATA (dimensions in mm) Dual in-line ceramic package Dual in-line plastic package 0.46 c::::] r, [:::::J PN CONNECTONS esc.nput OSC OUTPuT COLUMNS HGH " FREOUENCY NPUTS 'Z " 'DD " FLTER NPUT FLTER AND TONE OUTPUT ROW LOW FREOuENCY NPUTS MXER OUTPUT DGTAL '55 ~REauENCY OUTPUT 'D BLOCK DAGRAM c. 2 JEVBOARO 5 logc 8 cr... C4 OU"'" 96

187 M 75 ELECTRCAL CHARACTERSTCS (All parameters are 00% tested at 25 C, T amb= 25 C) Parameter DC CHARACTERSTCS.! Voo Voltage supply range C..0. V " Test conditions Values Min. Typ. Max. Unit V VDo Operating supply range VOD~3V ma 'NH nput high current Voo~3V ~ V,H ~ 3V 0..: " 'NL nput low current Voo~3V V,L ~ OV.. ~ /loa /loa " OL Output sink current at digital VDO~ 3V S- frequency output VOL~V See note 200 /loa 0 " 'AC CHARACTERSTCS M/f Maximum output tones frequency At crystal frequency % tolerance fa ~ MHz VLF Nominal output amplitude lower Voo~3V mvpp tones at filter tone output; pin 4 See note 2 VHF Nominal output amplitude high VOD~3V mvpp tones at filter tone output; pin 4 See note 2 Preeamphasis 2 3 db Voe Continuous output at filter tone V od=3v. V output; two tones activated See note 3 Unwanted frequency components f = 3.4 KHz -33 db m f = 50 KHz -80 db m Total harmonic distortion for single frequency 2 % t. Start-up time Voo=3V 3 5 ms See fig. 2 tr Maximum voltage supply rise time Voo~3V 0.5 ms See fig. 2 'Note : Digital frequency output is open drain. 2 : The value of the alternative output component (VLF, VHF) at two different conditions of supply voltages can be related as follows: V OD' VLF'(HF) (mvpp) ~ V LF (HF) (mvpp) -- V oo 3 The value of the continuous output component (V DC) at two different conditions of supply voltages can be related as follows: V OO' VOC' (V) = Voe (V) Voo 97

188 M 75 TEST CRCUT AND START UP TME DEFNTON, {) "2, 2m' 2m' 4.7V FROM.c,';.E"-5''---_- "'CH:Jsv 0, 2m,v 4!"'''' " --+- ;(" ~ ~ L~ 5-))47 APPLCATON CRCUT Rl 697 Hz ( (2 C3 209 lll6 477 C< 6)3 :J,s VOD TO THE ')P~ECH, CRCUT-,- (0,","'0 SPRNG /SET R2 770 Hz " R3 862 Hz R4 96 Hz.' " '0475 " LNE, 5 4, &-?G\ SNGLE PUSH BUTTON 98

189 ~S/MOS NTEGRATED CRCUT 752 ~~ ~ l. PRELMNARY DATA [. r t6 STAGE COUNTER ~ LOW QUESCENT POWER DSSPATON ~ WDE SUPPLY VOLTAGE RANGE: 3 to 7V ~ FULLY PROTECTED NPUTS r- NVERTER AVALABLTY FOR CRYSTAL OSCLLATOR TMNG APPLCATON ADJUSTABLE FREQUENCY DVDER N 27 STEPS ~ TEST OUTPUT AVALABEL ~ MOTOR DRVE BRDGE CONFGURATON OUTPUT 'The M752 (standard temperature range) is a 6 stage binary counter in COS/MOS technology in a single monolithic chip. An inverter is available for crystal oscillator application in which the function of the lrimmer capacitor has been taken over by the variable frequency divider comprised in the C and used to $et the correct output frequency. For this purpose seven adjustment terminals are provided on the M752: ~hey are used to set the divider ratio to the required value with an accuracy of 0-6. With an oscillator.frequency of MHz the bridge configuration outputs supply two symmetrical square wave ~ignals whose frequency is 64 Hz; duty cycle is 50% and their relative delay is of half period. The adjustable frequency divider has been designed in such a way that the maximum output frequency is set when :all adjustment terminals are either open-circuit or connected to pin 6. f one or more adjustment ter )ninals are grounded (taken to pin 4), the output frequency decreases. f all adjustment terminals are grounded, the output frequency is reduced by 242 ppm. The by-four-divided oscillator frequency may be checked at a separate test output (pin 9) non-reactive with respect to the oscillator. Based on this Check the output frequency and consequently the accuracy of the clock may be adjustable at the tertninals by means of the variable frequency divider. The device is available in 6 lead dual in-line plastic or ceramic package. ABSOLUTE MAXMUM RATNGS* V ** DD 2, 3 Ptot 'ToP T 5g Supply voltage Output current Power dissipation at T amb= 25 C Operating temper.ature range Storage temperature range -0.3 to +7 V 30 ma 200 mw -40 to +85 C -55 to + 25 C Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All voltages are referred to Vss pin voltage. ORDERNG NUMBERS: M752 B for dual in-line plastic package M752 D for dual in-line ceramic package, frit seal 99 /79

190 752 MECHANCAL DATA (dimension in mm) For dual in-line ceramic package, frit seal ~ ~ 0.,m~x PO~7-8 For dual in-line plastic package [:::::: PN CONNECTONS BLOCK DAGRAM and OUTPUT WAVEFORM Nt " '00 5 NC l OUTPUT FREQuENCY ADJUSTMENT 5 OUTPUT NPUTS QUARTZ 0 QUARTZ OSC. NPUT NPUT OUTPUT 0 05C.OUTPUT 9 TEST OUTPUT RECOMMENDED OPERATNG CONDTONS Voo Supply voltage: for general applications 3 to 6.5 V V DO for oscillator starting 6 to 6.5 V Vi nput voltage Voo to Vss V R L Output load resistance between pins 2 and 3 Kn Top Operating temperature -40 to +85 C 200

191 752 $TATC ELECTRCAL CHARACTERSTCS (over recommended operating conditions) Parameter Test conditions Vo Voo (V) (V) Values -40 C 25 C 85 C Unit Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. VOH Output high voltage 0H=0 V VOL Output low Q 0.05 voltage OL= 0 V ON Output drive pin current N-channel lop Output drive pin current 2-3 P-channel ON Current consumpt ion At quartz frequency of Hz. 0= O' 2 3 ma ma ma DYNAMC ELECTRCAL CHARACTERSTCS (T amb= 25 C, quartz frequency Hz) i Test conditions Values Parameter Voo (V) M752 0 M7528 Unit Min. Typ. Max. Min. Typ. Max. ft Frequency test Hz output.. fo Output frequency Hz Mo -r.;- Range output 2 ± 2 ± 2 ppm frequency adjustment Ro Total bridge output R L = 300n n resistance At the centre position of the variable divider. 20

192 752 APPLCATON CRCUT 4 M Jl. 6 +V 5 NC V 0 }'F / j 202

193 ~OS/MOS NTEGRATED CRCUT M754 PRELMNARY DATA 23 STAGE COUNTER WTH NTERMEDATE OUTPUT AT THE 6th STAGE LOW QUESCENT POWER DSSPATON 25% OUTPUT PULSE DUTY CYCLE WDESUPPLYVOLTAGERANGE:3to7V FULLY PROTECTED NPUTS NVERTER AVALABLTY FOR CRYSTAL OSCLLATOR TMNG APPLCATON ADJUSTABLE FREQUENCY DVDER N 27 STEPS TEST OUTPUT AVALABLE MOTOR DRVER BRDGE CONFGURATON OUTPUT The M754 (standard temperature range) is a 23 stage binary counter in COS/MOS technology in a single monolithic chip. An inverter is available for crystal oscillator application in which the function of the trimmer capacitor has been taken over by the variable frequency divider comprised in the C and used to set the correct output frequency. For this purpose seven adjustment terminals are provided on the M754; they are used to set the divider ratio to the required value with an accuracy of 0-6. The adjustable frequency divider has been designed in such a way that the maximum output frequency is set when all adjustment terminals are either open-circuit or connected to pin 6.lf one or more adjustment terminals are grounded (taken to pin 4). the output frequency decreases. With an oscillator frequency of MHz the bridge configuration outputs supply two square wave signals whose frequency is 0.5 Hz; the pulse duty factor is 0.25 and their relative delay is of half period. The intermediate output provides a 64 Hz signal with pulse duty cycle of 50%. The by-four-divider oscillator frequency may be checked at a separate test output (pin 9) non-reactive with respect to the oscillator. The device is available in 6 lead dual in-line plastic or ceramic package. ABSOLUTE MAXMUM RATNGS* Voo ** Supply voltage -0.3 to +7 V 2 3 Output current 30 ma Ptot Power dissipation at Tamb = 25 C 200 mw Top Operating temperature range -40 to +85 C T5tg Storage temperature range -55 to + 25 C Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All voltages are referred to V 55 pin voltage. ORDERNG NUMBERS: M754 Bl for dual in-line plastic package M754 Dl for dual in-line ceramic package frit seal 203 /79

194 M754 MECHANCAL DATA (dimension in mm) For dual in-line ceramic package, frit seal For dual in-- ine plastic package t:::::: ~:::::] PN CONNECTONS BLOCK DAGRAM and OUTPUT WAVEFORM NTERMEDATE :lutput " '00 5 NC -AEQUENCV 'OJUS'MENT 5 NPUTS OUTPUT 0() OUTPUT2 OSC. OuT, OSC. NPUT Vss,4 YOO 6 V t NTERMEDATE OUTPUT 0 OSC.DUTPUT 9 5 OUTPUT P"') OUT Pin2 L..- OUT2 RECOMMENDED OPERATNG CONDTONS V DD Supply voltage: for general applications for oscillator starting V i nput voltage RL Output load resistance between pins 2 and 3 Top Operating temperature range to to 6.5 VDD to Vss to +85 V V V n C

195 M754 rstatc ELECTRCAL CHARACTERSTCS (over recommended operating conditions), Test conditions Values Parameter -40" C 25 C 85 C Unit Vo Vee (V (V Min. Typ. Max. Min. Typ. Max. Min. Typ. Max., VOH Output high voltage OH= 0 V VOL Output low voltage OL=O V ON Output drive pin current 2-3 P-channel lop Output drive pin current N-channel ON Current consumption,* At quartz frequency of Hz. 0= O' 2 3 ma ma ma DYNAMC E lectr CAl CHARACTE R STCS (Tamb= 25 C, quartz frequency Hz) Test conditions Values Parameter Vee (V M754 0 M754 B Unit Min. Typ. Max. Min. Typ. Max. ft Frequency test output Hz f 0 Output frequency Hz Mo Range output 2 ± 2 ± 2 ppm ~ frequency adjustment Ro Total bridge output resistance RL = 300n At the centre position of the variable divider n 205

196 754 APPLCATON CRCUT 64 Hz OUT 560fl ~--_.--~==J---{)+v A 5 NC M V ~

197 ~OS/MOS NTEGRATED CRCUT, ~!. :3O CHANNEL REMOTE CONTROL TRANSMTTER LOW POWER DSSPATON N TRANSMSSON r. QUAS-ZERO STAND-BY CURRENT WDE SUPPLY VOLTAGE RANGE NPUTS FULLY PROTECTED.. HGH NOSE MMUNTY NTERLOCK PREVENTS NCORRECT SELECTON,The M 024 is a monolithic integrated circuit intended for remote controlled systems in which 30 dif 'ferent ultrasonic frequencies are used to transmit 30 commands_ -The M 024 comprises an oscillator circuit,a variable and a fixed frequency divider, a decoder and a com :~nd error protection_ The circuit is produced in COS/MOS technology_ n conjunction with the ultrasonic Receiver M 025 a complete remote control system can be realized_ The device is available in a ~6-lead dual in-line plastic package_ ABSOLUTE MAXMUM RATNGS* V ** DO V 0.ptot Tst9 Top Supply voltage nput voltage Output current Total power dissipation Storage temperature Operating temperature -0.5 to 2 V -0.5 to V DO +0.5 V 0 ma 200 mw -65 to 50 DC -25 to 70 DC Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All voltages value are referred to VSS pin voltage. ORDERNG NUMBER: M 024 B5 MECHANCAL DATA Dimensions in mm ~::::::: 207 2/77

198 PN CONNECTONS BLOCK DAGRAM OSCLLATOR N OSCLLATOR OUT N '6 '5 '4 VOO ULTRASONC FREQUENCY OUT VSS N b '3 N N c '2 N k N d " N, N N f '0 N h N (-": ~Hz T S-5)0 TRUTH TABLE (f; = MHz) Channel Number a b c d nputs e f 9 h i k Output Frequency H H H H 2 H H H H 3 H H H H 4 H H H H 5 H H H H 6 H H H H 7 L H H H 8 L H H H 9 H L H H 0 H L H H H H L H 2 H H L H 3 H H H L 4 H H H L 5 L H H H 6 L H H H 7 H L H H 8 H L H H 9 H H L H 20 H H L H 2 H H H L 22 H H H L 23 L H H H 24 L H H H 25 H L H H 26 H L H H 27 H H L H 28 H H L H 29 H H H L 30 H H H L L H H L H H H Hz L H H H H H L 3429 Hz L H L H H H H Hz L H H H H L H Hz L L H H H H H Hz L H H H L H H Hz H L H H H H H Hz H H H H L H H Hz H L H H H H H 3676 Hz H H H H L H H Hz H L H H H H H Hz H H H H L H H Hz H L H H H H H 380 Hz H H H H L H H Hz H H L H H H H Hz H H H H H L H 394 Hz H H L H H H H Hz H H H H H L H Hz H H L H H H H Hz H H H H H L H Hz H H L H H H H Hz H H H H H L H 4 29 Hz H H H L H H H 4565Hz H H H H H H L 492 Hz H H H L H H H Hz H H H H H H L Hz H H H L H H H 4295 Hz H H H H H H L Hz H H H L H H H Hz H H H H H H L Hz 208

199 ~ foescrpton ~The truth table shows the 30 ultrasonic transmission frequencies used in,'-,,, wireless transmission of re ;,note control commands to the receiver. These frequencies are derived frur, the frequency of a quartz '!;:ontrolled oscillator with the aid of a variable frequency divider operating on the blaking principle. ithis is accomplished by blanking out between and 30 out of every 28 pulses of the oscillator fre ~uency ( MHz). The variable divider is preceded by a flip flop which halves the quartz frequency. l.the variable divider is followed by a fixed divider which divides by 50. t reduces the jitter, which is iunavoidable when using the blanking principle, to negligible values. The expression for the ultrasonic ~tput frequency is fj (97 + N) fo= 2800 wherein N is the channel number and fj == MHz (sub-carrier frequency). The space between two -adiacent ultrasonic frequencies is Hz.. The inputs accept a 2 of code: by connecting simultaneously to Vss one of a to e and one of f to,input, a 5 bit word is generated internally and applied to the variable divider. The relative frequency is lhus available at the output..an error protection circuit prevents incorrect operation. Under these conditions the oscillator will not 'Start to operate, and the frequency divider is held in a defined position.. Since consumption under standby conditions is very low, the ultrasonic transmitter need never be switched off. The selected frequency appears at the output when the threshold voltage is exceeded at the two control inputs. A threshold voltage hysteresis ensures that AC voltages which may be superimposed on the input voltage cannot falsify the actuation. RECOMMENDED OPERATNG CONDTONS Supply voltage nput voltage Oscillator frequency Operating temperature 7 to 9 Ot')V oo to 70 v V MHz C STATC ELECTRCAL CHARACTERSTCS(over recommended operating conditions) Parameter Test conditions Values at 25 C Min. TVp Max. CCL Quiescent supply current Voo= 9V all inputs at Voo 2 0 cc Supply current Voo=9V oscillator running - ultrasonic freq. output open, nput current Voo=9V V=O.cVOO 0.0 ron High level output resistance Voo=7V OH= - rna 0.5 (on state) ---_. ron Low level output resistance Voo=7N OL = 0.2 rna.5 3 (on state) V TLH Positive going threshold voltage at Voo=9V 4.5 the inputs a to V THL Negative going threshold voltage at Voo=9V 4. the inputs a to Unit jja rna jja kn kn V V 209

200 TYPCAL APPLCATON '''ool: 47,0 a' a NPUT CRCUT FOR MECHANCAL CONTACTS ~ a' ( 2MJl "DO lmo -.() a 'OOpF -----~----«"S5 NPUT CRCUT FOR TOUCH CONTACTS 0;,.:.00/ 20

201 ~s NTEGRATED CRCUT r L t30-channel REMOTE CONTROL RECEVER ~ te 3 ANALOG OUTPUT SGNALS,e 5 BNARY-CODED NPUT/OUTPUT LNES f. MANS SWTCH OUTPUT ~ MUTNG FUNCTON,- f. NORMALZATON OF ANALOG SGNALS ie STORAGE AVALABLTY OF ANALOG SGNALS M025 [The M 025 is a monolithic integrated circuit intended for a remote-controlled system in which 30 differ,'rent ultrasonic frequencies are used to transmit 30 control commands. The recommended transmitters are 'the M 024 or the M 24. The M 025 measures the frequency of the arriving signal by counting the ; cycles during a fixed measuring time determined by a MHz quartz crystal. All ultrasonic commands : are converted into a coded 5-bit output signal and issued in pulsed form on 5 parallel lines. Nine of the l thirty commands are memorized and used inside the M 025;they can also be selected directly by a 5-bit :word applied to the input/output binary lines (A to ElThe further 2 commands are for free application; tdifferent TV channels are selectable if a decoder is connected to the outputs. Six of the nine memorized <commands give output signals for controlling three analog values, e.g. volume, brightness and colour ijaturation. These signals are continuously delivered in square waveform; the duty cycle can be varied so "determining the level of the analog value. Even when the mains voltage is not available, the latest analog value may be stored with a minimum of power by means of a battery or accumulator. The M 025 is constructed in low-threshold P-channel silicon gate technology and is supplied in a 6-lead dual in-line "plastic package with copper insert. Three different types are available"ca, CB, CAZ, which differ as. specified in the table below. 'Type MANS ON by commands (see truth table for the definition of N).CA CB N 5 to 30 (program selection) CAZ N = N = and N = 5 to 30 (program selection) ABSOLUTE MAXMUM RATNGS* Voo, Vooi* V 0 Ptot Tstg Top Supply voltages nput voltage Output current (pins 2, 3, 4, 6,7,8,9,, 2) Total package power dissipation Storage temperature Operating temperature -20 to to to to 70 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All voltages values are refered to Vss pin voltage. ORDERNG NUMBERS: M 025 B5 CA M 025 B5 CB M 025 B5 CAZ Supersedes issue dated 2/78 2 /79 V V ma W C C

202 Ml025 MECHANCAL DATA (dimensions in mm) ~ 838 PN CONNECTONS v 5S S '00 ""OLV~AE OUT-VL S CLOCK N BRGHTNESS OUT -BR :) COLOUR SATURATON our -c 5 " ULTRASONC FREQUENCV N 3 NOTE 2 5 lorage SUPPLY "DOl 5 2 NOUT " MANS SWTCH OUT (N) 6 NOUT B NOUl 0 "'OTE NOUT 0 N/OUT C NOTE : THS PN MUST BE LEFT OPEN (-<. CONNECTED TO V55 NOTE 2' THS PN MUST BE LEFT OPEN BLOCK DAGRAM CLOCK NPuT ULTRASONC FREaUENCY NPUT o-----t--~t..;;~~::._.j OUT DRECT NPUT/OUTPUT LNES 22

203 Ml025 truth TABLE (Clock frequency, f = MHz),.C f" ~;. jc f,;. Ultrasonic N Command Frequency Code E A B C D " c j CA, CAZ types: MANS ON/OFF" f Hz H L H H H ~ CB type: MAN5 OFF" ~ Hz MUTNG ON/OFF L L H H H Hz Colour saturation (C5+ H H L H H, c B4 Hz Normalisation ' L H L H H Hz Colour saturation C5 - H L L H H, Hz 5 L L L H H Hz Brightness BR+ H H H L H, Hz 52 L H H L H, Hz Brightness (BR - H L H L H t k Hz 53 L L H L H r Hz Volume (VL +; MUTNG OFF H H L L H ~ ~;, Hz 54 L H L L H Hz Volume VL - H L L L H Hz 55 L L L L H C" Hz Program H H H H L " Hz Program 2 L H H H L Hz Program 3 H L H H L Hz Program 4 L L H H L Hz Program 5 H H L H L " Hz Program 6 L H L H L ~., Hz Program 7 H L L H L CA, CB types: Hz Program 8 L L L H L all these Hz Program 9! H H H L L commands Hz Program 0 L H H L L act also as Hz Program H L H L L Hz Program 2 MAN5 ON" L L H L L Hz Program 3 H H L L L Hz Program 4 L H L L L Hz Program 5 H L L L L, Hz Program 6 L L L L L _ S to S5 are additional commands. * The Normalisation command sets the colour saturation to a pulse duty cycle of 6/3 and the brightness to a pulse duty cycle of 8/3;this command has no effect on volume, unless MUTNG has, been inserted: in this case the volume is restored, without changing the duty cycle. r ** f MUTNG has been commanded, each MANS OFF or MANS ON command also acts on MUT, NG to restore the previous volume level. ECOMMENDED OPERATNG CONDTONS ~OD Supply voltage -8 ± V f 00 Storage supply voltage: - D/A signal storing -0 to Voo V - No storing 0 V ~ nput voltage o to Voo V ~l nput clock frequency MHz rop Operating temperature -25 to 70 C r Supply voltage rise time max 00 ms ~ Output current (pins ) max 2.5 rna 23

204 M025 STATC ELECTRCAL CHARACTERSTCS (Over recommended operating conditions) (Typical values are at T arnb = 25 C) Parameter 00 Supply current 00 Storage supply current ron ron Output resistance (on state) pins 2, 3, 4, 6 Output resistance (on state) pins 7, 8, 9,,2 Test conditions and notes Values Min. Typ. Max. Voo'" -9V.-._ V OOl= -9V VOO= -8V, RL = 2 kh -_. f- Voo= -8V, R L =3.9kH 5 Unit rna ma kfl kfl DRECT NPUTS (7,8,9,, 2,6) V H V L High level input voltage Low level input voltage C LOCK NPUT (pin 5) - VSS VOO -4 V V V PP nput peak to peak voltage swing (sinusoidal) Signal applied without DC voltage ULTRASONC FREQUENCY NPUT (pin 4) nput peak to peak voltage swing Signal applied without DC voltage DYNAMC ELECTRCAL CHARACTERSTCS (Clock frequency f = MHz) Parameter Min. Typ. Max. tl Ultrasonic input acceptance time (except MANS and MUTNG 5.5 commands) t2 Ultrasonic input acceptance time (for MANS and MUTNG commands) t3 Direct inputs acceptance time (except MANS and MUTNG 69.3 commands) t4 Direct inputs acceptance time (for MANS and MUTNG commands) t5 Output activation delay (including acceptance time) for all commands 5.5 except MANS and MUTNG t6 Output activation delay (including acceptance time) for MANS and MUTNG commands t7 Analog-output step to step response time 84.8 t8 MANS OFF to ON acceptance time plus activation time from MANS 0 input-output f Analog-output frequency 8,9 D Analog-output frequency duty-cycle /3 30/3 Unit ms ms ms ms ms ms ms JS khz - 24

205 .025 ~. nescr PTON, ~he function of the M 025 is explained by reference to the various pins as follows: ~ fin - Vss ' ~ he substrate of the integrated circuit is connected to this pin. t is the reference point for all voltage arameters of the device, and is to be connected to the highest potential of the supply voltage. r xamples: Vss= OV V DD = -8V or Vss= +8V V DD = OV ~; ~in 5 - V D Dl storage supply voltage [f the last-stored D/A information is to be preserved when the mains plug has been disconnected, -0V iat least should be fed to pin 5. The current consumption of the memory is typically 0.2 rna. The voltage!vool should be applied before!v OD! falls below 6V. f the storing function is not required, VDDl has ~o be connected to V ss: in this case, when V DD is applied, the analog control signals are set at the!hormalized position. '/ ljtin 4 - Ultrasonic frequency input ;The amplified ultrasonic signals of 500 mv peak to peak at minimum are applied to this pin via a capaci i'fur to remove DC voltage. The input waveform must be present for more then 5.5 ms to allow the tcommand to be accepted. Exceptions are the MANS and MUTNG commands which have a ms :acceptance time. nternal control logic suppresses input frequencies greater than 55.4 khz and lower r'than 27.7 khz. Due to the recognition system, the ultrasonic transmission frequency of 33.9 khz may ~fluctuate by ± 0.5 % and the frequency of 44.0 khz by ± 0.39% without causing errors. ~. :'in 5 - Clock input ~<The clock input has to be connected via a capacitor to a MHz quartz controlled oscillator, whose "output peak to peak voltage has to be comprised between 4 and 8V.,Pins O/A outputs The outputs CS (colour saturation). B R (brightness) and V L (volume) are the drain of the output tran. sistors. A square wave output vo tage is produced when resistors are inserted between the outputs and :V OD ' The frequency of these square waves is 8.93 khz. The pulse duty cycle is variable in 30 steps between /3 and 30/3(see fig. ). 5.5 ms after the onset of an ultrasonic or direct binary command,,the pulse duty cycle is advanced by one step. n the case of a con :tinuous commanu, further advances follow at intervals of 84.8 ms :until the final value is reached. The time needed to make the entire variation is seconds. When the supply voltage is applied, with V OD = 0, the D/A outputs are normalized with the following pulse,duty cycles: output colour saturation = 6/3; output brightness =.8/3; output volume = 0/3; if V DDl pin has been maintained at :.its correct voltage, the last stored information is preserved. The com 'mand N = 2 switches on or off, the VL output transistor, with a "delay time of ms acting as a sound ON/OFF-switch. The com. mand N = 4 (normalisation) sets outputs CS and BR to a pulse duty ;cycle of 6/3 and 8/3, but this command has no effect on the.output VL, unless MUTNG has been previously commanded. n this -case the command N=4restores the volume. f the MUTNG has been commanded, the volume can also be restored with the command 'VL +, provided that the circuit is not in the stand-by position. n any case the MUTNG command is cancelled by a MANS ON or OFF command. 25 Fig. 'S5 i:toe~:~e"._----l J logc '00 J PNS '.J., ~. "'.' EXTERNAL RESSTM

206 Ml025 DESCRPTON (continued) Pin 6 - MANS ON/OFF output/input For the purpose of switching the TV set ON or OFF ultrasonically, the input signal must be present at least for ms. Thereafter the mains flip flop toggles, controlling an open drain transistor (see fig. 2). After power supply is applied, the mains flip flop is set independently of V DDl so that the output transistor is off. When the output transistor is off, the 0/ A-converters are locked, i.e. the output signals at pins 2,3 and 4 cannot be varied. With M 025 CA type, switching ON Fig.2 can be obtained either by selecting one of the 6 stations or by the FRO" THE power ON/OFF command. With M 025 CB type,switching ON can ~::!:"NO'p" be achieved only by using one of the 6 station control commands; with M 025 CAZ type,only by the Power ON/OFF command. n all TO THE types,switching ON can also be obtained connecting pin 6 to Vss for ~~'c;~~n'" at least 0 "s and switching OFF is obtained only by the command N = (see truth table). Pins Direct input/output lines ----., t----l OUTPUT TRANSSTOR t PN 6 ~ MANS ON/O'" 5 th' These pins serve as inputs for commands on the TV set and, also as outputs for ultrasonic transmitted' commands. Fig. 3 shows the input/output stage of one line of the circuit. The commands may be introduced directly in the form of a 5-bit word applied to the nput/output Fig.3 lines A, B, C, 0 and E. An input signal is only recognized as valid if it exceeds the threshold voltage at least once in each of three successive 23. ms periods, for at least 0 "s. When this happens, an output pulse of 23. ms duration is generated after a processing time of 46.2 ms. (Total delay time 5.5 ms). n the case of MANS ON/ OUT OFF and MUTNG input commands the acceptance time is OuTPuT ms; the output pulse will appear with a delay of 69.3 ms after the HA"lSSTQR acceptance time (total delay time ms). Evidently the output signals act on the inputs again, but this does not cause interferences because the inputs are locked while an output signal is available. f commands are issued either from the remote control or locally to the television set, the local command will always override the remote command. Fig. 4-Typical output charac- 's teristics of the open source {,' i~ --0;" transistoratpins7,8,9,,2 0 -t_ '"., (:Voo ".0 '.J~';u".""" YSS-\tlO,' t09v.--:-t t -::: + f S 26

207 S/MOS NTEGRATED CRCUT M 24 -CHANNEL REMOTE CONTROL TRANSMTTER FEW EXTERNAL COMPONENTS NTERLOCK PREVENTS NCORRECT SELECTON QUAS-ZERO STAND-BY CURRENT WDE SUPPLY VOLTAGE RANGE NPUTS FULLY PROTECTED e M 24 is a monolithic integrated circuit intended for remote controlled systems in which 30 dif. rent ultrasonic frequencies are used to transmit 30 commands. e M 24 comprises on oscillator circuit which does not require exter.nal components except the artz. Further it comprises a fixed and a variable frequency divider, a decoder and a command error fotection- All the command inputs are pulled-up to V DO by integrated resistors, to reduce the number.. external components. Due to the relative low input impedances, the M 24 is not suited for touch.. ntacts. The circuit is produced in COS/MOS technology. n conjunction with the ultrasonic receivers or M 30, a complete remote control system can be realized. The device is available in a 6-lead al in-line plastic package. MsOLUTE MAXMUM RATNGS t, DO ** ~.'0 ~tot!t 59 Supply voltage -0.5 to 2 V nput voltage Output current Total power dissipation -0.5 to V DO V ma mw Storage temperature -65 to 50 top Operating temperature o to 70!"'$tresses above those listed under "Absolute Maximum Ratmgs" may cause permanent damage to the device. This is ;-' a stress rating only and functional operation of the device at these or any other condition above those indicate in ~ the "Recommended operating conditions" section of this specification is not implied. Exposure to absolute maxi : mum rating conditions for extended periods may affect device reliability. All voltages are with respect to Vss (GND). ORDERNG NUMBER: M 024 B ~MECHANCAL DATA Dimensions in mm ~::::::: 27 79

208 M 24 PN CONNECTONS OSCLLATOR, N OSCLLATOR OUT N '6 5 4 Voo ULTRASONC FREQUENCY OUT VSS BLOCK DAGRAM N b 3 N N c N d 2 N, N, N 0 N h N t N g S-SJO TRUTH TABLE (f; = MHz) Channel Number a b c d nputs e f 9 h i k Output Frequency H H H H 2 H H H H 3 H H H H 4 H H H H 5 H H H H 6 H H H H 7 L H H H 8 L H H H 9 H L H H 0 H L H H H H L H 2 H H L H 3 H H H L 4 H H H L 5 L H H H 6 L H H H 7 H L H H 8 H L H H 9 H H L H 20 H H L H 2 H H H L 22 H H H L 23 L H H H 24 L H H H 25 H L H H 26 H L H H 27 H H L H 28 H H L H 29 H H H L 30 H H H L L H H L H H H Hz L H H H H H L 3429 Hz L H L H H H H Hz L H H H H L H Hz L L H H H H H Hz L H H H L H H Hz H L H H H H H Hz H H H H L H H Hz H L H H H H H 3676Hz H H H H L H H Hz H L H H H H H Hz H H H H L H H Hz H L H H H H H 38 0 Hz H H H H L H H Hz H H L H H H H Hz H H H H H L H 394 Hz H H L H H H H Hz H H H H H L H Hz H H L H H H H 4080 Hz H H H H H L H Hz H H L H H H H Hz H H H H H L H 429 Hz H H H L H H H 4565Hz H H H H H H L 492Hz H H H L H H H Hz H H H H H H L Hz H H H L H H H 4295 Hz H H H H H H L Hz H H H L H H H Hz H H H H H H L Hz 28

209 M 24 he truth table shows the 30 ultrasonic transmission frequencies used in the wireless transmission of reo 'ate control commands to the receiver. These frequencies are derived from the frequency of a quartz, ntrolled oscillator with the aid of a variable frequency divider operating on the blanking principle. EiS is accomplished by blanking out between to 30 out of every 28 pulses of the oscillator fre ency ( MHz) divided by 2.. e variable divider is followed by a fixed divider which divides by 50. t reduces the jitter, which 'is "'avoidable when using the blanking principle, to negligible values. The expression for the ultrasonic putput frequency is fi (97 + N) f f 0 = &merein N is the channel number and fi = MHz (sub-carrier frequency). The space between two.acent ultrasonic frequencies is Hz. ~ e inputs accept a 2 of code: by connecting simultaneously to Vss one of a to e and one of f to,', ut, a 5 bit word is generated internally and applied to the variable divider. The relative frequency is thus available at the output. ttn error protection circuit prevents incorrect operation. Under these conditions the oscillator will not &tart to operate, and the frequency divider is held in a defined position. tince consumption under standby conditions is very low, the ultrasonic transmitter need never be twitched off. The selected frequency appears at the output when the threshold voltage is exceeded at the two control inputs. RECOMMENDED OPERATNG CONDTONS ~DD fil fp rs Top Supply voltage nput voltage Parallel resonance frequency of the quartz at C L = 0 pf Series resistance of the quartz at CL= 0 pf Operating temperature 6 to 9 o to Voo <200 o to 70 v V MHz n C STATC ELECTRCAL CHARACTERSTCS (over recommended operating conditions) Typical values are at T amb= 25 C, unless otherwise specified. Parameter Test conditions Values Min. Typ. Max. DOL Quiescent supply current All nputs at VOO 2 0 DO Supply current Voo = 9 V oscillator running - ultrasonic freq. output open nput current V= a -20 fon High level output resistance OH= - ma 0.5 (on state 'on Low level output resistance OL= 0.2 ma.5 3 on "ate V TH Threshold voltayc of the control 4. inputs Unit JJ.A ma JJ.A kn kh V 29

210 M 24 TYPCAL APPLCATON 9v 6 'n~ 4433 C-] MHz L a OGNO / -----_._-- MATRX Y i 220

211 NTEGRATED CRCUT M 30 HANNEL REMOTE CONTROL RECEVER PROGRAM MEMORY OUTPUTS NTEGRATED CLOCK OSCLLATOR SEQUENTAL PROGRAM CHANGE COMMAND 5 BNARY CODED NPUT/OUTPUT LNES M 30 is a monolithic integrated circuit intended for a remote-controlled system in which 30 difultrasonic frequencies are used to transmit 30 control commands. Both the M 024 and the M 24 used as transmitter. The M 30 measures the frequency of the incoming signal by counting the during a fixed measuring time determined by a MHz quartz crystal. The accepted ultrasonic... 'mn"".rl. are converted into a coded signal and issued on 5 input/output lines (A to E). The 30 combe given not only ultrasonically, but also by applying a 5-bit word to the above mentioned additional "sequential program change" command is available only on the receiver. Signals to three analog values, e.g. volume, brightness and colour saturation are internally stored by the and continuously deliv~red io the shape of square wave voltages. The duty cycle of these signals nes the level of the analog value. An output is provided to drive a relay which switches the TV or OFF. The program output lines are provided to drive all the circuits which need a 4-bit binary such as the H 770//2/3 quad analog switches, or the M 93 electronic program memory. The 30 is constructed in a low threshold P-channel silicon gate technology and is supplied in an 8-lead,,,'- m--'r." plastic package. ABSOLUTE MAXMUM RATNGS* ~D[j* Supply voltage -20 to 0.3 V nput voltage -20 to 0.3 V io Output current (pins 2 to 4 and 6) 5 ma Ptot Total power dissipation (per package) 800 mw rst9 Storage temperature -65 to 50 C rop Operating temperature o to 70 C Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All voltages values are refered to V ss pin voltage. ORDERNG NUMBER: M 308,..eCHANCAL DATA Dimensions in mm R w 22 /79

212 M 30 PN CONNECTONS Vss 8 VOO BRGHTNE 55 OUT 2 7 QUAFHZ NPUT CQOUR SAT. OUT ] 6 T OUTPUT VOLlJME OUT S ULTRASONC NPUT MANS ON/OFF 4 PROGRAM OUT PB PROGRAM OU] PC 6 ] PROGRAM OUT PA PROGRAM OUT PO 7 2 E NPUT OUTPUT o NPUT OUTPUT 8 A NPl]T OUTPUT C NPUT OUTPUT 0 B NPUT OUTPUT TRUTH TABLES Table (Clock frequency = MHz) Channel no. Ultrasonic frequency (Hzl Command E A Code B C o Sequential progr. change - Mains ON Mains OFF Muting ON/OFF Colour saturation + Normalisation Colour saturation - Sl Brightness + S2 Brightness - S3 Volume + (Muting OFF S4 (Fine tuning- Volume - (Muting OFF S5 (Fine tuning + :~~~~:~ ~ \/ Program 4 Program 5 Program 6 Program 7 Program 8 all these commands act Program 9 \ also as Mains ON Program 0 Program Program 2 Program 3 Program 4 Program 5 Program 6 : L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L L H H L L H H L L H H L L H H L L H H L L H H L L H H L L H H H L L L L H H H H L L L L H H H H L L L L H H H H L L L L H H H H H H H L L L L L L L L H H H H H H H H L L L L L L L L H H H H H H H H H H H H H H H L L L L L L L L L L L L L L L L Note: Sl to S3 are additional commands. 222

213 :able 2: Output code at pins 6, 7, 3, 4 Program no. PA PB PC PO L L L L 2 H L L L 3 L H L L 4 H H L L 5 L L H L 6 H L H L 7 L H H L 8 H H H L 9 L L L H 0 H L L H L H L H 2 H H L H 3 L L H H 4 H L H H 5 L H H H 6 H H H H ~. ~ ~ ~COMMENDED OPERATNG CONDTONS 0 Supply voltage -8 ± nput voltage o to Voo b Output current (pins 2 to 4 and 6) max 2.5 nput clock frequency l Operating temperature ~ o to 70 V V rna MHz C rratc ELECTRCAL CHARACTERSTCS (over recommended operating conditions) rrvpical values are at T amb= 25 C) Parameter Test conditions Values Min. Typ. Max. Unit :00 Supply currerl't Vee=-9V -25 V H High level input voltage - Vss pins 'YL Low level input voltage Vee -4 ma V V :,vpp Ultrasonic input peak to peak The signal must be applied voltage (pin 5) without D.C. voltage 500 Vee mv ~OH High level output voltage OH=- ma pins 2 to VsS-0.6 V, 223

214 M 30 DYNAMC ELECTRCAL CHARACTERSTCS (Clock frequency = MHz) Parameter Min. Typ. Max. Unit' f Analog output frequency 7.6 khz D Analog output duty cycle /63 62/63 t Mains ON/OFF command delay time ms t2 Program stepping delay time with continuous command ms - t3 Analog output delay time with continuous command 38.6 ms tw Pulse width at pin 6 with command 2 (FT-) 2.6 ijs tw2 Pulse width at pin 6 with command 4 (FT +) 23. ms DESCRPTON The function of the M 30 is explained with reference to the various pins as follows: Pin- v ss... The substrate of the integrated circuit is connected to this pin. t is the reference point for all the voltagl parameters of the device and has to be connected to the highest potential of the supply voltage. c; Examples: Vss= OV Voo= -8V or Vss= +8V Voo= OV Pin 8 - Voo Negative pole of the supply voltage. Pins 2, 3, 4 - D/A Outputs These outputs are designed to control brightness, colour saturation and volume respectively. A square: wave is produced when resistors are inserted between the outputs and V DO (see fig. ). The frequency 0 the square wave is about 7.5 khz, the duty cycle is variable between /63 to 62/63. The information ~ contained in the pulse duty cycle and D.C. voltages are obtained by integrating the output signals wit RC networks. Approximately 5 ms after the switch-on ot an. J. j ultrasonic command, the pulse duty cycle is advanced by one Fig..~ step. n the case of a continuous signal, further steps follow at VFSRSOU THE J :,< intervals of 38.5 ms until the final value is reached. The time ~ needed to traverse the entire range of variation is 8.5 seconds. NTEqNAL ~._----jl ' During the pulse duration, the open drain output transistor is LOGC turned on and has a voltage drop of max 0.6V at ma output PNS 2-3-~. current. When the supply is switched on the analog outputs are normalized to the pulse duty cycle of 32/63. A Mute command EXTERN.~ switches the open drain output transistor at pin 4 OFF and ON LOAD : after a delay of 0,7 sec. The sound is also restored after a normal voo --, delay when one of the commands "Volume +" or "Volume -" is given. The sound is unmuted when the TV set is switched ON. 224 VSS Voo VSS Voo n n 63 OU'f~ -ll--...jl- DUTY Cyc~,r--r-62/6J OUT~ u U DUTY cyell!)-289 ij

215 Ml30 SCRPTON (continued) 5 - Mains switch output is output is provided to control the ON/OFF switching of. TV set via a transistor and a relay. When the supply voltage plied to the M 30 the output transistor is automatically ed off. n this "stand-by" condition, the analog outcannot be changed; this lasts until a mains ON command given in one of the following modes: by any of the 6 program commands for 0.7 sec. ~ by the command "sequential program change" (available ; only on direct inputs) for 0.7 sec. /by connecting the pin 5 to Vss for at least 0 Jls. ~. e TV set can only be switched off by a "Mains OFF" mand. l ~ Fig.2 FROM THE NTERf>oAL Fl'PFL(jP TO TE NTERNAl LOGC ' OUTPUT --. TRANSSTOR p,,," 5 :. MANS ONrOFF 58,9,0,,2 - Direct inputs/outputs ese pins are provided as inputs for commands on the TV set and also as outputs for ultrasonic trans "tted commands. The command may be introduced directly in the form of a 5 bit word applied to the ut/output lines A-B-C-D-E, according to the code indicated in the truth table. An input signal is ognized as valid after an acceptance time of 69.3 ms (for Mains ON/OFF and Muting ON 0.6 sec.), er which a further processing period of 46.2 ms occurs before the 23. ms output signal appears. ring the 23. ms pulse the output transistor shown in fig. 3 is conducting. The same pulse will appear "en the circuit is receiving coded commands from the ultrasonic input Erding to the truth table. Although the output signals are felt on the Fig. 3 NPUT PROTECTON V. t again this does not cause interference because the inputs are.' ed while an output signal is available. f commands are issued either rqe~--tasonically or normally to the television set, the manual command ~ always override the ultrasonic command. Concerning the "touch" PN58 '0" j)mmand, this type of operation is possible due to the very high imlildance of the MOS input. The only major point of consideration is in OUTPUT TRANS5 TOR ~ choice of diode matrix; this must have such a high reverse leakage,...,rent in even the worst conditions that an incorrect command tuation is avoided. OR JJ.J NPUT it, HANSSfOR -~ '00 ~r:'s 6, 7,3,4 - Program outputs PA-PB-PC-PD the information of the selected program is statically available in a binary coded form. The code is shown ~ table 2. TV programs are chosen either selectively (by the commands "Program.. Program 6") or!equentially upwards on the command "Sequential program change". f the "Sequential program change" Ommand is given continuously, the first change of program takes place after 5 ms and every further ~ange at 0.7 sec intervals. After program 6 has been reached it is followed again by program. When the supply voltage is applied to the M 30, the program outputs are automatically set to program. f he TV set is switched on by the command "Sequential program change" this command is made inef ~tive until it is released.!'he output configurations is similar to that shown in fig. 2. "" external load of min 47 Kn is to be connected to these outputs even if they are not used. 225

216 Ml30 DESCRPTON (continued) Pin 5 - Ultrasonic input Ultrasonic signals of at least 500 mv peak to peak have to be applied to this input via a capacitor. The integrated input amplifier is automatically biased and has an input resistance exceeding Mohm. The first ultrasonic pulses arriving at pin 5 are followed by a preparation period of 23. ms. After a measuring time and a delay time of 46.2 ms a pulse of 23. ms will appear on the input/output lines according to truth table. f a continuous signal is present at the ultrasonic input, the interval between the output pulses amounts to 38.5 ms. Pin 6 - T output When commands S4 or S5 are given, in addition to the binary coded output signals at the /O lines, a further signal in the shape of a pulse is available at this pin. The pulse which has a duration of 2.6 ls in the case of command S4 and of 23. ms in the case of command S5, is used for remote control of the fine tuning via the SGS-ATES M 93 Electronic Program Memory as shown in fig. 4. Fig.4.l8V 8V.2V Pin 7 - Quartz terminal A MHz quartz crystal has to be connected between this pin and Vss. A resistor of 5.6 Mohm has to be connected between the input and V DD to bias the integrated oscillator. The accuracy of the' frequency determines the evaluation accuracy of the ultrasonic receiver.. 226

217 NTEGRATED CRCUTS M 202A M 202AL - BT STATC RANDOM ACCESS MEMORY POWER SUPPLY V cc= 5V TTL COMPATBLE ALL NPUTS AND OUTPUTS THREE-STATE OUTPUT NPUTS PROTECTED AGANST STATC CHARGE ORGANZATON 024 x BT N 6 PN STD PACKAGE TYPE STANDBY PWR OPERATNG PW ACCESS TME (mw) (mw) (n5) M202AL M202AL M202AL M 202 A M 202 A M 202 A M 202 A ~he M 202A is a high speed 024 word by static N-channel silicon-gate MOS RAM. The device is!fully static and therefore does not require clocks or refreshing to operate. The data is read out non de Jtructively and has the same polarity as the input data. ~ low standby power version (M 202 AL) is also available. t has all the same operating characteristics!6f the M 202A with the added feature of 35 mw maximum power dissipation in standby and 74 mw tin operations. The device is available in 6 lead dual in-line.ceramic package, metal-seal or frit-seal and!plastic package. ~ fabsolute MAXMUM RATNGS nput voltage (at any pi n) Total power dissipation Storage temperature Operating temperature under bias ~. All voltage are referred to GND pin voltage -0.5 to 7-65 to 50 o to 70 V W C C ORDERNG NUMBERS: M 202A - B for dual-in-line plastic package M 202A - D for dual-in-line ceramic package, metal-seal M 2 02A - F for dual-in-line ceramic package, frit-seal M 2 02AL - B for dual-in-line plastic package M 2 02AL - 0 for dual-in-line ceramic package, metal-seal M 202AL - F for dual-in-line ceramic package, frit-seal 227 /79

218 M 202A M 2J2AL MECHANCAL DATA (dimensions in mm) Dual in-line ceramic package frit-seal for M2 02A/AL-F ~b~~: 046J.. _.-2~"'l 'n.~ 20""4' ~::::::: : Dual in-line plastic package for M 202A/AL-B 7'-' f4. l-_ ~l8_---,.,' e::::::: i, Dual in-line ceramic packagl metal-seal for M 2 02A/AL-O' CONNECTON DAGRAM LOGC DAGRAM A6 6 A7 A5 5 A8 R/W 4 A9 A 3 CE A2 2 DATA OUT A3 DATA N A4 0 Vcc AD GND S AD - A --- A2 0, A3 -- A4 -- AS -- A6 - A7 DO A8 - A' R/W CE r S ] 6~ PN NAMES TRUTH TABLE DN AO-Ag R/W T DOUT Vee DATA NPUT ADDRESS NPUTS READ/WRTE NPUT CHP ENABLE DATA OUTPUT POWER (+5V) CE R/W DN DOUT MODE H X X HGH Z NOT SELECTED L L L L WRTE "0" L L H H WRTE"" L H X DOUT READ 228

219 2J2A M2J2A. \ ~LOCK DAGRAM i, AODRES50 ~-- ADDRESS, ~ ADDRESS 2 ~~ ROW SELECTOR CEll ARRAY 32 ROWS 32 COLUMNS ADDRESS ~~, ADDRESS 4 7 READ WRTE DATA NPUT NPUT " CO~~~AOl COLUMN /0 CRCUTS COLUMN SELECTOR DATA OUTPUT CHP ENA8LE S.O'lR8 ADORESSS ADDRESS, ADORE SSg ADDRESSS ADDRESS a k ",ATC ELECTRCAL CHARACTERSTCS ltherwise specified) (Vee= 4.75 to 5.25V, T amb = 0 to 70 0 e unless ~: M 202 A, f M 202 AL M 202 A -2 Test M 202A -4 M 202 A-6 Parametar M 202 AL-2 conditiom M 202 AL-4 Min. Typ.* Max. Min. Typ~ Max. Min. Typ.* Max., V H nput high voltage 2 Vee 2 Vee 2.2 Vee V VL nput low voltage -0, V ~OH Output high voltage OH= -00 jla V ~OL Output low voltage OL-2. ma V!i. nput load current V,- 0 to 5.25V jla OH Output leakage CE- 2V. current VO=VOH OL Output leakage CE= 2V, current Vo=O.4V Unit jla jla cc Supply current V,= 5.25V ma Tamb= OOC \ Data out open ~: TYPical values for T amb= 25 C and nominal supply voltage.... The maximum cc value is 55 ma for the M 2 02A and M 202A-4,and 33 ma for the M 202ALand M 202AL

220 M 202A M 202AL DYNAMC ELECTRCAL CHARACTERSTCS otherwise specified) (Tamb= 0 to 70 g e, Vee= 5V ± 5% unlest Parameter Test M 202 A -2 M202A- M 202A -4 M 202 AL-2 M 202 AL M 202 AL-4 M 202 A-6 condition Min. Max. Min. Max. Min. Max. Min. Max. Unit Read Cycle trc Read cycle ns to Access time ns te CE to output time ns tr, tf= 0 ns toh Previous read data Load = TTL ns valid with respect gate and to address CL= 00 pf toh2 Previous read data ns valid with respect to chip enable ~rite Cycle twe write cycle ns taw Address to with ns setup time twp Write pulse width tr, tf= 0 ns ns Load = TTL twr write recovery gate and ns time CL=00pF ts Data setup time ns th Data hold time ns tew Ch ip enable to ns write setup time CAPACTANCE (T omb = 25 e, f= MHz) Values Parameter Test conditions Unit, Min. Typ. Max. C nput capacitance V =OV 3 5 pf / Co Output capacitance Vo = OV 7 0 pf ~

221 \ M 202A M 202Al STANDBY CHARACTERSTCS (Tamb= O C to 70 C) M 202 AL-4 Parameter Test conditions M 202 AL Min. Typ. Max. M 202 AL-2 Min. Typ. Max. Unit Vpo V CC in standby.5 VCES" CE bias in standby 2V'" VPO'" VCC Max. 2.5V";; VPO< 2V VPO pol Standby current All inputs - VpOl -.5V 5 23 p02 Standby current All inputs = Vp02-2V tcp Chip deselect to 0 stand by time tr Standby recovery trc time.5 V 2 V VPO V ma ma 0 ns Typical values are for T amb= 25 C. _ Consider the test conditions as shown: if the standby voltage (V po) is between 5.25V (V Cc max) and 2V, then CE must be held at 2V Min. (V,H). f the standby voltage is than 2V but greater than.5v (V po mini, then ~and standby voltage must be at least the same value or, if they are different, CE must be the more positive of the two. "'tr = trc (READ CYCLE TME). trc ns STANDBY WAVEFORMS STANDBY MODE 4.7SV 2V l.sv OV

222 .,202A., 202AL WAVEFORMS Read cycle ADDRESS CHP ENABLE DATA OUTPUT S 0989 Write cycle ADDRESS tcw CHP ENABLE READt WRTE DATA NPUT DATA CAN CHANGE DATA STABLE..,

223 f'- f ~ NTEGRATED CRCUT r M 236E f6384 BT READ ONLY MEMORY t- SNGLE +5V ± 0% POWER SUPPLY lit ACCESS TME 450 ns (MAX.) iii NPUTS AND OUTPUTS TTL COMPATBLE f. THREE PROGRAMMABLE CHP SELECTS FOR SMPLE MEMORY EXPANSON AND SYSTEM. NTERFACE ~ COMPLETLY STATC OPERATON l* THREE-STATE OUTPUT FOR DRECT BUS NTERFACE ~ 'The M 236E is a 6384 bit static Read Only Memory N-channel Si-Gate MOS organized as 2048 words ;by 8 bits. ts high bit density is ideal for large, non-volatile data storage applications such as program ~.storage. The three-state outputs and TTL input/output levels allow for direct interface with common :;system bus structu res. -the M 236E is available in 24-lead dual-in-line plastic package. rabsolute MAXMUM RATNGS nput voltage (at any pin) Total power dissipation Storage temperature Operating temperature under bias '. This voltage is with respect to Ground -0.5 to 7-55 to to 80 v W DC DC ~RDERNG NUMBER: M 236E B for dual in-line plastic package MECHANCAL DATA Dimensions in mm ~ ~~.~

224 PN CONNECTONS A7 Vcc A6 A8 A5 A9 A4 A3 CS3 CS PN NAMES A2 AD A AD CS2 D7 AO -A0 ADDRESS NPUTS DO 06 0 D GNo 03 DO - 07 CSl - CS3 DATA OUTPUTS CHP SELECT NPUTS BLOCK DAGRAM DO D5 06 D7 AD A9 A8 A7 V a: w ~ A6 ~ ::> "- A5 ~ CHP SELECT PROG. V A4 V w a: 0 A3 0 " A2 A BT CELL MATRX CHP SELECT NPUT fu'fers CS CS2 AD CS3 S

225 M 238E, $TATC ELECTRCAL CHARACTERSTCS :otherwise specified) (T amb= O C to +70 C, Vee= 5V ± 0% unless Parameter Test conditions Min. Typ.(l) Max. Unit Ll nput load currentlal input pins) V = 0 to 5.25V 0 la LOH Output leakage current Chip deselected Vo= 4V 0 la LOL Output leakage current Chip deselected Vo= O.4V -20 la ce Power supply current All inputs 5.25V Data out open rna VL nput low voltage V VH nput high voltage 2.4 Vee+V V VOL Output low voltage OL= 2. ma 0.4 V VOH Output high voltage OH= -400 la 2.4 V Note: Typical values for Tamb= 25 C and nominal supply voltage. DYNAMC ELECTRCAL CHARACTERSTCS (Tamb = O C to 70 C, Vee= +5V ± 0%unless otherwise specified) Parameter Test conditions Min. Typ. Max. Unit ta Address to output delay time Output load = TTL gate 850 ns and CL = 00 pf teo Chip select to output enable nput pulse levels -0.8 to 2.4V nput pulse rise and fall times 20 ns tdf delay time Chip deselect to output data 0% to 90%) -20 ns Timing Measurement Reference level: nput = V and 2.2V 0 00 ns float delay time Output = 0.8V and 2.2V C nput capacitance T amb= 25 C f = MHz All pins except pin under test tied to AC ground 5 0 pf Co Output capacitance T amb= 25 C f= MHz All pins, except pin under test tied to AC ground 0 5 pf 235

226 M 236E A.C. Waveforms ADDRESS PROGRAMMABLE CHP SELECTS ~ k--! X tc:(l.. ~. i X tdf X ~ DATA OUTPUT 236

227 MOS NTEGRATED CRCUTS M 2708 M 2704 PRELMNARY DATA M K BT (024 X 8) UV ERASABLE PROM M K BT ( 52 X 8) UV ERASABLE PROM STANDARD POWER SUPPLES: +2V, +5V, -5V TTL COMPATBLE: ALL NPUTS AND OUTPUTS DURNG BOTH READ AND PROGRAM MODES THREE-STATE OUTPUT ORGANZATON: M X 8-BT N A 24-LEAD DUAL N-LNE PACKAGE M X 8-BT N A 24-LEAD DUAL N-LNE PACKAGE ACCESS TME: 450 ns MAX. FAST PROGRAMMNG: TYP. 00 sec. FOR ALL 8K BTS LOW POWER CONSUMPTON DURNG PROGRAMMNG The M 2708 and the M 2704 are high-speed 024 x 8/52 x 8-bit erasable and electrically reprogrammabie static ROMs (EPROM) manufactured in N-channel silicon gate MOS technology. They are supplied in 24-lead dual in-line ceramic package with transparent lid. The transparent lid allows the user to 'expose the chip to ultraviolet light to erase the bit pattern. A new pattern can then be written into the devices. The devices are fully static and therefore require no clocks to operate. ABSOLUTE MAXMUM RATNGS Voo Vee, Vss Vee CS'/WE Voo with respect to Vee Vee and V ss with respect to V BB All input or output voltages with respect to V BB during read nput with respect to V BB during programming Program input with respect to V BB Power dissipation Ambient temperature under bias Storage temoerature +20V to -0.3 V +5Vto-0.3 V +5V to -0.3 V +20V to -0.3 V +35V to -0.3 V.5 W -25 C to + ~5 C -65 C to +25 C ORDERNG NUMBERS: M 27 XX Fl for dual in-line ceramic package, frit seal MECHANCAL DATA dimensions in mm '~~:k; T fejej~ ~ U V r f Vii d M,, (25':' m m., Supersedes issue dated 6/ /79

228 M~2708 M 2704 PN CONNECTONS A7 Va: A A' * VB AJ fsfwe bo A2 A " PROGRAM AO " OJ " VSS r",.. " ' o. PN NAMES AO-A9 ADDRESS NPUTS 0-08 DATA OUTPUTS * PN Z2 ~ 'Vss FOR M04 PN 22."'9 FOR CS/WE CHP SELECT/WRTE ENABLE NPUT BLOCK DAGRAM OATA OUTPUT 0-08 CS/WE ---+ CHP SElECT logc OUTPUT BUFFERS AO A A2 Al y DECODER GATNG ACDAESS NPUTS A4 AS A6 A7 A8 A9 DECODER 64 J: 28 ROM ARRAY 5-225S MODE 9,,3,7 2 PN NUMBER READ PROGRAM DOUT DN Vss Vss Vss VDD V L Vee Pulsed Voo V HW Vee V~ Vee Vee 238

229 ~-. t "'EAD OPERATON to.c. AND OPERATNG CHARACTERSTCS (Vee= "+5V ± 5%, Voo= +2V ± 5%, Vss= -5V ± 5%, :Vss= OV, T amb = 0 to 70 C unless otherwise specified) Values Parameter Test conditions Unit Min. Typ.* Max. Ll Address and chip select input sink V~ 5.25V or V ~ V L 0 JA current Lo Output leakage current Vo~ 5.25V. CS/WE ~ 5V 0 JA ~DO Voo supply current Worst case supply current: ma cc Vee supply current all inputs high 6 0 ma SS Vss supply current CS/WE ~ 5V Tamb~O C ma V L nput low voltage VSS 0.65 V V H nput high voltage 3 Vec+ V VOL Output low voltage lol ~.6 ma 0.45 V VOH Output high voltage loh pa 3.7 V tvoh2 Output high voltage OH ~ - ma 2.4 V ff'tot Power dissipation Tamb~ 70 C 800 mw Typical values are for Tamb~ 25 C and nominal supply voltage. A.C. CHARACTERSTCS (Vee= +5V ± 5%, Voo= +2V ± 5%, Vss= -5V ± 5%, Vss= OV, T amb = 0!O 70 C unless otherwise specified) Parameter M M2708 M Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit tacc Address to output delay tco Chip select to output delay tof Chip de-select to output float toh Address to output hold ns ns ns ns CAPACTANCE (Tamb= 25 C, f = MHz) Parameter Test conditions C nput capacitance V~OV Co Output capacitance Vo ~ OV Values Min. Typ. Max Unit pf pf DYNAMC TEST CONDTONS: Output load = TTL gate and C L = 00 pf nput Rise and Fall Times =,,;;;; 20 ns Timing Measurement Reference Levels = O.8V and 2.8V for inputs; 0.8V and 2.4V for outputs. nput Pulse levels = 0.65V to 3V. 239

230 WAVEFORMS ADDRESS ==>< -.JX' _ 0H CSfWE DATA OUT D_~_A_O_U_T NV_A_Lt_Oi J~' ~,_~_~_6~_t_'~ ~ 5-22')6 PROGRAMMNG nitially, and after each erasure, all bits of the M 2708/2704 are in the "'" state (output high). nformation is introduced by selectively programming "0" into the desired bit locations, A programmed "0" can only be changed to a "'" by UVerasure, The circuit is set up for the programming operation by raising the CS/WE input (pin 20) to +'2V. The word address is selected in the same manner as in the read mode. Data to be programmed are presented, 8-bits in parallel, to the data output lines (0'-08), The logic levels for address and data lines and the supply voltages are the same as for the read mode. After address and data set up, one program pulse fo~ address is applied to the program input (pin 8). One pass through all addresses is defined as a program loop, The number of loops (N) required is a function of the program pulse width (tpw ) according to Nxtpw ;;;. '00 ms. The width of the program pulse is from 0, to, ms. The number of loops (N) is from a minimum of loq (t pw= ms) to greater than 000 (tpw= 0. ms). There must be N successive loops through all 024 address. t is not permitted to apply N program pulses to an address and then change to the next address to be programmed. Caution should be observed regarding the end of a program sequence. The CS/WE falling edge transition must occur before the first address transition when changing from a program to a read cycle. The pro; gram pin should also be pulled down to V LP with an active instead of a passive device.this pin will sourc4! a small current (l pl ) when CS/WE is at V HW (2V) and the program is at V LP' Truth table formats for printed cards and paper tape must be compatible with ntel ones. ERASURE CHARACTERSTCS The erasure characteristics of the M 2708 are such that erasure begins to occur when exposed to light' with wavelengths shorter than approximately 4000 Angstroms (A). t should be noted that sunlight and, certain types of fluorescent lamps have wavelengths in the A range. Data show that constant' exposure to room level fluorescent lighting could erase the typical M 2708 in approximately 3 years: while it would take approximately week to cause erasure when exposed to direct sunlight, ; The recommended erasure procedure for the M 2708 is exposure to shortwave ultraviolet light which has' a wavelength of 2537 Angstroms (A). The integrated dose (i.e" UV intensity X exposure time) for erasure, should be a minimum of 5 W-sec/cm2, The erasure time with this dosage is approximately 5 to 2Q, minutes using an ultraviolet lamp with a 2000 jjw/cm 2 power rating. The M 2708 should be placed within inch of the lamp tubes during erasure, Some lamps have a filter on their tubes which should be~ removed before erasure. 240

231 ~... f, ffiogram CHARACTERSTCS ~.C. PROGRAMMNG CHARACTERSTCS (Tamb= 25 C, Vcc= +5V ± 5%, Voo= +2V ± 5%, tllb= -5V ± 5%, Vss= OV unless otherwise specified) Values Parameter Test conditions Unit Min. Typ. Max. ll' Address CS/W input sink current Vi = 5.25V 0 jj.a ~PL Program pulse source current 3 ma f"'h Program pulse sink current 20 rna loo Voo supply current Worst case supply current ma 'tec V cc supply current all inputs high 6 0 ma 8B V BB supply current CS/WE= 5V; Tamb= O"C ma VL nput low level (except program) Vss 0.65 V rvlh nput high level for all address or 3 V CC+l V.' data.vhw e5/we input high level referenced to V V "HP Program pulse high level referenced to V V ivllp Program pulse low level VHP-VLP= 25V min. Vss V ~C. PROGRAMMNG CHARACTERSTCS Values, Parameter Test conditions Min. Typ. Max. Unit ~AS Address setup ti me 0 jj.s!tess ~/WE setup time 0 jj.s tos elata setup time 0 jj.s [tah Address hold time jj.s tch ~/WE hold time 0.5 jj.s ~OH Data hold time jj.s tof Chip deselect to output float delay 0 20 ns,dpr Program to read delay 0 jj.s ~ Program pulse width 0. ms ~R Program pulse rise time jj.s _ ~F Program pulse fall time jj.s 24

232 PROGRAMMNG WAVEFORMS VHW OF N PROGRAM loops (AFTER N PROG. LOOPS'" READ CS/WE ADDRESS DATA V,L v," Vl V," V,L NOTE ADDRESS 0 lace 4SOn. MAl DATA OUT VALD PROGRAM PULSE V,L NOTE t: THE CSWE TRANSTON MUST OCCUR AFTER THE PROGRAM PULSE TRANSTON AND BEFORE THE AOORESS TRANSTON NOTE 2: NUMBERS N () NDCATE MNMUM TMNG N}JS UNLESS OTHERWSE SPECFED 242

233 0S NTEGRATED CRCUT? BT DYNAMC RANDOM ACCESS MEMORY. POWER SUPPLY Voo= 2V, Vee= 5V, Vee= -5V (ALL WTH ± 0% TOLERANCE) '. ALL NPUTS ARE LOW CAPACTANCE AND TTL COMPATBLE NPUT LATCHES FOR ADDRESSES, CHP SELECT AND DATA N ~. NPUTS PROTECTED AGANST STATC CHARGE ;. THREE-STATE TTL COMPATBLE OUTPUT C. OUTPUT DATA LATCHED AND VALD NTO NEXT CYCLE. ' ECLCOMPATBLE ON Vee POWER SUPPLY (-5.7V) LOW POWER CONSUMPTON: ACTVE POWER UNDER 470 mw STANDBY POWER UNDER 27 mw ORGANZATON 4096 x BT N 6-PN STD PACKAGE /. FUNCTONAL AND PN COMPATBLE WTH MK4027. ACCESS TME: TYPE M ns TYPE M ns TYPE M ns The M 4027 is a 4096 word by bit dynamic N-channel silicon gate MOS RAM. The M 4027 uses a single transistor cell utilizing a dynamic storage technique and dynamic control circuitry with low power dissipation. A unique multiplexing and latching technique for the address inputs permits the M 4027 to be mounted in a standard 6-pin package. The M 4027 incorporates several flexible operating modes. n addition to the usual read and write cycles, read modify write, page mode and RAS-only refresh cycles are available with the M Page-mode timing is very useful in systems requiring Direct Memory Access (DMA). The device is available in 6-lead dual in-line plastic or ceramic package (metal-seal), and ceramic package (frit-seal). ABSOLUTE MAXMUM RATNGS* Voltage on any pin relative to Vee Voltage on Voo, Vee relative to Vss Vee-Vss (Voo-Vss > O) Operating temperature Storage temperature for ceramic package for plastic package Short circuit output current Total power dissipation -0.5 to +20 V - to + 5 V o V Oto +70 C -65 to +50 C -55 to +25 C 50 ma W Stresses greater than those listed under "Absolute Maximum Ratings' may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indio cated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ORDERNG NUMBERS: M /3/4 B M /3/4 D M /3/4 F Supersedes issue dated 3/78 for dual in-line plastic package for dual in-line ceramic package, metal-seal for dual in-line ceramic package, frit-seat 243 9/79

234 MECHANCAL DATA (dimensions in mm) Dual in-line ceramic package frit-seal for M F ~ L:t Dual in-line ceramic package metal-seal for M D 74'... PO ~ib ~~~ ()J,, 2.5,::::f! "L'~ t778 ~.,, 2~S3m.. : tejj Dual in-line plastic package for M B >~,'~~.0,", ~ 20"' ' ~::::::: ~O: C PN CONNECTONS POWER(-$V) Vea GROUf"D BLOCK DAGRAM ~---~==~ ""..... DATA N COL_ AOORESS STROOE ~~fe' WRTE 3 NPUT."" ADDRESS STROE ADORESS '''''''T ADORESS NPUT A. CHP SELEtT ADDRESS '''''' AOORESS 'NPJT CiS "... ADORESS NPUT 0 9 AS ADORESS 'NPJT Vee FOo R{.5V),, et,~o;' ncnlu...n SELEct LNES,, -----L---LJ... SENS{.f(FAE$H.lMl>lFERS D.. T" ~ DATA OUT GATNG 244

235 .4027 ;RECOMMENDED DC OPERATNG CONDTONS! (T amb = 0 to 70 C)4 Parameter Values Min. Typ. Max. Unit Notes Voo Supply voltage V Vee Supply voltage V VSS Supply voltage a a a V Vee Supply voltage V VHe nput high voltage on RAS, CAS, WR TE V VH nput high voltage, all inputs except RAS, CAS, WR TE V 'V L, nput low voltage, all inputs V 2 2, DC ELECTRCAL CHARACTERSTCS (Tamb = 0 to 70 C)4 (Voo= 2V ± 0%, Vee= 5V ± 0%, Vss= OV, Vee= - 5,7 to -4.5V) Parameter Values Min. Typ, Max. Unit Notes 00 Average Voo power supply current 35 ma 002 Standby Voo power supply current 2 ma 003 Average Voo power supply current during "RAS only" cycles 25 ma cc Vee power supply current ma lee Average Vee power supply current 50 /la (L) nput leakage current (any input) 0 /la O(L) Output leakage current 0 /la VOH Output high voltage (lsou RCE= -5 mal 2.4 V VOL Output low voltage ( SNK= 3.2 mal 0.4 V ,9 245

236 M4027 AC CHARACTERSTCS AND RECOMMENDED OPERATNG CONDTONS.lo.ls (Tamb= 0 to 70 C)4. (Voo= 2V ± 0%. VCC= 5V ± 0%. Vss= OV. V BB= -5.7 to -4.5V) Types Parameter M M M Unit Notes Min. Max. Min. Max. Min. Max. trc Random read or write cycle time ns trwc Read write cycle time ns trmw Read modify write cycle time ns trac Access time from row address ns -3 strobe tcac Access time from column address ns 2-3 strobe toff Output buffer turn-off delay ns trp Row address strobe precharge ns time tras Row address strobe pulse width ns trsh Row address strobe hold time ns tcas Column address strobe pulse width ns tcsh Column address strobe hold time ns trco Row to column strobe delay ns 4 tasr Row address set-up time ns trah Row address hold time ns tasc Column address set-up time ns tcam Column add,,,ss hold time ns tar Column address hold time ns referenced to R AS tcsc Chip select set-up time ns tch Chip select hold time ns tchr Ch~ect hold time referenced ns to RAS tt Transition time (rise and fall) ns 5 trcs Read command set-up time ns trch Read command hold time ns twch Write command hold time ns twcr Write command hold time ns referenced to RAS twp Write command pulse width ns trwl Write command to row strobe ns lead time tcwl Write command to column strobe ns lead time tos Data in set-up time ns 6 246

237 M4027 AC CHARACTERSTCS AND RECOMMENDED OPERATNG CONDTONS (cont.) Types Parameter M M M Unit Notes Min. Max. Min. Max. Min. Max. toh Data in hold-time ns 6 tohr Data in hold time referenced to ns RAS tcrp Column to row strobe precharge ns time tcp Column precharge time ns trfsh Refresh period ms twcs Write command set-up time ns 7 tcwo CAS to WR TE delay ns 7 trwo RAS to WRTE delay ns 7 tooh Data out hold time ls CAPACTANCES (Tamb= 0 to 70 C, Voo= 2V ± 0%; Vss= OV; V BB= -5.7 to -4.5V) Parameter Typ. Values Max. Unit Notes Cil nput capacitance (Ao-A5), DN, CS 4 5 pf 8 C 2 nput capacitance RAS, CAS, WR TE 8 0 pf 8 Co Output capacitance (DOUT) 5 7 pf 8-8.Several cycles are required after power-up before proper device operation is achieved. Any 8 cycles which perform refresh are adequate for this purpose. 2.A voltages referenced to Vss. V BB must be applied before and removed after other supply voltages. 3.0utput voltage will swing from Vss to Vcc when enabled, with no output load. For purposes of maintaining data in standby mode, Vcc may be reduced to Vss without affecting refresh operations or data retention. However, the VOH (min) specification is not guaranteed in this mode. 4.T illb is specified for operation at frequencies to trc ~ trc (min). Operation at higher cycle rates with reduced ambient temperatures and higher power dissipation is permissible provided that all AC parameters are met. 5.Current is proportional to cycle rate. 00 (max) is measured at tne cycle rate specified by trc (min). 6.lcc depends on output loading. The V cc supply is connected to the output buffer only. 7.A device pins at 0 volts except V BB whi~at -5V and the pin under test which is at +0V. 8.0utput is disabled (high-impedance) and RAS and CAS are both at a logic. Transient stabilization is required prior to measurement of this parameter. 9.0V" V out "+0V. 0.AC measurements assume tt= 5 ns..assumes that trco " trco (max). 2.Assumes that trco ~ trco (max). 3.Measured with a load circuit equivalent to 2 TTL loads and 00 pf. 4.0peration within the trco (max) limit insures that trac (max) can be met. trco (max) is specified as a reference point only; if trco is greater than the specified trco (max) limit, then access time is controlled exclusively by tcac' 5,VHC (min) or V H (min) and V L (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V HC or.~h and V L. 6.These parameters are referenced to CAS leading edge in random write cycles and to WRTE leading edge in delayed write or read-modify-write cycles. 7.twcs, tcwo, and trwo are restrictive operating parameters in a read/write or read/modify/write cycle only. f, twcs ~ twcs (min), the cycle is an early write cycle and Data Out will contain the data written into the selected cell. f tcwo ~ tcwo (min) and trwo ~ trwo (min), the cycle is a read-write cycle and Data Out will contain data read from the selected cell. f neither of the above sets of conditions is satisfied, the condition of Data Out (at access time) is indeterminate. f Q 8. Effective capacitance is calculated from the equation: C =----z;;v-with fv = 3 volts. 247

238 READ CYCLE RAS V,HC V,L CAS VHe V,L VHC~7n~/;77n~7i,n7~ ~~~~~~ V,L ~ ~------~~ VOL ~::::::::~::==:::::::::::::~--~~~----~~~== ~ ~~ WRTE CYCLE (early write) trc ill V,HC V,L tree tar tra CAS VHC V,L ADORESSES V,H V,L WRTE V,HC V,L DN V,H V,L cs V,H V,L Dour VOH VOL t ---~ OPEN VAUO DATA S-D'Z 248

239 .402 READ WRTE/READ MODFY-WRTE CYCLE m VHC Vil ~m VHC Vil VH ADDRESSESVll.W/im VHC Vil B VH Vil!louT VOH VO~ Dw VH Vil PAGE MODE READ CYCLE iie VHC Vil CAS "He Vil AOORESS VH VL cs VH VL OUT VOH VOL WAiTE 249

240 PAGE MODE WRTE CYCLE R.t.S V,HC V,l ' CiS VHC v" V,H ADDRESSES V'l C5 V,H V,l OUT VOH VOL WRTE DN V'HC V,l V,H V,L )'// 5-22&42 RAS ONLY REFRESH CYCLE V,He ,L V,l ADDRESSES V,L DOUT 5-226,# 250

241 M4027 ~ADDRESSNG The 2 address bits required to decode one of 4096 cell locations within the M 4027 are multiplexed : onto the 6 address inputs and latched into the on-ch ip row and column address latches. ~ Row Address Strobe (RAS) latches the six row address bits onto the chip. Column Address Strobe ~(CAS) latches the six column address bits plus Chip Select (CS) onto the chip. ~Since the internal circuitry allows the columns information to be externally applied to the chip before it ~ is actually required, the hold time requirements for column address and CS are also referenced to RAS. ~ However, this gated CAS feature allows the systems designer to compensate for timing skews that may 'be encountered in the multiplexing operation. ~Since the Chip Select signal is not required until CAS time, which is well into the memory cycle, its ~decoding time does not add to system access or cycle time. Additional timing margin is gained because column address is not required until CAS makes its negative. transition.. The timing is further simplified by the positive transition of CAS not being referenced to the positive transition of RAS. n fact, CAS need not go HGH until the beginning of the next cycle. DATA NPUT/OUTPUT Data to be written into selected storage cell of the memory chip is first stored in the on-chip data latch. The gating of this latch is performed with a combination of WRTE and CAS while RAS is active. The later of this signals (WRTE or CAS) to make its negative transition is the strobe for the Data n into the latch. This permits several options in the write cycle timing. n a write cycle, if the WRTE input is activated prior to CAS, the Data n is strobe by CAS, and set-up time and hold time are referenced to CAS. f the Data n input is not available at CAS time or the cycle is a read-write or readmodify-write, the WRTE signal must be delayed until after CAS. n this "delayed write cycle" the data input set-up and hold times are referenced to the negative edge of WR TE rather than to CAS. (To illustrate this feature, Data n is referenced to WRTE in the timing diagram depicting the read-write and page mode write cycles while the "early write" cycle diagram shows Data n referenced to CAS) Note that if the chip is unselected (CS high at CAS time) WRTE commands are not executed and, consequently, data stored in the memory is unaffected. Data is retrieved from the memory in read cycle by maintaining WRTE in the inactive or high state throughout the portion of memory cycle in which CAS is active. Data read from the selected cell will be available at the output within the specified access time. DATA OUTPUT CONTROL At the beginning of a memory cycle, the state of the Data Out latch and buffer depend on the previous memory cycle. Changes in the condition of Data Out latch are initiated by CAS. The negative transition of CAS causes the Data Output (D out ) to unconditionally go to its open-circuit state. f will remain open-circuited until after the access DouT time, the will assume the proper state for the type of cycle; performed. f the cycle is a read; read-modify-write, or a delayed write and the chip is selected, then the DouT atch and buffer will contain the data from the selected cell. This output data is the same polarity (not inverted) as the input data. f the cycle is a write cycle (WR TE active low before CAS goes low) and the chip is selected, then DouT will contain the input data. Once the DouT goes active, it will remain active until the next negative transition of CAS. f the cycle is a CAS only cycle (no RAS sig~ then QQuT will assume the open - circuit state. The same istrue for normal cycles (both RAS and CAS present-when the chip is unselected DouT remains in the open-circuit state until the next negative transition of CAS. RAS only refre5h cycles (no CAS) have no effect on the DouT. However, when RAS only refresh cycles are continued for extended periods of time, Do UT may eventually go open-circuit. f the chip unselected, it will not accept a write command and the DouT will remain in the open-circuit state. 25

242 M4027 NPUT/OUTPUT LEVELS All inputs, including the two address strobes, interface directly with TTL. The high-impedance, low-capacitance input characteristics simplify input driver selection by allowing use of standard logic elements rather than specially designed driver elements. The 3-state output buffer is a low impedance to Vee for a logic "" and a low impedance to Vss for a logic "0". The output resistance to Vee (logic "" state) is 420 ohm maximum and 35 ohm tipically. The output resistance to Vss (logic "0" state) is 25 ohm maximum and 35 ohm tipically. The separate Vee pin allows the output buffer to be powered from supply voltage of the logic to which chip is interfaced. During battery stand-by operation, the Vee pin may be unpowered without effecting the M 4027 refresh operation. This allows all system logic, except RAS timing circuitry and refresh address logic, to be turned off during battery stand-by to save power. REFRESH Refresh of the dynamic cell matrix is accomplished by performing a memory cycle at each of the 64 row address every two millisecond or less. Any cycle in which a RAS signal occurs, accompl ished a refresh operation. A read cycle will refresh the selected row, regardless of the state of the Chip Select (CS) input. A write or read-modify-write cycle also refreshes the selected row, but the chip should be unselected to prevent writing data into the selected cell. f, during a refresh cycle, the M 4027 receives a RAS signal but no CAS signal, the state of the output will not be affected. However, if "RAS-only" refresh cycles (when RAS is the only signal applied to the chip) are contained for extended periods, the output buffer may eventually lose proper data and go open-circuit. The output buffer will regain activity with the first cycle in which a CAS signal is applied to the chip. POWER DSSPATON/STANDBY MODE Most of the circuitry used in the M 4027 and most of the power drawn is the result of an address strobe edge. Because the power is not drawn during the time the strobe is active, the dynamic power is a function of operating frequency rather than active duty cycle. Tipically, the power is 70 mw at J.l.sec cycle rate for M 4027 with a worse case power of less than 470 mw at 320 J.l.sec cycle time. To reduce the overall system power, the Row Address Strobe (RAS) should be decoded and supplied to only the selected chips. The CAS must be supplied to all chips (to turn off the unselected output). Those chips that did not receive a RAS, however, will not dissipate any power on the CAS edges, except for that required to turn off the outputs. f the RAS signal is decoded and supplied only the selected chips, then the chip select (CS) input of all chips can be at a logic O. Then chips that receive a CAS but no RAS will be unselected (output open-circuited) regardless of the Chip Select input. For refresh cycles, however, either the CS input for all chips must be high or the CAS input must be held high to prevent several "wire-or" outputs from turning on with opposing force. Note that the M 4027 will dissipate considerably less power when the refresh operation is accomplished with a "RAS-only" cycle as opposed to a normal RAS/CAS memory cycle. 252

243 . PAGE MODE OPERATON The "Page mode" feature of the M 4027 allows for successive memory operations at multiple column location of the same row address with increased speed without an increase in power. This is done by strobing the row address into the chip and keeping the RAS signal at logic 0 throughout : all successive memory cycles in which the row address is common. This "Page Mode" of operation will not dissipate the power associated with the negative going edge of. RAS. The time required for strobing in a new row address is eliminated, thereby decreasing the access and cycle times. The chip select input (CS) is operative in page made cycles just as in normal cycles. t is not necessary that the chip be selected during the first operation in sequence of page cycles. Likewise, the CS input can be used to select or disable any cycle(s) in a series of page cycles.. This feature allows the page boundary to be extended beyond the 64 column location in a single chip. 'The page boundary can be extended by applying RAS to multiple 4K memory blocks and deconding CS 'to select the proper block. POWER UP The M 4027 requires no particular power supply sequencing so long as the Absolute Maximum Rating Conditions are observed. However, in order to insure compliance with the Absolute Maximum Ratings, SGS-ATES recommends sequencing of power supplies such that Vss is applied first and removed last. Vss should never be more positive than V 55 when power is applied to V DD. Under system failure condiction in which one or more supplied exceed the specified limits significant additional margin against catastrophic device failure may be achieved by forcing RAS and Data Out to the inactive state. After power is applied to the device, the M 4027 requires several cycles before proper device operation is achieved. Any 8 cycles which perform refresh are adequate for this purpose. 253

244 .os NTEGRATED CRCUT ~ t '6384-BT DYNAMC RANDOM ACCESS MEMORY M 48 PRELMNARY DATA RECOGNZED NDUSTRY STANDARD 6-PN CONFGURATON 50ns ACCESS TME, 320ns CYCLE (M 46-2) 200ns ACCESS TME, 375ns CYCLE (M 46-3) 250ns ACCESS TME, 40ns CYCLE (M 46-4) ± 0% TOLERANCE ON ALL POWER SUPPLES (+ 2V, ±5V) LOW POWER: 462 mw ACTVE, 20 mw STANDBY (MAX) OUTPUT DATA CONTROLLED BY CAS AND UNLATCHED AT END OF CYCLE TO ALLOW ~~. lwo DMENSONAL CHP SELECTON AND EXTENDED PAGE BOUNDARY COMMON /O CAPABLTY USNG "EARLY WRTE" OPERATON READ-MODFY-WRTE, RAS-ONL Y REFRESH, AND PAGE-MODE CAPABLTY ~. ALL NPUTS TTL COMPATBLE, LOW CAPACTANCE, AND PROTECTED AGANST STATC >. CHARGE ~ 2B REFRESH CYCLES :. MOSTEK 46 PN TO PN REPLACEMENT '.- ECL COMPATBLE ON Vee POWER SUPPLY (-5.7V) ~the M 46 is a new generation MOS dynamic random access memory circuit organized as 6384 words :.'by bit. The technology used to fabricate the M 46 is double-poly N-channel silicon gate. This process, coupled with the use of a single transistor dynamic storage cell, provides the maximum posl$ible circuit density and reliability, while maintaining high performance capability. The use of dynamic,'circuitry through-out, including sense amplifiers, assures that power dissipation is minimized without ~ny sacrifice in speed or operating margin. lmultiplexed address inputs permits the M 46 to be packaged in a standard 6-pin DP. The device is tavailable in 6-lead dual in-line ceramic package. ABSOLUTE MAXMUM RATNGS* Top Tstg Voltage on any pin relative to Vee Voltage on VDD, Vee supplies relative to Vss Vee-Vss (VDD-VSS > OV) Operating temperature Storage temperature for ceramic package. for plastic package 0 Short circuit output current Ptot Total power dissipation -0.5 to +20 V - to+5 V 0 V o to +70 C -65 to +50 C -55 to + 25 c 50 ma W Stresses greater than those listed under" Absolute Maximum Ratings" may cause permanent damage tothe device. This is a stress rating only and functional operation of the device at these or any other condition above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. ORDERNG NUMBERS: M 46-2/3/4 D for dual in-line ceramic package, metal-seal M 46-2/3/4 F for dual in-line ceramic package, frit-seal 255 7/79

245 MECHANCAL DATA (dimensions in mm) Dual in-line ceramic package Dual in-line ceramic package :3,"f';~"". ~ f ~~, ~ ~ LrrJ _. CE3J _. PN CONNECTONS Voa Vss D,N 5 CAS WRTE 3. DOUT.AS 3 A. BLOCK DAGRAM - - 'Do - '« 'iss.. -~-.. DATA '...' AD Z A3 A2 A. A 0 AS VDD Vee., PN NAMES 5-29)7 " ~A6 ~g~~~~s ~ci~~~~s STROBE DN DATA N ~T ~6~~~~~ESS STROBE W!lTE' Vaa Vee Voo Vss REAOWRTE NPUT POWER (-6V) POWER (+5V) POWER (+2V) GROUND " CJ!..4r«CELLS.4-CCU... 5(LECT LNES COllMll OECCDERS, OF 4., 256

246 M 48 ~ECOMMENDED DC OPERATNG CONDTONS (Tamb= 0 to 70 C) Types Parameter Unit Nota i ~' Min. Typ. Max.,Voo Supply voltage V 2 ~VCC Supply voltage V 2.3,VSS Supply voltage V 2 "'BB Supply vol tage V 2 W HC nput high voltage on RAS, CAS, WRTE V 2 "VH nput high voltage, all inputs except RAS, CAS, WRTE V 2 lvl nput low voltage, all inputs V 2 DC ELECTRCAL CHARACTERSTCS (Tamb = 0 to 70 C), Voo= 2V±0~ Vcc= 5V±00/0; VBB = -5.7 to -4.5V; Vss= OV).. Types Paramatar Test conditions M 46-2/3 M46-4 Unit Nota Min. Max. Min. Max. 00 Average operating current ma 4 RAS, CAS cycling CCl Average operating current 5 trc= trc min) 'BB Average operating current' JA 002 Standby current.5.5 ma RAS = V CC2 Standby current HC DOUT= High impedance JA tbb2 Standby current 00 JA 003 Refresh average current Refresh mode: RAS cycling ma 4!eC3 Refresh average current CAS = VHC JA BB3 Refresh average current trc= tre (min) 200 JA 004 Page mode average current Page mode: RAS = VL ma 4 CC4 Page mode average current CAS cycling 5 tpc~ BB4 Page mode average current tpc (min) 200 JA 'll) nput leakage current VBB- -5V OV'; V N.; +7V, all other pins not under test = 0 volts JA 'OL) Output leakage current DOUT in disabled OV.; V OUT ~ +5.5V JA VOH Output high voltage OUT--5 ma 2.4 ; 2.4 V 3 VOL Output low voltage OUT-4.2 ma V 3 257

247 M 46 ELECTRCAL CHARACTERSTCS AND RECOMMENDED AC OPERATNG CONDT. (T amb= Oto 70 C), Voo= 2V± 0%; VCC= 5V± 0%;V ss=ov, V BB= -5.7 to -4.5V) Types Parameter M 46-2 M 46-3 M 46-4 Unit Note Min. Max. Min. Max. Min. Max. trc Random read or write cycle time ns 9 trwc Read-write cycle time ns 9 trmw Read modify write cycle time ns 9 tpc Page mode cycle time ns 9 trac Access time from RAS ns 0,2 tcac Access time from CAS ns,2 toff Output buffer turn-off delay ns 3 tt Transition time (rise and fall) ns 8 trp RAS precharge ti me ns tras RAS pulse width ns trsh RAS hold time ns tcsh CAS hold time ns trco RAS to CAS delay time ns 4 tcas CAS pulse width ns tcrp CAS to RAS precharge time ns tasr Row address set-up time ns trah Row address hold time ns tasc Column address set-up time ns tcah Column address hold time ns tar Column address hold time referenced to ns RAS trcs Read command set-up time ns trch Read command hold time ns twch Write command hold time ns twcr Write command hold time referenced to RAS ns twp Write command pulse width ns trwl Write command to RAS lead time ns tcwl Write command to CAS lead time ns tos Data-in set-up time ns 5 toh Data-in hold time ns 5 tohr Data-in hold time referenced to RAS ns tcp CAS precharge time (for page mode cycle only) ns tref Refresh period ns twcs WRTE command set-up time ns 6 tcwo CAS to WRTE delay ns 6 trwo RAS to WR TE delay ns 6 258,

248 M 46 ~ tes: 't.tamb is specified here for operation at frequencies to trc;;' trc (min). Operation at higher cycle rates with reduced, ambient temperatures and higher power dissipation is permissible,however,provided AC operating parameters are met....a voltages referenced to Vss. [ Output voltage will swing from VSS to VCC when activated with no current loading, For purposes of maintaining, data in standby mode, VCC may be reduced to V ss without affecting refresh operations or data retention. However, the VOH (min) specification is not guaranteed in this mode. 00' 003 and 004 depend on cycle rate. CC and CC4 depend upon output loading. During read out of high level data V CC is connected through a low : impedance to data out. At all other times CC consists of leakage currents only. ".several cycles are required after power-up before proper device operation is achieved. Any 8 cycles which perform, refresh are adequate for this purpose. '/.AC measurements assume tt = 5 ns. VHC (min) or V H (min) and V L (max) are reference levels for measuring timing of input signals. Also, transition,:' times are measured between V HC or VH and V L.,.The specifications for trc (min) and trwc (min) are used only to indicate cycle time at which proper operation l.. over the full temperature range (DOC";; T amb,,;; 70 C) is assured. f/-assumes that trco,,;; trcd (max!. f trcd is greater than the maximum recommended value shown in this table, ~ trac will increase by the amount that trcd exceeds the value shown. Assumes that trcd ;;. trcd (max!..measured with a load equivalent to 2 TTL loads and 00 pf. ". toff (max) defines the time at which the output achieves the open circuit condition and is not referenced to ':' output voltage levels. ~4.0peration within the trcd (max) limit insures that trac (max) can be met. trcd (max) is specified as a reference t point only;if trcd is greater than th~cified trcd (max) limit, then access time is controlled exclusively by tcac' 6. These parameters are referenced to CAS leading edge in early write cycles and to WR TE leading edge in delayed ~ write or read-modify-write cycles.!6.twcs, tcwd and trwd are not restrictive operating parameters. They are included in the data sheet as electrical ~ characteristics only: f twcs ;;. twcs (min), the cycle is an early write cycle and the data out pin will remain open ( circuit (high impedance) throughout the entire cycle; f tcwd;;' tcwd (min) and trwd;;' trwd (min), the cycle is r, a read-write cycle and the data out will contain data read from the selected cell; f neither of the above sets of con ~ ditions is satisfied the condition of the data out (at access time) is indeterminate. ['. Effective capacitance calculated from the equation C = ~vt with /:'v = 3 volts and power supplies at nominal levels. :8.CAS = V HC to disable DOUT,. "'APACTANCES (T amb= o to 70 e ~ 0, V 00= 2V %; V ss= OV;Vss= -5.7 to -4.5V) " Parameter Min. Typ. Max. Unit Notes ~C nput capacitance (Ao-AS) DN 4 5 pf 7 \.C2 nput capacitance RAS, CAS, WRTE 8 0 pf 7 ~o Output capacitance (DoUT) 5 7 pf 7,8 259

249 M 46 READ CYCLE ~ c ~ s ~ RAS 'CSt< : ~.co --J CAS VH_ ADDRESSES "'L- WRTE ~tcac lrac _ ~ --_-~-OFF DOUT v~ VOL - OPEN VALD DATA S-2942 WRTE CYCLE (EARLY WRTE) ~ C ~ ~ t RA$ V HC '" tar L - V'HC i-i , VL -. t... ADDRESSES v, H_'7'?'7'7'7'77777rlrrrrrr~ lr-'--==~--'\ rrrrrrrrrrr.rr.'7'7'7'7'7' "rrrrrr.... V, L -"-'-'-''''''''-'-'-'-.....,.-'-'-'-''-'-'-'... OHO ~ DOUT VOH - VOL OPEN

250 M46 AO-WRTE/READ-MODFY-WRTE CYCLE ---- t twe / MW ----., t [ ~. r OUT ~., ~ DN r' " ~AS-ONLY" REFRESH CYCLE RAS V He- V L - f,.. t., t FlAS to, t top ~.. "H- ROW. ADDRESSES ADDRESS "OH - OPEN ::-:: S

251 M 46 PAGE MODE READ CYCLE RAS VHC. V L - tar - -- t RAS, CAS V MC _ VL - V M - AOOMESSES VL-, DOUT WRTE VOH - V OL - VMC,..' V L _/ '""~ trch~ ~'"" // PAGE MODE WRTE CYCLE ---- t RAS ADDRESSES D'N twp~ _ t RWL tom ~ ~~k:0?tlffizj s

252 M 46 f PESCRPTON oriented features include ±0% tolerance on all power supplies, direct interfacing capability with E-stem '. performance logic families such as Schottky TTL, maximum input noise immunity to minimize. alse triggering" of the inputs (a common cause of soft errors), on-chip address and data registers which ~minate the need for interface registers, and two chip select methods to allow the user to determine the ippropriate speed/power characteristics of his memory system. The M 46 also incorporates several xible timing/operating modes. n addition to the usual read, write. and read-modify-write cycles, the 46 is capable of delayed write cycles, page-mode operation and RAS-only refresh. Proper control [".. the clock inputs (RAS, CAS and WRTE) allows common /O capability, two dimensional chip selec. n, and extended page boundaries (when operating in page mode). t looressng the 4 address bits required to decode of the 6,384 cell locations within the M 46 are multiplexed ~to the 7 address inputs and latched into the on-chip address latches by externally applying two nega ;Ve going TTL-level clocks. The first clock, the Row Address Strobe (RAS), latches the 7 row address ~ts into the chip. The second clock, the Column Address Strobe (CAS), subsequently latches the 7 Olumn address bits into the chip, Each of these signals, RAS and CAS, triggers a sequence of events irilich are controlled by different delayed internal clocks. The two clock chains are linked together logi ially in such a way that the address multiplexing ope~ation is done outside of the critical path timing [equence for read data access. The later events in the CAS clock sequence are inhibited until the occur ~ce of a delayed signal derived from the RAS clock chain. This "gated CAS" feature allows the CAS ~k to be externally activated as soon as the Row Address Hold Time specification (trah) has been ti.f;"d and the address inputs have been changed from Row address to Column address information. ilote that CAS can be activated at any time after trah and it will have no effect on the worst case data ~ess time (tracl up to the point in time when the delayed row clock no longer inhibits the remaining jequence of column clocks. Two timing end-points result from the internal gati!!llqf CAS which are ;ailed t RCD (min) and t RCD (max). No data storage or reading errors will result if CAS is applied to the 46 at a point in time beyond the t RCD (max) limit. However, access time will then be determined jxelusively by the access time from CAS (tcac ) rather than from RAS (trac), and access time from RAS will be lengthened by the amount that t RCD exceeds the t RcD (max) limit. PATANPUT/OUTPUT )ata to be written into a selected cell is latched into an on-chip register by a combination ofwrtt and ~ while RAS is active. The later of the signals (WR TE or CAS) to make its negative transition is the ~fobe for the Data n (DN) register. This permits several options in the write cycle timing. n a write!vele, if the WR TE input is brought low (active) prior to CAS, the DN is strobed by CAS, and the set-up ld hold times are referenced to CAS. f the input data is not available at CAS time or if it is desired that itle cycle be a read-write cycle, the WRTE signal will be delayed until after CAS has made its negative transition. n this "delayed write cycle" the data input set-up and hold times are referenced to the nega ~ive edge of WRTE rather than CAS. (To illustrate this feature, DN is referenced to WRTE in the timng diagrams depicting the read-write and page-mode write cycles while the "early write" cycle diagram!hows DN referenced to CAS). :>ata is retrieved from the memory in a read cycle by maintaining WR TE in the inactive or high state ihroughout the portion of the memory cycle in which CAS is active (low). Data read from the selected ~ will be available at the output within the specified access time.. OATA OUTPUT CONTROL rhe normal condition of the Data Output (D out ) of the M 46 is the high impedance (open-circuit)!fate. That is to say, anytime CAS is at a high level, the DouT pin will be floating. The only time the ~tput will turn on and contain either a logic 0 or logic is at access time during a read cycle. DouT will remain valid from access time until CAS is taken back to the inactive (high level) condition. 263

253 M 48 DATA OUTPUT CONTROL (continued) f the memory cycle in progress is a read, read-modify write, or a delayed write cycle, then the data outputwill go from the high impedance state to the active condition,and at access time will contain the data~ read from the selected cell. This output data is the same polarity (not inverted) as the input data. Once. having gone active, the output will remain valid until CAS is taken to the precharge (logic ) state, whether or not RAS goes into precharge. f the cycle in progress is an "early-write" cycle (WRTE active before CAS goes active), then the output pin will maintain the high impedance state throughout the entire cycle. Note that with this type of output configuration, the user is given full control of the DOUT pin simply by controlling the placement of ~ command during a write cycle, and the pulse width of the Column Address Strobe during read operations. Note also that even through data is not latched at the output, data can remain valid from access time until the beginning of a subsequent cycle without paying any penalty in overall memory cycle time (stretching the cycle). This type of output operation results in some very significant system implications. Common /O Operation - f all write operations are handled in the "early write" mode, then DN can be connected dorectly to DOUT for a common /O data bus. DOUT will remain valid during a read cycle from tcac until CAS goes back to a high level (precharge). allowing data to be valid from one cycle up until a new memory cycle begins with no penalty in cycle time. This also makes the RAS/CAS clock timing relationship very flexible. Two Methods of Chip Selection - Since DOUT is not latched, CAS is not required to turn off the outputs of unselected memory devices in a matrix. This means that both CAS and/or RAS can be decoded for chip selection. f both RAS and CAS are decoded, then a two dimensional (X, Y) chip select array can be realized. Extended Page Boundary - Page-mode operation allows for successive memory cycles at multiple column locations of the same row address. By decoding CAS as a page cycle select signal, the page boundary can be extended beyond the 28 column location in a single chip. (See page-mode operation). OUTPUT NTERFACE CHARACTERSTCS The three state data output buffer presents the data output pin with a low impedance to V cc for a logic and a low impedance to V ss for a logic O. The effective resistance to V cc (logic state) is 420. maximum and 35. typically. The resistance to Vss (logic 0 state) is 95. maximum and 35. typically.the separate V cc pin allows the output buffer to be powered from the supply voltage of the logic to which the chip is interfaced. During battery standby operation, the V cc pin may have power removed without affecting the M 46 refresh operation. This allows all system logic except the RAS timing circuitry and the refresh address logic to be turned off during battery standby to conserve power. PAGE MODE O~ERATON The Page Mode" feature of the M 46 allows for successive memory operations at multiplie column locations of the same row address with increased speed without an increase in power. This is done by strobing the row address into the chip and maintaining the RAS signal at a logic 0 throughout all success-. ive memory cycles in which the row address is common. This "page-mode" of operation will not dissipat' the power associated with the negative going edge of RAS. Also, the time required for strobing in a new row address is eliminated, thereby decreasing the access and cycle times. The page boundary of a single M 46 is limited to the 28 column locations determined by all combinations of the 7 column address bits. However, in system applications which utilize more than data words, (more than one 6K memory block), the page boundary can be extended by using CAS' rather than RAS as the chip select signal. RAS is applied to all devices to latch the row address into each device and the CAS is decoded and serves as a page cycle select signal. Only those devices which receive both RAS and CAS signals will execute a read or write cycle. 264

254 M 48 resh of the dynamic cell matrix is accomplished by performing a memory cycle at each of the 28 addresses within each 2 millisecond time interval. Although any normal memory cycle will perform refresh operation, this function is most easily accomplished with "RAS-only" cycles. RAS-only esh results in a substantial reduction in operating power. This reduction in power is reflected in the ; 3 specification. ~ER CONSDERATONS t of the circuitry used in the M 46 is dynamic and most of the power drawn is the result of an ads strobe edge.conseguently, the dynamic power is primarily a function of operating frequency rather n active duty cycle. This current characteristic of the M 46 precludes inadverten burn out of the ice in the event that the clock inputs become shorted to ground due.to system malfunction. though no particular power supply noise restriction exists other than the supply voltages remain within specified tolerance limits, adequate decoupling should be provided to suppress high frequency noise ting from the transient current of the device. This insures optimum system performance and reility. Bulk. capacitance requirements are minimal since the M 46 draws very little steady state (DC) rent. system applications requiring lower power dissipations, the operating frequency (cycle rate) of the 46 can be reduced and the (guaranteed maximum) average power dissipation of the device will be. ered in accordance with the DDl (max) spec limit equation. lote : ~ ~ r. The M 46-4 is guaranteed to have a maximum DDl requirement of ns cycle with an ambient temperature range from 0 to 70 C. A lower operating frequency, for example microsecond cycle, results in a reduced maximum DDl requirement of under 20 ma with an ambient temperature range from 0 to 70 C. ~thou9h RAS and/or CAS can be decoded and used as a chip select signal for the M 46 overall sys!em power is minimized if the Row Address Strobe (RAS) is used for this purpose. All unselected devices ljh~se which do not receive a RAS) will remain in a low power (standby) mode regardless of the state _CAS". k>wer UP h,e M 46 requires no particular power supply sequencing so long as the Absolute Maximum Rating ~ditions are observed. However, in order to insure compliance with the Absolute Maximum Ratings, ~S-ATES recommends sequencing of power supplies such that V BB is applied first and removed last. 'BB should never be more positive than Vss when power is applied to V DD. Jnder system failure conditions in which one or more supplies exceed the specified limits significant adlitional margin against catastrophic device failure may be achieved by forcing RAS and CAS to the inacive state (high level). ~fter power is applied to be device, the M 46 requires several cycles before proper device operation is Chieved. Any 8 cycles which perform refresh are adequate for this purpose. 265

255 NTEGRATED CRCUT M PRELMNARY DATA T READ ONLY MEMORY 8K x 8 ORGANZATON - EDGE ENABLED OPERATON (CE) 250 ns ACCESS TME, 375 ns CYCLE TME FOR M ns ACCESS TME, 450 ns CYCLE TME FOR M NGLE +5V ±.0% POWER SUPPLY. LOW POWER DSSPATON: 220 mw MAX ACTVE. LOW STANDBY POWER DSSPATON: 35 mw MAX (CE HGH) ON CHP LATCHES FOR ADDRESSES (CONTROLLED BY CE NPUT) NPUTS AND THREE-STATE OUTPUTS - TTL COMPATBLE OUTPUT DRVE 2 TTL LOADS AND 00 pf STANDARD 24 PN DP (EPROM PN OUT COMPATBLE) M36000 is a N--channel silicon gate MOS Read Only Memory, organized as 892 words by 8 bits. device incorporates advanced circuit techniques designed to provide maximum circuit density and lity with the highest possible performance, while maintaining low power dissipation and wide ng margins. The M36000 utilizes a static storage cell with clocked control periphery which allows circuit to be put into an automatic low power standby mode. This is accomplished by maintaining chip enable (CE) input at a TTL high level. n this mode, power dissipation is reduced to typically mw, as compared to unclocked devices which draw full power continuously. n system operation, a is selected by the CE input, while all others are in a low power mode, reducing the overall system The edge enabled operation means greater system flexibility and an increase in system speed, this device ideally suited for 8 bit microprocessor systems such as those which utilize the Z80. offer significant cost advantages over PROM. The M36000 is available in 24-lead dual in-line or ceramic package. LUTE MAXMUM RATNGS* Voltage on any pin with respect to Ground Total power dissipation Storage temperature: for ceramic package for plastic package Operating temperature - to +7 V W -65 to + 50 c -55 to + 25 o to +70 c c Stresses greater than those listed under "Ab~olute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating conditions of this specification is not implied. Exposure to absolute maximum rating con~ ditions for extended periods may affect device reliability. ~DERNG NUMBERS: M Bl M M Fl M Bl M Dl M Fl for dual in-line plastic package for dual in-line ceramic package for dual in-line ceramic package, frit-seal for dual in-line plastic package for dual in-line ceramic package for dual in-line ceramic package, frit-seal 267 6/79

256 -~--- M MECHANCAL DATA (dimensions in mm) Dual in-line plastic package ~ ~.3 Dual in-line ceramic package 5 ~ f~ 5.24 C-0093 Dual in-line ceramic package, frit-seal 336~' c::::::::: CONNECTON DAGRAM A, 24 'icc BLOCK DAGRAM 00 0, 0, 0, 0< 0,! 0, 0 AS 23 AS A" AS 22 A9 A" A" 2 A2.. A3 CE AS A2 A0 A A" ".. "",,--Vcc.NO AO 0, AS -- DO Os , O2 04 &5536 B" CELL MAT~X CHP ENABLE BUFFER &CLOCK GND 03 AO

257 M38000 ~COMMENDED DC OPERATNG CONDTONS(T amb =Oto 7CJ' e unless otherwise specified ~. Values Parameter Test conditions Unit Min. Typ. Max..CC Supply voltage V ~H nput high voltage 2 Vcc V H_ nput low voltage V ~ATC ELECTRCAL CHARACTERSTCSl (T amb = 0 to 70 0 e unless otherwise specified) ~ Values k Parameter Test conditions Unit Min. Typ. Max. ~OH Output high voltage OH~ -220 /la 2.4 V ~OL Output low voltage OL~ 3.3 ma 0.4 V "- nput lea kage current V~Ot05.5V -0 0 /la t..o Output leakage current Device unselected; Vo~ 0 to 5.5V -0 0 /la fec Supply current (active)2 40 ma 'icc2 Supply current (standby) CE high 8 ma.' ~ ~. ~:~, f h-namc ELECTRCAL CHARACTERSTCSl (Tamb = 0 to 70 0 e unless otherwise specified), ~. M M ~: Parameter Test conditions Unit. Min. Max. Min. Max. :tc Cycle time ns Output load ~ 2 TTL gate 'tee CE pulse width and 00 pf ns transition times = 20 ns t:tac CE access time ns ~!off Output turn off delay ns ~AH Address hold time ns ~S Address setup time 0 0 ns lip T precharge time ns Otes: ~,A minimum 00 /ls time delay is required after the application of VCC (+5V) before prop ex device operation is ~ achieved. CE must be at VH for this time period. ~Current is proportional to cycle rate. CC is measured at the specified minimum cycle time. 269

258

259 nformation furnished is believed to.be accurate and reliable. However, no responsibility is assumed for the consequences of its use nor for an infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-ATES. This publication supersedes and substitutes all information previously supplied. SGS - AlES GROUP OF COMPANES taly - France - Germany - Singapore - Sweden - United Kingdom - U.S.A. SGS-ATES Componenti Elettronici SpA, 979- Printed in taly Garzan!i s.p.a. - Cernusco s.ln.