MC33PF8100, MC33PF8200

Transcription

1 Rev. 1 4 October 2018 Errata sheet Document information Information Keywords Abstract Content MC33PF8100, MC33PF8200 This errata sheet describes both the known functional problems and any deviations from the electrical specifications known at the release date of this document. Each deviation is assigned a number and its history is tracked in a table.

2 Table 1. Revision history Rev Date Description Initial release, including E20 to E29 All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. 2 / 16

3 1 Product identification This errata document applies to PF8100 and PF8200 identified in the following table. Table 2. Revision overview table Revision ID Part number Die ID Package Device marking B0 B0 MC33PF8100xxES (xx represents all OTP versions of this device) MC33PF8200xxES (xx represents all OTP versions of this device) N59W 56 pin 8 x 8 mm QFN (F) MC33PF 8100xxES AWLYWZ N59W 56 pin 8 x 8 mm QFN (F) MC33PF 8200xxES AWLYWZ 1.1 Device build information / date code The marked trace code is the link between the physically marked materials and the manufacturing lot s system genealogy information. Once the connection between the marked material and system genealogy information is made, traceability reports provide the material s manufacturing/shipping history. All devices listed in the errata sheet are affected unless specific date codes are provided. All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. 3 / 16

4 2 Errata overview Table 3. Errata summary table Erratum ID Short description Severity level [1][2][3][4] ER020 LDOs detecting an OV condition when changing set point Work-around Product version(s) Detailed description Low Yes B0 Section 3.1 ER021 VSELECT incorrect set point. Medium Yes B0 Section 3.2 ER022 VTT discharge during power down sequence Low Yes B0 Section 3.3 ER023 ER024 XFAIL causes Dual PMIC to cycle ON/OFF when WDI event is present. SW1 to SW6 PFM/APS efficiency at low current is lower than expected. Medium Yes B0 Section 3.4 Low No B0 Section 3.5 ER025 PFM Accuracy is up to 30 mv off from target voltage. Medium No B0 Section 3.6 ER026 LDO_LS ilim interrupt setting late or not at all. Low No B0 Section 3.7 ER027 ER028 ER029 LDO1 incorrect output voltage during Hardwire configuration. Switching regulator output ripple in multi-phase APS mode Unexpected OV detection at voltage transition in PFM mode Low No B0 Section 3.8 Medium No B0 Section 3.9 Low Yes B0 Section 3.10 [1] High: Failure mode that severely inhibits the use of the device for all or a majority of intended applications [2] Medium: Failure mode that might restrict or limit the use of the device for all or a majority of intended applications [3] Low: Unexpected behavior that does not cause significant problems for the intended applications of the device [4] Enhancement: Improvement made to the device due to previously found issues on the design All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. 4 / 16

5 3 Functional problems detail 3.1 ER020: LDOs detecting an OV condition when changing set point Severity level Low Problem When an LDO is requested to change the output voltage from one voltage to a lower voltage level, the fault monitoring may detect an OV condition Root cause Root cause and solution have been identified. When an LDO is changing from one voltage to a lower voltage level, the output does not have a defined discharge path and it will float as much as the output load allows it until it reaches the final regulation voltage. In this scenario, if the load is not strong enough, it will float slowly causing the internal OV/UV blanking timer to expire and hence detecting an OV event. B0 UPDATE: On B0 silicon, the digital implementation improved this behavior by keeping the OV detection masked and using an internal pull down resistor to force the output low until the output has crossed the OV detection threshold. When this happens, the control logic enables the OV detection and removes the pull down resistor. However, when the discharge resistor is removed, the output voltage would bounce slightly back due to the output capacitance, causing the OV threshold to detect an OV event only if the output current is less than 60 to100 μa Work-around If the LDO is expected to change during the System On states, set the corresponding LDOx_OV_BYPASS bit to 1 in order to avoid the transition from detecting the OV condition. If the corresponding LDO is expected to notify the power good state via the PGOOD pin, the corresponding PG_EN bit should be set to 0 before requesting the new voltage on the LDO and then it can be set back to 1 after the output has reached regulation. This will eliminate any glitch on the PGOOD pin during the voltage transition. In both cases, the bits can be permanently changed if the feature is not needed, or can be disabled only during the transition and set back to the desired operating mode after the output voltage has reached regulation. B0 UPDATE: In addition to the workarounds mentioned above, this condition can be eliminated if the LDO has a loading current above 60 μa during the transition from high to low voltage Fix plan To be fixed in a future release of this product. All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. 5 / 16

6 3.2 ER021: VSELECT incorrect set point Severity level Medium Problem LDO2 sets the incorrect output when it is controlled by the VSELECT pin. When VSELECT is enabled and the pin is set high, the LDO2 Output is set to 1.6 V instead of 1.8 V as specified in the device data sheet Root cause Root cause and solution have been identified. The LDO output configuration set points was updated to add support for 1.6 V set point. When the configuration set point got rearranged, the RTL code did not update to the new code that sets the 1.8 V output voltage Work-around If the LDO2 output is required to change from one voltage to another, it is recommended to disable the VSELECT control and used the I2C command to set the output voltage to the correct voltage manually Fix plan To be fixed on a future release of this product. All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. 6 / 16

7 3.3 ER022: VTT discharge during power down sequence Severity level Low Problem When the SW6 is set to VTT mode, and it is turned on at a later slot than SW5, if the part starts a power down event, the SW6 will discharge slowly following the VTT pull down configuration instead of forcing a DVS ramp down to 0 V Root cause Root cause and solution have been identified. Design implementation recognizes the scenario where SW6 disabling first in the power down sequence as if it was still in normal mode and VTT (SW6) needs to be in High-Z or passive pull-down Work-around Always keep SW5 and SW6 in the same power up slot when the VTT mode is enabled Fix plan To be fixed on a future release of this product. All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. 7 / 16

8 3.4 ER023: XFAILB causing a cyclic failure when WDI asserted Severity level Medium Problem When two PMICs are connected together and the XFAILB is used to synchronize both PMICs, and when a WDI hard watchdog event occurs in both PMICs at the same time, the XFAILB could potentially get desynchronized and one of the devices may cycle in a power up / power down cycle Root cause The root cause has been understood and a solution identified. The state machine cycle in a loop when it detects an XFAILB pulled low externally right before the WDI request the XFAILB to be pulled-low internally. There is an internal signal to flag an external XFAILB event and a similar signal to flag an internal XFAILB event. The state machine will remember each one of the events and release its corresponding flag when it is processed. Unfortunately, the external XFAILB event is processed during the power up sequence, leading the state machine in to a PWRUP failure cycle, which means the internal XFAILB flag could not be released, causing an endless loop Work-around 1. Connect the Watchdog output from the i.mx processor to the Master PMIC only, and leave the WDI pin of the slave PMIC disconnected. 2. Or, prevent the WDI to generate a Hard WD reset in the system. 3. If the system requires a Soft WD reset when the WDI pin is asserted, then both WDI pins can be connected together to the MCU's Watchdog output Fix plan To be fixed in a future release of this product. All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. 8 / 16

9 3.5 ER024: SW1 to SW6 PFM/APS efficiency failing Severity level Low Problem During APS and PFM mode operation, the output efficiency at low currents is lower than expected Root cause Root cause and solution have been identified. When the switching regulators are operating in the PFM feedback loop, there is a false zero crossing detection being triggered during the low current operation. When the Zero Crossing detection is triggered, the LS-Fet is disabled and the inductor current is discharged through the reverse body diode, causing a large drop and hence the efficiency gets impacted at low currents Work-around No workaround to improve efficiency in low current operation. If low power conditions are not a concern, it is recommended to operate the device in PWM mode Fix plan To be fixed in a future release of this product. All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. 9 / 16

10 3.6 ER025: PFM Accuracy is out of spec Severity level Medium Problem When any of the SW regulators are set in PFM mode, the output accuracy may be shifted up to 30 mv causing the output to fall outside of the expected accuracy range Root cause The root cause has been understood and a solution identified. The closed loop during PFM operation is not properly compensated, thus causing the DC offset on the output voltage when the system switches between modes Work-around Use the regulator in PWM mode to ensure the output is kept within the output accuracy specification Fix plan To be fixed in a future release of this product. All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. 10 / 16

11 3.7 ER026: LDO_LS ilim interrupt setting late or not at all Severity level Low Problem When the LDO is set in Load Switch operation, the protection circuit may start limiting the current at a level higher than the ILIM specification. In some scenarios, where the current approaches this threshold gradually, the LDO output may fold back and start an oscillation trying to fully engage the current limit behavior. When this happens, the ILIM interrupt flag may be set late if the circuit managed to fully enter the ILIM state, or it may not set at all if the condition is not strong enough to cause the ILIM circuit to be engaged Root cause The root cause has been understood and a solution identified. The ILIM flag is set when the current reaches the OCP threshold which in regulation mode is the same or less than the ILIM threshold; in this mode, the issue is not visible. However, in Load Switch mode the OCP threshold is much higher than the ILIM threshold, causing the circuit to require a higher current before it starts protecting the output and fold back the output current to the ILIM level and set the ILIM interrupt flag. In this specific scenario, when the circuit is working in the voltage drop-off condition (as a switch), the circuit tries to start the ILIM protection circuit gradually which in turns lowers the current, preventing the LDO from reaching the OCP and hence not setting the flag properly. This condition occurs when the current is increased gradually, and will not occur if the overcurrent is due to a short circuit, or a current step high enough to cross the OCP threshold right away Work-around There is no specific workaround to eliminate this condition. If the LDO is used in Load Switch mode, ensure the system does not exceed the nominal current rating. This will ensure the output voltage drop due to the FET RDSON is kept within a reasonable level. If higher currents are expected on the respective LDO, do not rely on the LDOxILIM_I flag to notify the over current condition Fix plan To be fixed in a future release of this product. All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. 11 / 16

12 3.8 ER027: LDO1 incorrect output voltage during Hardwire configuration Severity level Low Problem When the device is operating in Hardwire configuration, LDO1 turns on at 1.6 V instead of 1.8 V as specified on the device data sheet Root cause Root cause and solution have been identified. The LDO output configuration set points were updated to add support for 1.6 V set point. When the configuration set point got rearranged, the RTL code did not update to the new code that sets the 1.8 V output voltage when the Hardwire configuration is selected Work-around Avoid using the Hardwire configuration as the final solution in the system Fix plan To be fixed in a future release of this product. All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. 12 / 16

13 3.9 ER028: Switching regulator output ripple in multi-phase APS mode Severity level Medium Problem Type 1 switching regulators output has a voltage ripple around 25 mv when they are set in multi-phase Auto Pulse Skip mode and operated in Continuous Conduction mode Root cause Root cause and solution have been identified. The Zero Crossing detection circuit is generating incorrect detection of zero crossing while the device is still in CCD mode. This causes the system to skip random pulses and trying to compensate in the next switching cycle causing the overvoltage at the output Work-around Do not use APS mode Fix plan To be fixed in a future release of this product. All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. 13 / 16

14 3.10 ER029: Unexpected OV detection at voltage transition in PFM mode Severity level Low Problem OV fault is detected when type 1 switching regulators output is changed to low voltage in PFM mode with less than 7 % OV threshold and no current load. The issue was observed when the voltage was changed from 1.5 V to 0.6 V Root cause Root cause and solution have been identified. OV voltage threshold is too tight at low voltage in PFM mode Work-around Use more than 9 % OV threshold for output voltage less than 0.6 V in PFM mode Fix plan To be fixed in a future release of this product. All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. 14 / 16

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16 Contents 1 Product identification Device build information / date code Errata overview Functional problems detail ER020: LDOs detecting an OV condition when changing set point Severity level Problem Root cause Work-around Fix plan ER021: VSELECT incorrect set point Severity level Problem Root cause Work-around Fix plan ER022: VTT discharge during power down sequence Severity level Problem Root cause Work-around Fix plan ER023: XFAILB causing a cyclic failure when WDI asserted Severity level Problem Root cause Work-around Fix plan ER024: SW1 to SW6 PFM/APS efficiency failing Severity level Problem Root cause Work-around Fix plan ER025: PFM Accuracy is out of spec Severity level Problem Root cause Work-around Fix plan ER026: LDO_LS ilim interrupt setting late or not at all Severity level Problem Root cause Work-around Fix plan ER027: LDO1 incorrect output voltage during Hardwire configuration Severity level Problem Root cause Work-around Fix plan ER028: Switching regulator output ripple in multi-phase APS mode Severity level Problem Root cause Work-around Fix plan ER029: Unexpected OV detection at voltage transition in PFM mode Severity level Problem Root cause Work-around Fix plan Legal information...15 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. NXP B.V All rights reserved. For more information, please visit: For sales office addresses, please send an to: salesaddresses@nxp.com Date of release: 4 October 2018 Document identifier: