Gen 2 SiC MOSFETs Extends the Benefits of Silicon Carbide in Industrial Applications

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1 Gen 2 SiC MOSFETs Extends the Benefits of Silicon Carbide in Industrial Applications Dr. Vladimir Scarpa, Salvatore La Mantia Michele Macauda, Luigi Abbatelli December 4 th 2018

2 Contents 2 Silicon Carbide at STMicroelectronics SiC MOSFET - Technology roadmap Gen 2 SiC MOS Technology STGAP2S Isolated Gate Driver Practical Example

3 Contents 3 Silicon Carbide at STMicroelectronics SiC MOSFET - Technology roadmap Gen 2 SiC MOS Technology STGAP2S Isolated Gate Driver Practical Example

4 20 Years of ST SiC History 4 April st contract on SiC with CNR-IMETEM (Dr. V. Raineri) November 2003 First ST internal product request May 2004 Schottky Diode Demonstrator (ST line) March 2009 Power MOSFET 3" Demonstrator September st Gen MOSFET Start Production June 1996 Collaboration with Physics Dept. (Prof. G. Foti) February 2003 ETC Epitaxial reactor prototype installed in ST May 2002 Schottky Diode Demonstrator (CNR line) December 2005 Schottky Diode Mat 20 October st Gen Diode Start Production May nd Gen Diode Start Production September kV Diode Start June 2014 Production 3 rd Gen 3 Diode Start Production June nd Gen MOSFET AG 6" Start Production June " ST line June " ST line June " ST line June " ST line Pioneers.....to mass production

5 ST SiC Manufacturing 5 Normalized to capacity in Silicon Carbide manufacturing line growth % 235% 285% 335% 375% 100%

6 Contents 6 Silicon Carbide at STMicroelectronics SiC MOSFET - Technology roadmap Gen 2 SiC MOS Technology STGAP2S Isolated Gate Driver Practical Example

7 SiC MOSFET Technology RoadMAP 7 From Planar to Trench -44% -28% -30% In Production New! In Development 20V 18V 18V 15V

8 SiC MOSFET Benchmark Parameter: R DS,ON x Area 8 Gen1 (2014) Gen2 (2018) Comp. 1 Comp.2 Gen3 (2020+) Trench technology Comp. 3 ST Gen2 as good as today s Trench MOSFETs

9 Contents 9 Silicon Carbide at STMicroelectronics SiC MOSFET - Technology roadmap Gen 2 SiC MOS Technology STGAP2S Isolated Gate Driver Practical Example

10 V DS [V] 650 R DS (on) 18V, 25ºC [mω] SiC MOSFET Gen 2 Planned Portfolio Id Package P/N HiP247 H2PAK-7 HiP247-4L H2PAK-7 HiP247 Bare die SCTW90N65G2V SCTH90N65G2V-7 SCTW90N65G2V-4 SCTH100N65G2-7AG SCTW100N65G2AG SCT100N65G2D2AG Automotive Grade Packages T j.max =200 C H2PAK-7 SCTH35N65G2V-7AG HiP247 H2PAK-7 HiP247-4 HiP247 H2PAK-7 H2PAK-7 HiP247 dice HiP247 H2PAK-7 H2PAK-7 HiP247 V DS [V] R DS 25ºC [mω] SCTW35N65G2V SCTH35N65G2V-7 SCTW35N65G2V-4 SCTW70N120G2V SCTW70N120G2V-4 SCTH70N120G2V-7 SCTH100N120G2-AG SCTW100N120G2AG SCT100N120G2D2AG SCTW40N120G2V SCTH40N120G2V-7 SCTH40N120G2V7AG SCTW40N120G2VAG Id P/N HiP-247 (STD & LL) TM SMD H2PAK 2 and 7 leads Kelvin Source + T j.max =200 C SCTW35N65G2V SCTW90N65G2V SCTW70N120G2V-4

11 SiC MOSFETs Qualification Status 11 Same qualification path than Silicon parts; Temperature increased to T j =200 C for HiP247 Package

12 Advantages Static Parameters Low temperature dependency of R ds,on V Devices 650V/900V Devices Up to 200 C! Up to 200 C! Lowest temperature dependancy among SiC MOSFETs in the market; Lower risk of thermal runaway even at very high temperature operation.

13 Relevant Parameters for Safe Gate Driving 1) Miller Capacitance SCTW90N65G2V 13 C rss =C GD C iss =C GS //C GD C GS C oss =C GD //C DS Weak capacitive coupling through Miller Capacitance. Low risk of parasitic turn-on. Operation inside SOA, no gate oxyde degradation.

14 Relevant Parameters for Safe Gate Driving 2) Gate Voltage SOA V gs+,max +25V +20V V gs+,op Gen 1 Gen 2 +22V +18V 14 V gs-,op V gs-,min -5V -5V -10V -10V Wide negative range. Flexibility in design. Low risk of parasitic turn-on.

15 Contents 15 Silicon Carbide at STMicroelectronics SiC MOSFET - Technology roadmap Gen 2 SiC MOS Technology STGAP2S Isolated Gate Driver Practical Example

16 STGAP2S V, 4A gate drivers Up to 26 V supply voltage Miller CLAMP pin option Propagation delay < 100 ns CMTI > 100V/ns Galvanic isolation 1.7 kv in SO-8 package 6 kv in SO-8W package SO-8N SO-8W In Production 2019

17 120 V/ns 129 V/ns test vehicle: EVALSTGAP2SCM STGAP2S CMTI test 17 Test equipment DPO 7104C 1 GHz Oscilloscope IsoVu 1 GHz isolated differential probe 4 kv single-ended probe with GND clip DC linear power supply (+1500 V) GNDISO vs GND GON-GOFF vs GNDISO

18 1700 V, 4A gate drivers In Production STGAP2S 8 Recommended for SiC MOSFETs Option 1: Single output and Miller CLAMP Option 2: Separated sink\source outputs

19 Effectiveness of Active Miller Clamp Tests in a Half-Bridge Inverter 19 Circuit block diagram Expected Waveforms in LS Switch Assuming positive current Gate driver S1 FILTER V ds S2 V ds S1 V ds S2 V IN I C -CURRENT PROBE Gate driver S2 V DS VOLTAGE PROBE V OUT =110V AC Dead-time V gs S2 Device V GS - VOLTAGE PROBE Description V gs S1 V gs S1 S1 & S2 SCTW35N65G2V (55 mω, 650 V SiC MOS) Gate Driver STGAP2S, in both versions AMC and SO Risk of Parasitic turn-on. Operation outside SOA.

20 SCTW35N65G2V 55 mω, 650 V SiC MOSFET Active Miller Clamp Positive Glitch Negative Glitch Vgs with S-OUT Vgs with AMC Vgs off with AMC Vgs off with S-OUT Vgs [V] 5 0 Vgs [V] ,11E-05 2,13E-05 2,15E-05 2,17E-05 2,19E-05 2,21E-05 Time [sec] -15 1,96E-05 1,97E-05 1,98E-05 1,99E-05 2,00E-05 2,01E-05 2,02E-05 2,03E-05 Time [sec] Legend of driver configuration S-Out: separated output AMC: Active Miller Clamp Vgs-on=+18V Vgs-off= -5V

21 SCTW35N65G2V 70 mω, 650 V SiC MOSFET Negative Deactivation Voltage 21 Negative Glitch Positive Glitch Vgs_off=-5V 15 Vgs_off=-2.5V 10 Vgs_off=-2.5V Vgs_off=0V 10 Vgs_off=-5V Vgs_off=0V Vgs [V] 5 0 Vgs [V] ,94E-05 1,96E-05 1,98E-05 2,00E-05 2,02E-05 2,04E ,96E-05 1,97E-05 1,98E-05 1,99E-05 2,00E-05 2,01E-05 2,02E-05 2,03E-05 2,04E-05 2,05E-05 Time [sec] Time [sec]

22 Contents 22 Silicon Carbide at STMicroelectronics SiC MOSFET - Technology roadmap Gen 2 SiC MOS Technology STGAP2S Isolated Gate Driver Practical Example

23 Application Example DC Chargers for Electrical Vehicles 23 Parameter Symbol Value Input voltage V in 230V ac Ph-N 400V ac ph-ph Max. Input Current I in.max 32A/ph Max Power P in.max 7.36 kw/ph 22 kw total DC Link Voltage V DC Vdc Output Voltage V out Vdc Configuration Device R Tj=25 C Package Number in parallel Conf. 1 SCT50N V gs =20V HiP247 2x Conf. 2 SCTW70N120G2V-4 25 V gs =18V TO (Kelvin Source) 1x

24 Comparison on Device Level 24 Parameter Conditions SCT50N120 (x2) SCTW70N120G2V-4 R ds,on V gs = V g,op, I d =I d,nom, T j =25 C 52 mω (26 mω) 25 mω R th,j-c K/W (0.27 K/W) 0.45 K/W R th,c-h --- ~ 1 K/W (~0.5 K/W) ~ 1K/W Dynamic Improvements must compensate thermal disadvantages of Conf. 2! Parameter Conditions SCT50N120 (x2) SCTW70N120G2V-4 C iss Conf. 1 Conf pf (3800 pf) 3500 pf C oss Vds= 800V, Vgs=0, f=1mhz 170 pf (340 pf) 180 pf C rss 30 pf (60 pf) 30 pf

25 Experimental Results Comparison Gen 1 vs. Gen 2 SiC MOS 25 +2% R g,on = R g,off =3 Ω Parameter Advantages on System Level Gain Amount of switch devices 50% less Heat-sink size 40% smaller PCB area 26% smaller Commutation loop size 43% smaller

26 Summary 26 Gen 2 SiC MOSFETs Based on planar structure, Gen 2 is a large improvement step in SiC MOSFET technology. Product portfolio includes 650V and 1200V voltage classes, with very low R ds,on and innovative packages, like TO-247 4pin and D2PAK 7pin. The combination of low Miller capacitance and extended negative gate voltage range enables fast and safe commutation. Results in EV charger demonstrates the possibility to build up systems above 20 kw without the need of paralleling devices.

27 New! STPower TM 27

28 28 Thank you! Questions?

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