Synthesis of Ultra-High Gain Operational Transconductance Amplifiers Using a Generalized Controller-Based Compensation Method

Transcription

1 Synthesis of Ultra-High Gain Operational Transconductance Amplifiers Using a Generalized Controller-Based Compensation Method Ming Yang Department of Electrical and Computer Engineering McGill University, Montréal December, 2015 A thesis submitted to the Faculty of Graduate Studies and Research in partial fulfillment of the requirements of the degree of Master of Engineering. Copyright Ming Yang 2015.

2 Abstract This thesis presents a method that can be used to create operational transconductance amplifiers (OTAs), or their many related constructs such as operational amplifiers, with extremely high DC voltage gains levels previously deemed unachievable due to stability concerns. The principle is based on the cascade of integrators to realize large DC gains and a controller to stabilize its operation in a closed-loop configuration. With K-integrators in cascade, the DC gain approaches levels described by (gmro) 2K V/V with a frequency response involving K co-incident poles having a frequency roll-off of -20K db/decade. With the addition of the controller, the order N of the OTA is simply one order higher than the number of integrators in cascade, i.e., N=K+1. Collectively, this arrangement of gain stages provides an extremely high DC voltage gain but also a larger 3-dB bandwidth than its predecessors resulting in improved closed-loop negative feedback properties. To demonstrate the design principles and the proposed topology, a programmable OTA was fabricated in the IBM 130 nm CMOS process that could be programmed to realize orders ranging from 2 to 5. Measure data reveals DC gains ranging from 50 db to 150 db with a 3-dB bandwidth of 10 khz and a unity gain frequency of 10 MHz. Operation in a unity-gain configuration demonstrate the accuracy of the synthesis method as defined by its Euclidean distance from its desired transfer function. While this thesis demonstrates the design principles using CMOS integrated circuits, the principles are general and can be applied to any type of circuit technology such as integrated or discrete implementations. Moreover, the methods are easily automated as the principles are based on closed-form formulae as opposed to iterative numerical search techniques.

3 Résumé Cette thèse présente une méthode pouvant être utilisée pour concevoir des amplificateurs opérationnels de transconductance (OTAs), ou autres designs semblables, tels que les amplificateurs opérationnels dont le gain en tension continue est tellement élevé, que ces designs étaient auparavant considérés comme irréalisables pour des raisons de stabilité. Ce concept de topologie consiste en une cascade d intégrateurs, pour réaliser l important gain en tension continue, ainsi qu en un régulateur, pour stabiliser son fonctionnement en boucle fermée. Avec K intégrateurs en cascade, le gain en tension continue approche le comportement décrit par (gmro) 2K V/V avec une réponse fréquentielle comprenant des pôles coïncidents et une atténuation de -20K db/decade. Avec l ajout d un régulateur, l ordre N de l OTA est simplement d un ordre supérieur au nombre d intégrateurs en cascade, tel que N=K+1. Cette configuration d étages amplificateurs permet non seulement un gain en tension continue extrêmement élevé, mais aussi une bande passante à -3 db plus large que celles de ses prédécesseurs, résultant en une amélioration des propriétés du comportement en boucle fermée à rétroaction négative. Afin de démontrer les principes de ce design ainsi que la topologie proposée, un OTA programmable a été fabriqué selon le procédé de fabrication de CMOS de 130 nm d IBM. Cet OTA peut être programmé afin de faire varier son ordre de 2 à 5. Les mesures donnent un gain en tension continue variant de 50 à 150 db avec une bande passante à -3 db de 10 khz et une fréquence à gain unitaire de 10 MHz. Le comportement en boucle à gain unitaire atteste de la précision de la méthode de synthèse, définie par la distance euclidienne entre la fonction de transfert voulue et celle obtenue. Bien que cette thèse démontre les principes de ce design avec des circuits intégrés de CMOS, les principes sont généraux et peuvent s appliquer à tout types de technologies de circuits, telles que les implémentations intégrées ou discrètes. De plus, les méthodes peuvent être facilement automatisées car ces principes sont basés sur des formules analytiques et non sur des techniques de recherche itérative.

4 Acknowledgements Upon the completion of my master study, I am grateful for having the opportunity to work with Professor Gordon Roberts as one of his students. I owe a debt of thanks to Professor Roberts, who brought me into this fascinating integrated circuit world and consistently devoted his wisdom and patience in supervising this thesis work over the past two years. I would like to express my sincere gratitude to all my fellows in the Integrated Microsystem Laboratory at McGill University, and I feel lucky to be surrounded by the talents and skills from every one of you. I will never forget the support from Steven Bielby on microsystem design and PCB fabrication, the assistance from Steven Ding on PCB assembly, and numerous insightful advices from my fellows Dong An, Adam Gordon, Omar Abdelfattah, and Moataz Abdelfattah. I would also like to recognize the generous support from Lola Damski on translating part of this thesis. My accomplishments would not have been possible without the dedicated support from my lovely parents and friends. I want to say thank you to all my friends, particularly to Kevin Han, Tracy Lee, Zhiyuan Huang, Xiaoqi Wang, Nan Li, Siyu Wang, Yueze Lu and Xinyu Liu, who have been always there with me through thick and thin.

5 Contents Chapter 1 Introduction Thesis Background State of the Arts Scope of Thesis Thesis Outline... 4 Chapter 2 Background Canonical-Type State-Space Representation of a Linear System Gaussian Transfer Function Operational Amplifier and OTA Operational Amplifier Operational Transconductance Amplifier Closed-Loop Operation of Operational Amplifier Unity-Gain Follower Unity-Gain Resistive Feedback D-Type Flip-Flop Summary Chapter 3 System-Level Synthesis of OTA OTA Transfer Function Synthesis Controller-Based Compensation Method State-Space Realization of OTA Synthesis and Realization of Gaussian Transfer Function Implementation of the 1/s Integrator Small-Signal Properties of the OTA Evaluation of OTA Frequency Response Verification of OTA Frequency Response Using Spice Bandwidth, Impedance and Dynamic Range Scaling Bandwidth and Impedance Scaling Dynamic Range Scaling OTA Robustness and Calibration OTA Sensitivity Analysis OTA Stability Analysis Post-Manufacturing Calibration... 37

6 Contents 3.6 Summary Chapter 4 Design of Programmable OTA Prototype System-Level Implementation of Programmable OTA Unit-Sized Gm Cell Design D-Type Flip-Flop Design Analog Multiplexer Design Programmable Gm Cell Design Two-Input Miller-C Integrator IC Floor Plan Open-Loop Frequency Operation Closed-Loop Unity-Gain Operation Summary Chapter 5 OTA Testing Setup Fabricated OTA Prototype Testing Circuitry Testing Circuitry for Unity-Gain Closed-Loop Measurement Testing Circuitry for Open-Loop DC Gain Measurement Merged Circuitry for DC and Closed-Loop Measurement Printed Circuit Board Design Testing Preparation PCB Assembly Test Bench Setup Summary Chapter 6 Experimental Results Small-Signal Step Response Large-Signal Step Response Closed-Loop Small-Signal Frequency Response Comparison with State-of-the-Art Summary Chapter 7 Conclusion Thesis Contribution Further Improvement... 74

7 Contents Appendix I...76 Closed-Loop Aggregate Sensitivity Metric Appendix II...78 Chip Bonding Diagram Appendix III...79 Chip Pinout Bibliography...80

8 List of Figures 2.1 Observable canonical realization of a transfer function Operational amplifier circuit model Operational transconductance amplifier circuit model OTA unity-gain follower configuration OTA closed-loop inverting configuration DFF symbol and its digital operation Block diagram of a 5 th -order ultra-high gain OTA Block diagram of a 5 th -order ultra-high gain OTA realized using an observable canonical state-space formulation Comparing the step response of a 5th-order Gaussian transfer function and its modified form Magnitude response of an ideal vs. non-ideal integrator operation Basic single-ended Gm-C integrators Two-input Miller-C integrator Normalized frequency response of the OTA in open-loop using ideal components Unit step response of the OTA in a unity gain configuration using ideal components Sensitivity analysis of an OTA in a unity-gain closed-loop configuration Schematic diagram of the 20-Gm programmable cell Schematic diagram of a fully programmable ultra-high gain OTA Schematic diagram of the fully differential unit-sized Gm cell SPICE simulation results for a unit-sized Gm cell with different control voltage Vctrl values Gate-level schematic design of the D-type flip-flop Gate-level schematic design of the analog multiplexer Transfer characteristic of the programmable Gm cell Frequency response behavior of a two-input Miller-C integrator with one input grounded Cadence layout view of the programmable amplifier in the IBM 130 nm technology...49

9 List of Figures 4.9 Frequency response of the open-loop programmable amplifier extracted from layout and compared to the ideal simulated result Fully differential unity-gain amplifier with resistive feedback Post-layout simulated normalized step response of the programmable amplifier Simulated closed-loop AC response of the amplifier in a unity-gain configuration for various OTA orders Die photo of the programmable OTA fabricated in IBM 130nm CMOS technology Pinout diagram of the programmable OTA packaged in CFP24A Fully-differential servo-loop testing circuitry for DC gain measurement Customized testing circuitry for DC gain and closed-loop measurement Printed circuit board design for DC gain and closed-loop measurement Assembled printed circuit board for DC gain and closed-loop measurement Photograph of the test bench setup Measured small-signal step response of the programmable OTA in a unity-gain configuration to a 20 mv step input for various orders Measured large-signal step response of all four OTA orders before and after excessive ringing occurs at its output A comparison between the measured vs. simulated AC response of the amplifier in a unity-gain closed-loop configuration for various OTA orders Comparing the measured step response of a 4th-order OTA in a unity-gain configuration for two different pole-zero canonical type transfer functions...74 A.1 Bonding diagram of the fabricated ultra-high gain OTA...78

10 List of Tables 3.1 Denominator polynomial coefficients of a Gaussian transfer function Pole/zeros locations of the remainder function R(s) for different orders corresponding to a modified Gaussian transfer function Modified-Gaussian state-space coefficients scaled for maximum dynamic range Worst-case coefficient tolerances predicted by Kharitonov s method Unit-sized Gm cell transistor aspect ratios Programmable OTA coefficients for application in a resistive feedback unity-gain amplifier Integrator capacitor values Summary of OTA measured performance (without buffer) in comparison to other works Computer optimized transfer functions with reduced overshoot and pole-zero canonical transfer function...75 A.1 A comparison of the aggregate sensitivity measure of the various compensation methods described in this work under normalized-frequency conditions...77 A.2 Pin assignments of the packaged ultra-high gain OTA chip...79

11 Abbreviations OTA CMOS IC ADC DAC LHP VCVS VCCS DFF GBP RMS CM ESD CMC CFP DUT PCB SMA SOIC AC DC Operational Transconductance Amplifier Complementary Metal Oxide Semiconductor Integrated Circuit Analog-to-Digital Converters Digital-to-Analog Converters Left-Half Plane Voltage Controlled Voltage Source Voltage Controlled Current Source D-Type Flip-Flop Gain-Bandwidth Product Root Mean Square Common Mode Electrostatic Discharge Canadian Microelectronics Corporation Ceramic Flat Package Device Under Test Printed Circuit Board Subminiature Version A Small Outline Integrated Circuit Alternating Current Direct Current

12 To my dear parents.

13 Chapter 1 Introduction 1.1 Thesis Background Operational transconductance amplifiers (here in referred to as OTAs) are key building blocks for many types of signal processing algorithms realized in complementary metal oxide semiconductor (CMOS) integrated circuit (IC) technologies. Together with another known form as operational amplifiers, various applications can be found in signal amplification, rectifiers, regulators, analog-to-digital converters (ADC), digital-to-analog converters (DAC) and analog filters. The circuit operation with many of them usually requires a fairly high open-loop gain to meet demanding design specifications. Unfortunately, as transistor dimensions scale downwards with advancing technology developments, so too does their intrinsic voltage gain, which in turn, reduces the upper limit of the open-loop gain achievable by any OTA. This fact can be illustrated by the OTA small-signal intrinsic gain defined as gmro, where gm and ro are the transconductance and output resistance of OTA, respectively. Given the fact that output resistance scales down with deep submicron technology [1], the intrinsic gain, sometimes referred as the maximum gain an OTA could have without loading and parasitic effects, is further decreased as well. In low-voltage low-power applications, obtaining a high DC gain is the key challenge faced by many analog integrated circuit designers, as low-gain OTAs have an immediate impact on the absolute accuracy that the system can achieve. 1

14 Chapter 1. Introduction 2 Consider that any time domain specification is a combination of three factors: (1) overshoot, (2) settling time, and (3) steady-state error. While an ideal system constructed with infinite-gain OTAs can satisfy all three metrics simultaneously, a system constructed with low-gain OTAs cannot. For the most part, low-overshoot and fast settling time specifications may be met, but the final steadystate error will not be met. In essence, the system would fail its absolute accuracy requirements. As OTAs realized in advanced CMOS nodes have very low DC gain, high-performance systems constructed with these components will fail to meet their performance expectations. 1.2 State of the Arts As the analog CMOS circuit designer has been faced with this trend for over 30 years, several circuit techniques have been used to circumvent transistor gain reduction. One approach is the application of cascoding, the series stacking of transistors, one on top of the other, and another is the cascading of multiple single-stage amplifiers [2]. While multi-level cascoding [3] has been very successful when large voltage supply levels are available, it is less useful when voltage supplies drop below 2 V due to limited output signal swing the situation with CMOS technologies with transistor lengths less than 180 nm. Cascading, on the other hand, is much less sensitive to reductions in the voltage supply levels and more suitable to small-dimensional CMOS technologies. Cascading multiple stages together to achieve large DC gains is faced with stability issues when inserted into a negative-feedback loop arrangement, which would require frequency compensation to stabilize the loop. In the past, these frequency compensation techniques have been largely investigated for two-stage and three-stage OTAs. A commonly used stabilization approach for multi-stage amplifiers is to use a Miller (floating) capacitor between individual gain stages, thus creating a dominant pole behavior [4]. Many efforts have been underway trying to find a compensation scheme with high power efficiency [5]. Other compensation techniques, such as impedance adapting compensation [6], damping factor control [7] and feedforward compensation [8], can be combined with a Miller compensation approach to achieve excellent power efficiency and high-load capability. However, multi-stage amplifier designs usually lead to complicated and

15 Chapter 1. Introduction 3 non-systematic design procedures when three or more stages are placed in cascade, and thus only a few studies have been performed for four-stage OTAs [9-11]. Furthermore, compensation topology based on Miller compensation is not efficient both in power and area, as the capacitive load driving capability is directly proportional to the compensation capacitance [12]. In addition, the polesplitting effect created by Miller compensation significantly limits the gain-bandwidth product of the overall amplifier. To avoid this problem, a no-capacitor feedforward compensation topology was proposed in [13]. While the method is in principle extendable to N stages in cascade, only a two-stage prototype was ever built and verified again, a result, we believe is due to the cumbersome mathematics involved in the compensation procedure. 1.3 Scope of Thesis In this thesis, a more general approach is used to design the dynamic operation of the OTA for a feedback loop arrangement which leads to a stable, predictable closed-loop step response behavior that can meet the absolute accuracy requirements of high-performance analog systems. It begins by selecting the desired closed-loop transfer function and then synthesizing a controller-based compensation circuit that is placed in cascade or integrated alongside the numerous gain stages represented by ideal integrators. By doing so, very high gain and bandwidth OTA structures can be constructed so that it has a specific closed-loop behavior. The OTA open-loop response is not limited to a single-pole response and a phase margin objective, but rather one that provides the desired closed-loop response. By doing so, the complexity related to the compensation of a multistage cascaded amplifier is linearly proportional to the number of amplifier stages in cascade. The approach proposed here borrows from the well-known theory of active filter design and enables a systematic design method that can easily be automated and captured by a computer-aided design method. While any number of gain stages can be placed in cascade, sensitivities to process variations will ultimately limit this number to about five integrators equivalent to ten individual gain stages. Furthermore, post-manufacturing calibration techniques will be required to tune the OTA behavior against process variations.

16 Chapter 1. Introduction Thesis Outline This thesis begins by explaining the circuit theories required for the high-gain OTA synthesis in Chapter 2. The synthesis method, together with a system description of the building blocks will be given in Chapter 3. The small-signal properties, and some other properties related to dynamic range scaling and robustness of the OTA will be described in Chapter 3 as well. Subsequently, Chapter 4 will describe the design of programmable OTA structure whose order can vary between two and five. This chapter also illustrates the expected operation results both in open loop and closed-loop feedback arrangement. Chapter 5 will then describe its experimental setup for OTA testing, which includes designing a specified testing circuitry on a printed circuit board. Experimental results are reported and compared with the state-of-the-arts in Chapter 6. A conclusion and some discussion on methods to improve the proposed OTA synthesis method will be given in Chapter 7.

17 Chapter 2 Background This chapter will introduce some basic theories and building blocks demonstrated in the programmable OTA design. This include the state-space realization of a linear system, choice of high-order Gaussian transfer function, D flip-flop design, and fundamental amplifier theories required for both OTA design and verification. 2.1 Canonical-Type State-Space Representation of a Linear System In electrical and electronic engineering, a state-space representation is a synthesis method commonly applied in filter system designs. From a mathematical point of view, the state-space model is derived from a group of first-order differential equations and it provides a high-level abstraction on the input-output relationship defined by these differential equations. Controllable canonical realization and observable canonical realization are two typical statespace realizations for a given continuous-time linear time-invariant differential system. In this thesis work, the proposed programmable OTA structure is implemented from the observable canonical realization. To illustrate this process, one may start with an arbitrary Nth-order transfer function H(s) with the form H(s) = b Ms M +b M 1 s M 1 + +b 0 s N a N 1 s N 1 a 0 (2.1) To avoid losing generality, here all coefficients can take up either positive or negative values. Dividing both the numerator and denominator polynomials in Equation 2.1 by s N, we have 5

18 Chapter 2. Background 6 H(s) = b Ms M N +b M 1 s M N 1 + +b 0 s N 1 a N 1 s 1 a 0 s N (2.2) Here we assume M=N without loss of generality, H(s) becomes H(s) = b N+b N 1 s 1 + +b 0 s N 1 a N 1 s 1 a 0 s N (2.3) In a state-space system, output signal and input signal are denoted as Y(s) and U(s), respectively. Given the fact that the system transfer function is the ratio of the two signals, rearranging Equation 2.3, the output Y(s) can be written as Y(s) = b N U(s) + [b N 1 U(s) + a N 1 Y(s)]s [b 0 U(s) + a 0 Y(s)]s N (2.4) In Equation 2.4, the output Y(s) is a linear combination of input U(s) and Y(s) itself, both weighted by some transfer function coefficients and integrated by integrator s -1 for various times. As depicted in Figure 2.1, this fact suggests the observable canonical realization with N integrators cascaded in a chain. FIGURE 2.1: Observable canonical realization of a transfer function

19 Chapter 2. Background 7 In Figure 2.1, X1(s) XN-1(s), XN(s) are the state variables of state-space model. It can be observed that the state variable XN(s) is determined by adding the weighted input U(s) produced by the feedforward path bn, to the previous state variable XN-1(s), and then added by an-1bnu(s) + an-1xn(s) through the feedback path an-1. Therefore, for any N>1, we have sx N (s) = X N 1 (s) + a N 1 X N (s) + (b N 1 + a N 1 b N )U(s) (2.5) Thus, state variables are updated incessantly by a varying input signal U(s). The state-space model used in this work is to represent an electronic system with no charge at every circuit node before powering up, so here we are only interested in the zero-state response of the system by assuming the system starts from rest, i.e., all state variables are assigned with zero initial conditions in time domain. State-space model provides a simple but systematic way to synthesis any proper transfer function, and it is the theoretical basis of this entire thesis work. In later chapters, a correspondence will be established between this mathematical model and the system-level implementation of programmable OTA. Every transfer function block in Figure 2.1 will have an integrated-circuit realization through unit-sized transconductance cells.

20 Chapter 2. Background Gaussian Transfer Function A system with Gaussian-type transfer function has the minimum possible group delay and its step response never overshoots the steady state value. Given this advantage, Gaussian transfer function of different orders will be used to synthesis the programmable OTA in this work. The process to generate Gaussian transfer function of various orders is illustrated in this section. As its name suggests, the impulse response of a Gaussian transfer function can be described by a Gaussian function, which is widely used in statistics to define Gaussian distribution. In time domain, the impulse response of a Gaussian transfer function is given by g(t) = π π 2 α e α 2t2 (2.6) Where α is a real-valued coefficient defined by α = ln2 2f c (2.7) Here fc is the 3-dB cutoff frequency of the lowpass transfer function. Then, the impulse response of a Gaussian transfer function in frequency domain, which is the Gaussian transfer function itself, can be obtained through Fourier transform. A Gaussian transfer function has the general form G(jω) = e α2 ω 2 4π 2 (2.8) With Equation 2.7, the magnitude-squared frequency response is G(jω) 2 = e ln2 ω2 ωc 2 = e γω2 (2.9) Where ωc=2πfc and γ=ln2/ωc 2. Expanding Equation 2.9 using Maclaurin series up to the N th term, we have G(jω) 2 = 1 + γω 2 + γ2 2! ω4 + + γn n! ω2n = 1 γ 1+ N k k=1 k! ω2k (2.10) With the fact that G(s)G( s) s=jω = G(jω) 2 (2.11)

21 Chapter 2. Background 9 Equation 2.10 can be rewritten as G(s)G( s) = 1 γ 1+ N k k=1 k! ( 1)k S 2k (2.12) From a system synthesis perspective, the system transfer function G(s) can be also expressed by the ratio of P(s) to E(s), where P(s) and E(s) are the transmission zero polynomial and naturalmode polynomial, respectively. Which is to say P(s)P( s) = G(s)G( s) = 1 E(s)E( s) γ k 1+ N k=1 k! ( 1)k s 2k (2.13) Thus, this fact leads to the following correspondence E(s)E( s) = 1 + N γ k k=1 k! ( 1)k s 2k (2.14) To have a stable system, all system poles of the transfer function G(s) need to be situated on the left-half plane (LHP). Therefore, all LHP roots in Equation 2.14 should be assigned to E(s). Finally, the synthesized transfer function can be written as G(s) = E(0) E(s) (2.15) The value of E(s) at zero is assigned to the numerator to imply a unity gain at DC. Equation 2.15 is the desired Gaussian transfer function given in rational form derived from Maclaurin series. A more accurate approximation results in an increasing number of terms included in the Maclaurin series given in Equation 2.10, so does the order of transfer function G(s). In this work, Gaussian transfer function of different orders will be selected as the desired closed-loop transfer function of the programmable OTA system.

22 Chapter 2. Background Operational Amplifier and OTA Operational Amplifier (a) Circuit symbol of an operational amplifier (b) Modeling an operational amplifier with VCVS FIGURE 2.2: Operational amplifier circuit model Operational amplifier is an electronic device which amplifies a differential input voltage single and outputs the amplified signal in voltage form. As a result, the core of an operational amplifier is usually modeled as a voltage controlled voltage source (VCVS) with voltage amplification ratio Av. A commonly used operational amplifier model is depicted in Figure 2.2. Figure 2.2 (a) demonstrates the schematic symbol of a differential-in, single-out operational amplifier. DC biasing is not given in the figure as it is assumed that all DC points are properly established for amplifier operation. In open loop, the amplifier operation simply follows the equation V out = A v (V in+ V in ) (2.16) Where Vin+ and Vin- are the voltage potential at positive input terminal and negative input terminal,

23 Chapter 2. Background 11 respectively. Figure 2.2 (b) gives a more practical circuit model of operational amplifiers constructed with a VCVS and its input resistance Rin and output resistance Rout. To simplify the analysis, no capacitance is included in the model and the Vin- terminal is grounded without loss of generality. The output resistance is placed in series to the VCVS forming a Thévenin equivalent circuit. When the amplifier is placed in an actual circuitry, any source or load impedance connected with it forms a voltage divider. For instance, with an output impedance ZL connected between the output node and ground, the overall voltage gain of the amplifier becomes G = V out V in = A v Z L Z L +R out (2.17) Thus, a deduction on the amplifier gain is always expected when a source impedance ZS or a load impedance ZL is presented Operational Transconductance Amplifier Vin + Gm - Iout (a) Circuit symbol of an operational transconductance amplifier (b) Modeling an operational transconductance amplifier with VCCS FIGURE 2.3: Operational transconductance amplifier circuit model

24 Chapter 2. Background 12 Different from operational amplifier, OTA is a type of amplifier which amplifies a differential input voltage single but outputs the amplified signal in current form. As a result, the core of an OTA is usually modeled as a voltage controlled current source (VCCS) with transconductance gm. A commonly used differential-in single-out OTA symbol is depicted in Figure 2.3 (a). DC biasing is not given in the figure as it is assumed that all DC points are properly established for amplifier operation. In open loop, the OTA operation simply follows the equation I out = G m (V in+ V in ) (2.18) Figure 2.3 (b) gives a more practical circuit model of OTA constructed with a VCCS and its input resistance Rin and output resistance Rout. To simplify the analysis, no capacitance is included in the model and the Vin- terminal is grounded without loss of generality. The output resistance is placed in parallel to the VCCS forming a Norton equivalent circuit. The overall voltage gain of OTA can be found by A v = V out V in = G m R o (2.19) When the amplifier is placed in an actual circuit, any source or load impedance connected with it forms a current divider. For instance, with an output impedance ZL connected between the output node and ground, the overall voltage gain of the amplifier becomes G = V out V in = G m Z L R out Z L +R out (2.20) Thus, a deduction on the OTA gain is always expected when a source impedance ZS or a load impedance ZL is presented. Unlike operational amplifiers, an OTA is often designed to drive a capacitive load due to the nature of its high output impedance. Driving resistive load would require a voltage buffer placed at the output for impedance transformation. Therefore, the operation of a buffered OTA is equivalent to an operational amplifier, which is usually used in a resistive network. In this thesis, our proposed OTA will be tested in a resistive feedback loop, and thus a buffer is required to help driving these loop resistors.

25 Chapter 2. Background Closed-Loop Operation of Operational Amplifier Unity-Gain Follower AOL(s) FIGURE 2.4: OTA unity-gain follower configuration As the proposed programmable OTA will be placed in a closed-loop configuration to perform various tests, it is important to study the closed-loop operation of a given OTA. In this section we will use single-ended OTA as an example to carry out the discussion. Although the actual OTA implementation is fully differential in this work, but same equations should apply to the differential circuit without any extra constrain. Figure 2.4 illustrates a unity-gain follower setup for OTA closed-loop operation. In frequency domain, assuming the OTA has an open-loop transfer function AOL(s). As the output node is directly connected back to the negative input terminal of OTA, from Equation 2.16, we know V out (s) = [V in (s) V out (s)]a OL (s) (2.21) Therefore, V out (s)[1 + A OL (s)] = V in (s)a OL (s) (2.22) Rearranging the equation, the overall transfer function H(s) of a unity-gain follower is defined as H(s) = V out (s) V in (s) = A OL(s) 1+A OL (s) (2.23) With AOL(s)>>1, H(s) 1 and Vout Vin in both time and frequency domain. Thus in a unity-gain follower the input signal is always closely followed by the output.

26 Chapter 2. Background Unity-Gain Resistive Feedback AOL(s) FIGURE 2.5: OTA closed-loop inverting configuration For a differential-in differential-out OTA, the unity-gain setup described in the previous section is not applicable because the OTA is shorted by directly connecting inputs and outputs together. Therefore, the resistive feedback loop depicted in Figure 2.5 can be used as a replacement. As shown in the figure, the so-called inverting configuration contains two resistors R1 and R2 in the loop. Input signal Vin is injected to the negative input terminal of OTA through R1, and then output is delivered back to the same node through R2. To find the transfer function of this inverting configuration, one may start with Equation 2.16, V out (s) = [0 V in (s)] A OL (s) (2.24) By Ohm s law, assuming no current flowing into the input terminals of OTA due to high impedance, V in (s) V in (s)/r 2 = [V in (s) V out (s)]/r 1 (2.25) Plugging the expression of Vin-(s) from Equation 2.24 into Equation 2.25, yields V in (s) + V out (s) = R 2 1 V A OL (s) R out (s)[ + 1] 1 A OL (s) (2.26) Rearranging the equation, we have V in (s) = V out (s) [ R 2 R 1 ( 1 A OL (s) + 1) + 1 A OL (s) ] (2.27)

27 Chapter 2. Background 15 Therefore, the overall transfer function H(s) of an inverting configuration with resistor R1 and R2 is found as H(s) = V out (s) = V in (s) With AOL(s)>>1 in magnitude, H(s) can be simplified to A OL (s) [ R 2 R1 (1+A OL (s))+1] H(s) = V out (s) = A OL (s) R 1 V in (s) [ R 2 R1 (1+A OL (s))+1] R 2 (2.28) (2.29) Leading to the following input-output relationship in both time domain and frequency domain: V out = R 1 R 2 V in (2.30) In an inverting configuration, the input signal is amplified by ratio R1/R2. With R1=R2, another realization of unity-gain configuration is achieved. For a given sinusoidal input signal, the negative sign in Equation 2.30 indicates a 180 degrees lagging in phase at the output. Consequently, given an inverting configuration with unity-gain setup, the output is always a vertically flipped version of input. 2.5 D-Type Flip-Flop FIGURE 2.6: DFF symbol and its digital operation

28 Chapter 2. Background 16 D-type flip-flop (DFF) is a fundamental storage element in sequential digital logic. As a flipflop, it stores a single bit of data representing one of the two binary values 0 or 1. The DFF operation is edge-sensitive and synchronized by a clock signal. Figure 2.6 depicts the DFF circuit symbol and an example of its operation in time domain. Here we assume no time delay due to circuit parasitics and DFF operation is only sensitive to the rising edge of clock signal. As shown in this figure, with an input signal presented at its input data port D, the value of input signal is latched and delivered to the output port Q immediately at the rising edge of the clock signal. During the time when no rising edge is experienced in clock signal, DFF always holds its output regardless of the change at input. DFFs are used in this programmable OTA design to obtain a desired Gm value for every programmable stage. Multiple DFFs are cascaded in a serial chain forming a serial-in parallel-out shift register. All Gm cells connected to this chain are either turned on or off, depending on the binary value stored in each DFF. DFF has various types of realizations. Popular design choices include circuit made from SR latches and D latches. The timing performance and silicon cost can vary based on circuit implementation. Therefore, case-specific design consideration is required in a DFF design. 2.6 Summary The canonical-type state-space representation of a linear system was introduced as the method to synthesis the programmable amplifiers. As Gaussian transfer function was used as an example to be synthesized by the state-space method, the process to generate Gaussian transfer function of various orders was also illustrated in this chapter. Fundamental knowledge about operational amplifier, operational transconductance amplifier and their closed-loop operation was studied. Finally, a review about D-type flip-flop circuit operation was given.

29 Chapter 3 System-Level Synthesis of OTA In this chapter, we propose a novel OTA synthesis method together with its corresponding statespace realization. Gaussian transfer function of different orders is adopted as an example for OTA synthesis in this thesis work. Furthermore, the choice of integrators in the OTA realization is made with justified reasons. A full analysis on the OTA properties, including small-signal behavior, operating range scaling and system-level robustness is performed through circuit simulations. 3.1 OTA Transfer Function Synthesis Controller-Based Compensation Method The synthesis of OTA transfer function starts with a desired closed-loop transfer function T(s). Assuming the OTA is embedded in a single-loop feedback structure with feedback factor β, the OTA transfer function can be expressed as A(s) = T(s) 1 β T(s) (3.1) Provided the closed-loop transfer function T(s) has the general form, T(s) = 1 β d K 1 s K 1 + +d 1 s 1 +d 0 s N +d N 1 s N 1 + +d K s K +d K 1 s K 1 + +d 1 s 1 +d 0 (3.2) where di is the i-th coefficient of both the numerator and denominator polynomials, the OTA transfer function takes on the overall form of 17

30 Chapter 3. System-Level Synthesis of OTA 18 A(s) = 1 sk R(s) (3.3) Here A(s) consists of a product of K integrator functions (1/s K ) multiplied by, what we shall refer to as, a remainder function, R(s). The general form of Equation 3.2 is to be referred to as a polezero canonical type transfer function owing to its transfer function depends only on the coefficients of its pole polynomial. Comparing Equations 3.1 and 3.3, and substituting Equation 3.2 and rearranging, one finds the remainder function R(s) as R(s) = sk T(s) = 1 d K 1 s K 1 + +d 1 s 1 +d 0 1 β T(s) β s N K +d N 1 s N 1 K + +d K+1 s 1 +d K (3.4) For realization purposes, N 2K-1 otherwise the order of the denominator will be less than that of the numerator, which would lead to an impractical result. This sets an upper limit on the number of integrators that can be used to form the OTA. For reasons to be given shortly, an OTA with the largest DC gain is one realized with maximum number of integrators. For instance, an OTA described by a 5 th -order transfer function could be realized using 3 integrators and a 2 nd -order biquadratic function in cascade, as depicted by the block diagram shown in Figure 3.1. The circuit that realizes the remainder function is what control theorist refers to as a controller. The controller is used to stabilize the closed-loop configuration. Herein, we shall refer to this method of OTA stabilization as a controller-based compensation method. It should be noted that any filter synthesis method, such as cascade of bilinear/biquads, follow-the-leader feedback filter methods, etc., can be used to synthesize the open loop transfer function of the OTA provided it can handle an input-output transfer function with multiple poles at DC. In the past, one would not expect to synthesize a transfer function with poles at DC. FIGURE 3.1: Block diagram of a 5 th -order ultra-high gain OTA

31 Chapter 3. System-Level Synthesis of OTA State-Space Realization of OTA Another means in which to realize the OTA transfer function A(s) is through a state-space formulation involving the parameters {A, b, c, d} expressed in general terms as sx(s) = AX(s) + bu(s) y(s) = c T X(s) + du(s) (3.5) where X is an N-dimensional vector describing the states of the system, u and y are the scalar input and output signals, respectively, and A, b, c T and d are (N N), (N 1), (1 N) and (1 1) constant coefficient matrices, respectively. The overall transfer function can be described in terms of the state-space parameters as follows A(s) = c T (si A) 1 b + d (3.6) The advantages of a state-space formulation over the previous cascade approach is that it can directly lead to a realization with a greater number of integrators in cascade, specifically N-1 integrators, and an implicit controller function distributed among the various integrators. Following the well-known observable canonical state-space form [14], the OTA transfer function described by Equations 3.3 and 3.4, can be written as follows: X 1 (s) d N X 1 (s) 0 X 2 (s) X 2 (s) d N 2 s = + u(s) X N 1 (s) X N 1 (s) d 1 [ X N (s) ] [ ] [ X N (s) ] [ d 0 ] X 1 (s) X 2 (s) y(s) = [ ] X N 1 (s) [ X N (s) ] (3.7) Dividing both sides of the top equation with the Laplace variable s, the state-space equations become

32 Chapter 3. System-Level Synthesis of OTA 20 X 1 (s) d N X 1 (s) X 2 (s) = X 2 (s) s + 1 s X N 1 (s) X N 1 (s) [ X N (s) ] [ ] [ X N (s) ] X 1 (s) X 2 (s) y(s) = [ ] X N 1 (s) [ X N (s) ] 0 d N 2 u(s) [ d 1 d 0 ] (3.8) Figure 3.2 illustrates the form of these equations for a 5 th -order OTA, highlighting the cascade of four integrators with several input feed forward paths. Note that the integrator closest to the output has a feedback path rather than a feed forward path involving coefficient a11. This changes the integrator into a damped integrator. As will be seen shortly, this stage does not provide large DC gain and instead serves the purpose of positioning the closed-loop poles. The other bi terms are responsible for positioning the three zeros of the closed-loop transfer function. FIGURE 3.2: Block diagram of a 5th order ultra-high gain OTA realized using an observable canonical state-space formulation Synthesis and Realization of Gaussian Transfer Function This thesis work will use Gaussian transfer function of different orders as the closed-loop transfer function of the demonstrating circuit prototype to illustrate the procedure. Assume an OTA to be used in a unity-gain closed-loop configuration having a unit step response with a 5 th -order Gaussian response, i.e.

33 Chapter 3. System-Level Synthesis of OTA 21 T(s) = s s s s s (3.9) Next, to enable a realization as a cascade of 4 integrators, the numerator of T(s) must be modified to include a portion of the denominator polynomial in the numerator as described earlier as T(s) = s s s s s s s s (3.10) The additional LHP zeros generally alter the desired step response by introducing overshoot and ringing. This is clearly visible in the plot of the step response for each transfer function in Figure 3.3. It should be noted at this juncture that this design principle is not based on any pole-zero cancellation technique but rather on the careful placement of the poles and zeros such that a desired closed-loop step response whose transfer function has the general form shown in Equation 3.2. FIGURE 3.3: Comparing the step response of a 5th-order Gaussian transfer function and its modified form Assuming the step response achieves the desired closed-loop performance levels under realistic gain conditions, the resulting state-space realization would appear as that depicted in Figure 3.3 with frequency normalized coefficients derived from the Gaussian denominator polynomial coefficients seen listed in Table 3.1 for order = 5. Also listed in Table 3.1 are the polynomial coefficients for transfer function orders for 2 to 4. These numbers will serve as the basis of the circuit implementation in the following chapters.

34 Chapter 3. System-Level Synthesis of OTA 22 TABLE 3.1: Denominator Polynomial Coefficients of a Gaussian Transfer Function Order d0 d1 d2 d3 d Implementation of the 1/s Integrator FIGURE 3.4: Magnitude response of an ideal vs. non-ideal integrator operation Integrators are at the core of all OTA implementations and this work has no exception. The magnitude response of an ideal integrator is shown in Figure 3.4 as a dashed line. Here the gain is infinite at DC and rolls off with a constant rate of -20 db per decade. The gain reaches unity at the unity-gain frequency ωt. In practice, the frequency response behavior of an integrator will include the addition of a low-frequency pole, which we shall denoted as p1, and, possibly, the addition of a high-frequency zero, denoted as z1. The parasitic pole/zero is a result of the finite output resistance of the transistors used to construct the integrator. This effect also reduces the DC gain of the integrator from infinity to something much smaller, which we shall denote as Ao. These effects are depicted in the solid curve of Figure 3.4.

35 Chapter 3. System-Level Synthesis of OTA 23 FIGURE 3.5: Basic single-ended Gm-C integrators: (a) transconductance symbol (b) shunt-c and (c) Miller-C In comparison, any practical integrator will behave exactly like an ideal integrator for frequencies bounded approximately between the low-frequency pole, p1 and the high-frequency zero, z1. For general purpose applications, it is generally best to find an integrator with the lowest parasitic pole and the highest parasitic zero. There are two general types of integrators implemented in a CMOS technology: shunt-c and the Miller-C. These are shown in Figure 3.5 where the trapezoidal symbol represents a VCCS with transconductance gm and output resistance ro. In the case of the shunt-c integrator shown in Figure 3.5(b), the input-output transfer function can be described in terms of the transistor small-signal parameters gm,1 and ro,1 as v o v in (s) = g m,1r o,1 s = (1+s/ ro,1c1 ) A o (1+s/p 1 ) (3.11) Here we see the shunt-c integrator has a pole at 1/(ro,1C1) and a DC gain of gm,1ro,1. In contrast, the transfer function of the Miller-C integrator of Figure 3.5(c) is v o (s) = g m,1r o,1g m,2r o,2(1 s/ 1 v in (1+s/ gm,2ro,1ro,2c1 ) gm,2 C1 ) = A o (1 s/z 1 ) (1+s/p 1 ) (3.12)

36 Chapter 3. System-Level Synthesis of OTA 24 Here we see that this integrator contains both a pole and a zero. In the case of the pole, it is located at a much lower frequency than the shunt-c integrator, i.e., 1/(gm,2ro,1ro,2C1) although it also exhibits a high-frequency right-half plane zero at gm,2/c1. One will also noticed that the Miller-C integrator exhibits a much higher DC gain of gm,1ro,1gm,2ro,2. As long as the high-frequency zero z1 can be placed at least two order of magnitude greater than the unity gain frequency ωt, its presence will have little effect. Since the frequency at which the Miller-C integrator reaches unity gain is approximately gm,1/c1 and the parasitic zero is gm,2/c1 then this condition is simply met by ensuring gm,2 > 100 gm,1. A condition easily met in practice. As a result, the Miller-C integrator will be a better choice as an integrator, as it will have a larger DC gain and a lower parasitic pole. For frequencies above the pole frequency p1 and, of course, below the zero z1, the transfer function of the Miller-C integrator can be approximated as v o (s) A op 1 = ω t = g m,1 ( 1 ) v in s s C 1 s (3.13) Thus revealing that any coefficient of the state-space realization, such as di, is set by the unity-gain frequency ωt=gm,1/c1 of the corresponding Miller-C integrator. A state-space formulation involves numerous rows of integration equations having the general form X p = a p,p+1 X s p+1 + b p u s (3.14) FIGURE 3.6: Two-input Miller-C integrator

37 Chapter 3. System-Level Synthesis of OTA 25 A multiple-input Miller-C integrator having a similar form is shown in Figure 3.6. Here the inputoutput relationship can be written as V p = g m,1 C 1 ( 1 )V s p+1 + g m,3 ( 1 )V C 1 s in (3.15) Establishing the following correspondences, leads to the following coefficient relationships X p V p X p+1 V p+1 u V in a p,p+1 = g m,1 C 1 b p = g m,3 C 1 (3.16) Extending this approach to the remaining state-space equations leads to a similar result. The key take away here is that the state-space coefficient is set by the ratio of the transconducatance of the feed-in stage to the integrator to its integration capacitance C1. The transconductance of the second stage gm,2 is set much higher than gm,1 or gm,3 to place the parasitic zero at least one order of magnitude away from the unity cross-over frequency. For every coefficient, there is one degree of design freedom associated with it. One can either set Ci to a fixed value, and then select the gm values to correspond to the coefficient values, or vice versa.

38 Chapter 3. System-Level Synthesis of OTA Small-Signal Properties of the OTA In this section we shall outline several of the important properties of these ultra-high gain OTA circuits and what makes them different from traditional OTA implementations Evaluation of OTA Frequency Response As a first step, recall that the transfer function of a Miller-C integrator has the general form T 1 (s) = A o (1 s/z 1 ) (1+s/p 1 ) (3.17) To avoid getting bogged down with low-level details, each Miller-C integrator will be assumed to constructed with identical gm and ro, except that the transconductance associated with the zero term will be set at 100 gm so that it at least 100 times away from the unity gain frequency ωt of the integrator. Thus, one can write A o = g m 2 r o 2 p 1 = 1 g m r o 2 C = ω t A o z 1 = 100ω t (3.18) where ω t = g m C (3.19) Given the above facts, the frequency response behavior of an N-th order OTA can be approximated by A(s) A o N 1 s (1 z1 )N (1+ s p1 )N 1 R(s) (3.20) where R(s) is the remainder function defined by Equation 3.4 with K=N-1. Table 3.2 lists the pole and zero locations for a modified Guassian transfer function for orders 2 to 5. The DC gain of the OTA corresponds to the individual gains of N-1 Miller-C integrator stages, which can be made extremely high, i.e., A DC = A o N 1 (3.21)

39 Chapter 3. System-Level Synthesis of OTA 27 TABLE 3.2: Pole/Zeros Locations of the Remainder Function R(s) for Different Orders Corresponding to a Modified Gaussian Transfer Function Order Remainder Function R(s) Zeros Pole ± j , ± j Also, we see that there are N co-incident RHP zeros at z1 and N-1 co-incident low-frequency poles at p1, all resulting from the parasitic elements of the Miller-C integrator. By design, the zeros are purposely placed at least two orders of magnitude higher than the unity-gain frequency of a single stage Miller-C integrator. In regards to the remainder function R(s), there are N-2 LHP zeros located slightly below ωt and a single pole at a slightly higher frequency than the unity-gain frequency at a11ωt. Collectively, the LHP zeros force the OTA roll-off to a slope of -20 db/dec at the unity gain cross-over frequency. The 3-dB bandwidth of the OTA can be approximated as ω 3 db ω t A o 2 1 N 1 1 (3.22) where the factor 2 1 N -1-1 accounts for the bandwidth reduction caused by the co-incident poles. As a point of reference, this factor is equal to 1, 0.64, 0.51 and 0.43 for N equal to 2, 3, 4 and 5. The gain-bandwidth product (GBP) figure of merit reveals some very interesting properties associated with these ultra-high gain OTAs. Multiplying Equation 3.21 with 3.22, one finds GBP = A DC ω 3 db A o N 2 ω t (3.23) Here increasing the number of integrators in cascade can increase the GBP above the unity-gain

40 Chapter 3. System-Level Synthesis of OTA 28 frequency of the Miller-C integrator. While GBP is an interesting side effect, the real benefit of the proposed ultra-high gain amplifiers over present day OTA structures is that a much larger gain is available over its unity-gain bandwidth Verification of OTA Frequency Response Using Spice (a) Magnitude response (b) Phase response FIGURE 3.7: Normalized frequency response of the OTA in open-loop using ideal components A SPICE-like simulation of the magnitude and phase behavior of the proposed OTA structure is shown in Figure 3.7 for orders ranging from 2 to 5. Each OTA was designed to have a modified

41 Chapter 3. System-Level Synthesis of OTA 29 Gaussian unity-gain closed-loop response behavior as described by the polynomial coefficients seen listed in Table 3.1. The transconductances of all the integrators are modeled with ideal VCCS with an output resistance to provide a realistic level of DC gain. As is evident from Figure 3.7 (a), the DC gains ranges from 40 db to as high as 180 db for the 5 th order realization. All four realizations have a similar 3-dB normalized bandwidth of about rad/s. The gain roll-off beyond the 3-dB bandwidth varies from -20 db/dec to as high as -100 db/dec but all reduce to -20 db/dec at the unity gain frequency. Also shown in Figure 3.7 is the corresponding phase behavior (part (b)). Just before the unity gain frequency, the phase behavior for orders 3 to 5 sees a sudden change in its slope, quickly rising above the critical -180 degree phase point, staying above this point for at least one decade in frequency then leveling off to -360 degrees. The second order response does not has a LHP zero so there is no change in its phase. However, in all cases, the phase margin remains positive, although decreasing with OTA order. (a) Unit step response

42 Chapter 3. System-Level Synthesis of OTA 30 (b) Expanded view of the final error after settling FIGURE 3.8: Unit step response of the OTA in a unity gain configuration using ideal components In order to test out the original hypothesis of this work, the OTA was connected in a unity-gain configuration and its unit step response was simulated using SPICE and compare to the expected modified-gaussian behavior. The results are collected for OTA orders from 2 to 5 and displayed in Figure 3.8 (a). As is clearly evident, the results all agree with their expected behavior. In addition, it is also noticed that the peak value and the amount of ringing increases with order but the propagation delay decreases. Overall, no one order seems to have better settling time. This, of course, begs the question of what advantage does a high-order OTA have on the step response of the amplifier. The answer lies with the final error after the amplifier has settled. A higher order OTA will have smaller final settling error, as seen from the captured SPICE results shown in Figure 3.8 (b). The relative error can be seen to be inversely proportional to the DC gain of the OTA.

43 Chapter 3. System-Level Synthesis of OTA Bandwidth, Impedance and Dynamic Range Scaling OTAs are required to operate over many different bandwidths and impedance levels. By designing with a frequency and impedance normalized prototype, such as those described in Table 3.1, other OTAs can be derived from it by applying a scaling factor to the components of the prototype. In general, there are two independent scale factors that are commonly used. One involves scaling the bandwidth of the OTA and the other involves scaling the impedance level (or in other words, finding more practical component values) Bandwidth and Impedance Scaling In general, the bandwidth of the OTA can be increased from 1 rad/s to ωo rad/s by dividing all integrator capacitors by this same factor, i.e., C i C i ω o i = 1 N (3.24) It should be noted that if the OTA frequency response were scaled to very high frequencies, its behavior would experience changes on account of the influence of various transistor parasitics not considered in our analysis here. Conversely, the impedance level of any components associated with a single integrator can be scaled without changing its transfer function as long as the same factor, say γ, is used on all the transconductances and the integration capacitor associated with that cell. For instance, the two-input Miller-C integrator shown in Figure 3.6 consists of three transconductances gm,1, gm,2 and gm,3, and one integrator capacitor C1. These particular components can all be scaled according to the following rule without altering its transfer function: g m,1 γ g m,1 g m,2 γ g m,2 g m,3 γ g m,3 C 1 γ C 1 (3.25) If resistors were included in the circuit as well, then these would be scaled according to r o,1 r o,1 /γ r o,2 r o,2 /γ r o,3 r o,3 /γ (3.26)

44 Chapter 3. System-Level Synthesis of OTA Dynamic Range Scaling Another form of scaling can be used to equalize the peak or root mean square (RMS) values associated with each integrator output during closed-loop operation. This maximizes the signal handling capability of the overall closed-loop configuration, i.e., maximizes the input linear range before the onset of slew-rate limiting. Moreover, scaling for maximum dynamic range reduces the spread in the various components used to realize the OTA a benefit that should be exploited with every design. Through a transient or frequency-domain analysis of the OTA in closed-loop operation, a metric of interest is collected for each integrator output, such as the peak value corresponding to a step input, and assigned to the corresponding element of a diagonal matrix, normalized by the desired peak value Vmax. For instance, if the peak value of the output of the i th integrator is denoted as αi and then one can write the diagonal matrix as α 1 0 T = 1 V max 0 [ 0 α α N α N ] (3.27) Dynamic range scaling would then be performed on the state-space parameters according to the similarity transformation described by: {A, b, c, d} {T 1 AT, T 1 b, T T c, d} (3.28) For the specific set of OTA state-space parameters seen listed in Equation 3.7, one would arrive at the following scaled state-space parameters as

45 Chapter 3. System-Level Synthesis of OTA 33 d K α 2 /α A = 0 0 [ d K 1 V max /α 2 B = d 1 V max /α N 1 [ d 0 V max /α N ] 0 α 3 /α α N /α N 1 0 ] C = [α 1 /V max 0 0 0] (3.29) While the only nonzero element in the C vector appears as though it is no longer unity, in practice, Vmax and α1 would actually be the same value on account of the goals of the closed-loop system. Table 3.3 presents the state-space coefficients corresponding to the modified Gaussian transfer function presented earlier in Table 3.1 when scaled for equal integrator transient peak outputs. TABLE 3.3: Modified-Gaussian State-Space Coefficients Scaled for Maximum Dynamic Range Order A-Matrix State-Space Coefficients a11 a12 a23 a34 a Order B-Matrix State-Space Coefficients b1 b2 b3 b4 b

46 Chapter 3. System-Level Synthesis of OTA 34 Order C-Matrix State-Space Coefficients c1 c2 c3 c4 c5 all OTA Robustness and Calibration It is well known in the active filter literature that a canonical state-space realization is very sensitive to its coefficients [15]. This limited their use as precision filter circuits. However, for OTA applications, this sensitivity is less critical unless the order of the realization is very high, and as such, some form of post-manufacturing calibration can be introduced OTA Sensitivity Analysis To better understand the robustness of the proposed OTA structure with a given transfer function, consider the analysis of an OTA design in a unity gain configuration for orders ranging from 2 to 5. As before, a closed-loop modified Gaussian response will be used. Two metrics will be considered here. The first is the normalized sensitivity of the peak value of the step response to the individual filter coefficients, di. Mathematically, it is defined as S Peak di = d i Peak Peak d i (3.30) Through a numerical analysis, the results are displayed in Figure 3.9 (a). Here we see that the sensitivity to changes in the peak value increases with OTA order. Moreover, we see that the maximum peak sensitivity for the 5th order design occurs with the b2 coefficient. If the any coefficient undergoes a 1% change in value, then one can expect a 0.4% change in its peak value for many OTA applications this is an acceptable amount.

47 Settling-Time Sensitivity (a.u.) Peak Sensitivity (a.u.) Chapter 3. System-Level Synthesis of OTA 35 Another sensitivity metric that is quite revealing is the normalized sensitivity to settling time, Ts. Mathematically, it is defined as T S S di = d i T S T S d i (3.31) and the results are displayed in Figure 3.9 (b). Here it is very evident that the sensitivity to parameter changes is quite low for OTA orders less than 5 but increases very quickly above this value. In fact, a 1% change in the b3 coefficient in a 5 th order OTA will result in a 25% change in its settling time. In many applications this would be unacceptable unless a large margin was included in the design a11 a12 b2 a23 b3 a34 b4 a45 b5 Programmable Unit 2nd 3rd 4th 5th (a) Sensitivity to peak value a11 a12 b2 a23 b3 a34 b4 a45 b5 Programmable Unit 2nd 3rd 4th 5th (b) Sensitivity to settling time FIGURE 3.9: Sensitivity analysis of an OTA in a unity-gain closed-loop configuration

48 Chapter 3. System-Level Synthesis of OTA OTA Stability Analysis A means to quantify the stability robustness of a closed-loop system was defined by Kharitonov using a four polynomial method involving its characteristic function [16]. Consider that the inputoutput transfer function T(s) of the OTA of Figure 3.2 in a unity-gain configuration can be written in terms of its state-space parameters as T(s) = a 1,2 b 2 s 3 +a 1,2 a 2,3 b 3 s 2 +a 1,2 a 2,3 a 3,4 b 4 s+a 1,2 a 2,3 a 3,4 a 4,5 b 5 (s 5 a 1,1 s 4 +a 1,2 b 2 s 3 +a 1,2 a 2,3 b 3 s 2 +a 1,2 a 2,3 a 3,4 b 4 s+a 1,2 a 2,3 a 3,4 a 4,5 b 5 ) (3.32) Here the poles of this system are simply the roots of the denominator polynomial. The system will be stable if and only if the poles of this feedback system remain in the LHP under all possible variations in the OTA parameters. Assuming each coefficient can undergo a worst-case error of ±ε due to manufacturing, Kharitonov showed that the system will be stable if the roots of the following four polynomials remain in the LHP: p 1 (s) = s 5 (1 ε)a 1,1 s 4 + (1 + ε) 2 a 1,2 b 2 s 3 + (1 + ε) 3 a 1,2 a 2,3 b 3 s 2 +(1 ε) 4 a 1,2 a 2,3 a 3,4 b 4 s + (1 ε) 5 a 1,2 a 2,3 a 3,4 a 4,5 b 5 p 2 (s) = s 5 (1 + ε)a 1,1 s 4 + (1 ε) 2 a 1,2 b 2 s 3 + (1 ε) 3 a 1,2 a 2,3 b 3 s 2 +(1 + ε) 4 a 1,2 a 2,3 a 3,4 b 4 s + (1 + ε) 5 a 1,2 a 2,3 a 3,4 a 4,5 b 5 p 3 (s) = s 5 (1 + ε)a 1,1 s 4 + (1 + ε) 2 a 1,2 b 2 s 3 + (1 ε) 3 a 1,2 a 2,3 b 3 s 2 (3.33) +(1 ε) 4 a 1,2 a 2,3 a 3,4 b 4 s + (1 + ε) 5 a 1,2 a 2,3 a 3,4 a 4,5 b 5 p 4 (s) = s 5 (1 ε)a 1,1 s 4 + (1 ε) 2 a 1,2 b 2 s 3 + (1 + ε) 3 a 1,2 a 2,3 b 3 s 2 +(1 + ε) 4 a 1,2 a 2,3 a 3,4 b 4 s + (1 ε) 5 a 1,2 a 2,3 a 3,4 a 4,5 b 5 Using the state-space parameters for the OTA from Table 3.3 for orders of 2 to 5, the worst-case manufacturing error can be found by solving for the value of ε that leads to the critically damped situation. These results are summarized in Table 3.4. Clearly, the higher the OTA order, the lower the tolerance to manufacturing errors. As a first-order approximation, one can state that the maximum error tolerance decreases by a factor two with increasing order beyond second-order.

49 Chapter 3. System-Level Synthesis of OTA 37 TABLE 3.4: Worst-Case Coefficient Tolerances Predicted by Kharitonov s Method Order Max. Error, ε Post-Manufacturing Calibration For very high order, expecting manufacturing tolerances as low as 7.8% may be a tall order, especially across cell transconductances. Instead, one can rely on a post-manufacturing calibration procedure. To the best of the author s knowledge this is the first time such a scheme is being propose for OTA circuits. Calibrating circuits have generally been performed at a higher circuit level to compensate for errors introduced by low-gain OTAs. Here the reverse is being proposed calibration is to be used to ensure the OTA has a high gain so that circuit errors are minimized. FIGURE 3.10: Schematic diagram of the 20-Gm programmable cell

50 Chapter 3. System-Level Synthesis of OTA 38 As each coefficient is realized as an integer sum of individual unit-sized Gm cells, digitally selected from a bank of Gm cells using a scan chain of DFFs that switch on or off the bias level (Vctrl) to the individual cell. With the inputs and outputs of all Gm cells tied together, through the appropriate bit sequence, the appropriate number of unit-sized Gm cells can be connected in parallel. This is illustrated in Figure 3.10 for two unit Gm cells. If after manufacturing the coefficient Gm level is set either too low or too high, the bit sequence stored in the scan chain can be reset to adjust the total Gm value or the bias voltage level Vctrl can be altered slightly. The trimming algorithm would begin by adjusting the most sensitive coefficients first, progressively moving down towards the least sensitive one. 3.6 Summary The synthesis of proposed OTA at system level was realized by state-space realization and specified values were assigned to each transconductance cell in the system. The choice of integrators in the OTA realization was made with justified reasons. A full analysis on the OTA operations, including small-signal behavior, operating range scaling and system-level robustness was carefully performed through SPICE-like circuit simulations.

51 Chapter 4 Design of Programmable OTA Prototype This chapter will explain the design choices made for the programmable state-space OTA prototype, including the circuit-level implementation of individual circuit block. The performance of some blocks will be verified by SPICE simulation, and the operation of the complete OTA prototype will be evaluated as well. 4.1 System-Level Implementation of Programmable OTA In order to demonstrate the synthesis method illustrated in Chapter 3, a fully programmable state-space OTA is designed for fabrication in the IBM 130 nm CMOS process. The circuit can be programmed for OTA orders ranging from 2 to 5, and can be used to realize a wide range of transfer functions. A system-level architectural view of the proposed amplifier is depicted in Figure 4.1. The basic structure of this amplifier is identical to that shown in Figure 3.2 with a one-to-one correspondence between the grey-shaped transconductance cells labeled as P1, P2, P3,, P9 and the state-space parameters, a11, a12, b2, b5. These cells are digitally programmable using a bank of twenty unit-sized Gm-cells in the manner illustrated previously in Figure The transconductance stage is realized with a bank of one hundred unit-sized Gm-cells. This will force the zero of each integrator to a frequency of two orders magnitude higher than the unity-gain bandwidth of each integrator, which should minimize the effect of the RHP zeros. 39

52 Chapter 4. Design of Programmable OTA Prototype 40 FIGURE 4.1: Schematic diagram of a fully programmable ultra-high gain OTA

53 Chapter 4. Design of Programmable OTA Prototype Unit-Sized Gm Cell Design The unit-sized Gm cell is an adaptation of the design first proposed in [17]. As shown in Figure 4.2, the Gm cell consists of a transconductance stage and an adaptive bias circuit. Within the transconductance stage, transistor M1 and M2 form the input differential pair; M3 and M4 are the source degeneration transistors to improve the linearity of the transconductance; M5 and M6 are the common-mode feedback transistors operating in their triode region to set the output commonmode (CM) level. The transconductance of the cell can be changed via the bias voltage Vctrl applied to the gates of transistor M9 and M10. An adaptive bias circuit is included to counteract changes in the output CM level when the transconductance is changed via the control voltage terminal Vctrl. FIGURE 4.2: Schematic diagram of the fully differential unit-sized Gm cell

54 Chapter 4. Design of Programmable OTA Prototype 42 The unit-sized Gm cell was designed for a nominal transconductance of 50 μa/v at a control voltage of 300 mv using the transistor aspect ratios seen listed in Table 4.1. The input and output CM level are set at one-half the VDD level at 600 mv. The output current versus input voltage for different control voltage settings as computed by SPICE is displayed in Figure 4.3 (a). The corresponding transconductance for these same control voltage settings is shown in part (b) of this figure. At Vin = 0 V, the transconductance is seen to vary from 40 μa/v to as high as 66 μa/v for control voltage settings between 280 mv to 320 mv. It is also important to note that the cell can be completely turned off by setting the control voltage to zero. This provides a simple on-off control mechanism that is used to set a desired transconductance level in a programmable Gm cell that is described in the later section. TABLE 4.1: Unit-Sized Gm Cell Transistor Aspect Ratios M1 M2 M3 M4 0.72mm 0.36mm 0.72mm 0.36mm 0.72mm 0.36mm 0.72mm 0.36mm M5 M6 M7 M8 5.04mm 0.36mm 5.04mm 0.36mm 1.44mm 0.36mm 1.44mm 0.36mm M9 M10 M11 M mm 0.36mm 1.44mm 0.36mm 1.08mm 0.36mm 2.52mm 0.36mm M13 M mm 0.36mm 1.44mm 0.36mm

55 Chapter 4. Design of Programmable OTA Prototype 43 (a) Output current I0 versus Vin (b) Transconductance versus Vin FIGURE 4.3: SPICE simulation results for a unit-sized Gm cell with different control voltage Vctrl values

56 Chapter 4. Design of Programmable OTA Prototype D-Type Flip-Flop Design FIGURE 4.4: Gate-level schematic design of the D-type flip-flop There are various existing DFF designs directly available to be implemented as the controller for Gm stage programming. The DFFs in the OTA prototype do not operate constantly and they become inactive after configuring all programmable Gm cells. Without any demanding timing specification on DFF operation, the simplicity of DFF structure and the silicon area required for physical implementation are considered as the primary design considerations. These are both relevant to the number of transistors used in a DFF structure. The discussion above yields the DFF implementation with 6 identical 3-input NAND gates and the circuit schematic is given in Figure 4.4. The size of each transistor can be flexible without affecting OTA performance, so it is not specified in the context. However, for space-saving purpose these transistors should be minimized in the IBM 130 nm CMOS process. In addition, this particular design choice enables set and reset capability in OTA programming, through which every DFF can be reconfigured in one single clock cycle.

57 Chapter 4. Design of Programmable OTA Prototype Analog Multiplexer Design FIGURE 4.5: Gate-level schematic design of the analog multiplexer The operation of each programmable Gm stage is determined by the bit sequence stored in the DFF chain. By default, the DLL design described in Section 4.3 operates with a 1.2V digital logic. Therefore, an analog multiplexer is required to implement the on-off control mechanism that is used to set a desired transconductance level in a programmable Gm cell. The multiplexer converts the 1.2V output from a DFF to the voltage level equals to the external voltage reference Vctrl, and the 0V output determined by a DFF should remain unchanged as this voltage level is assigned to set the transconductance to zero (turning Gm cells off). The gate-level schematic of the analog multiplexer design is depicted in Figure 4.5. The same principles considered in DFF design should apply to analog multiplexer as well to minimize implemented silicon area. The analog multiplexer consists of two minimum-sized inverters (120μm/120μm for every transistor in 130nm CMOS) cascaded in series, where the power rail of the second inverter is supplied by Vctrl instead of 1.2V. This simple structure can convert the voltage input Vin to either Vctrl or 0V, depending on the digital output of a given DFF.

58 Chapter 4. Design of Programmable OTA Prototype Programmable Gm Cell Design The programmable Gm stage consists of 20 unit-sized Gm cells all connected in parallel in the manner described earlier and illustrated in Figure Whether or not the Gm cell contributes to the total transconductance depends on the state of the enable bit established by the corresponding D-type flip-flop. This bit is used to switch between a nominal control voltage level, say between 280 mv to 320 mv, which is set externally using the Vctrl pin of the IC, or 0 V to shut down the cell. A 20 bit binary sequence is used to set the state of the programmable Gm. All the enable bits of the nine programmable Gm cells in this prototype are daisy chained together and loaded externally using a 2-wire clock and data control bus, much like that described for the I 2 C bus protocol defined by Philips. FIGURE 4.6: Transfer characteristic of the programmable Gm cell To illustrate the functionality of this programmable Gm stage, Figure 4.6 illustrates the transfer characteristic of the programmable Gm cell as computed from data generated from a SPICE analysis. Specifically, one sees that transconductance of the cell varies from 0 μa/v to a maximum level that ranges between 760 μa/v to 1350 μa/v, depending on the bias level at the control pin.

59 Chapter 4. Design of Programmable OTA Prototype 47 Moreover, the slope of the best-fit line drawn through the data set ranges from 38.0 μa/v/bit to 67.5 μa/v/bit. As is clearly evident, the programmable Gm cell shows excellent linearity over its full programming range at any particular control voltage setting. 4.6 Two-Input Miller-C Integrator At the core of our amplifier prototype is the creation of a two-input fully differential Miller-C integrator, in the manner illustrated in Figure 3.6; albeit here we are using fully differential inputs and outputs. As the target application for this prototype is to realize minimum-sized integrators with a unity-gain bandwidth of approximately 10 MHz, a 2-pF capacitor is to be used with each integrator realization. Using two feed-in branches to the integrator, one realized with a unit-sized Gm stage and the other set at 20 times the unit-size. The stage supporting the integrator capacitor was set at 100 unit-sizes. The bias voltage Vcrtl for each Gm cell was set to 300 mv. FIGURE 4.7: Frequency response behavior of a two-input Miller-C integrator with one input grounded as computed by a SPICE analysis on a fully extracted layout

60 Chapter 4. Design of Programmable OTA Prototype 48 With one input grounded and other excited by a 1-V AC voltage source, the frequency response behavior of the fully extracted circuit including layout parasitics was simulated using SPICE. The magnitude and phase results are shown in Figure 4.7. As is evident, the integrator output corresponding to the unit-sized feed-in branch displays a unity-gain frequency of about 2.5 MHz whereas the integrator output corresponding to the 20 unit-sized feed-in branch has a unity-gain bandwidth of about 70 MHz. One also sees that that the DC gain is 24 db for the first case and 50 db for the higher Gm case. A RHP zero is present in both cases; located above 1 GHz in both cases. This zero is caused by gate-drain capacitance associated with each transistor and is not related to the Miller-C RHP zero mentioned earlier. Instead, the Miller-C RHP zero is located close to a new parasitic pole arising from the layout parasitics (e.g., transistor gate capacitances). This is evident from the way the phase changes in the frequency region slightly above the unity-gain frequency. The theory presented earlier in Section 3.2 for a single input integrator did not contain this additional parasitic pole. While an expression for this pole in terms of the parasitic elements is rather cumbersome, the general form of the Miller-C integrator transfer function would appear as T 1 (s) = A o (1 s/z 1 ) (1+s/p 1 )(1+s/p 2 ) (4.1) where Ao, z1 and p1 are the same as before as shown in Equation 3.18 and p2 represents the additional parasitic pole. This parasitic pole-zero pair does degrade the phase behavior of the integrator around its unity gain frequency. For the minimum Gm case, the phase error is about 0 degrees whereas for the maximum Gm case, the phase error is as large as 30 degrees. For the specific transistor sizing used in this Miller-C integrator, each additional unit-sized Gm cell will contribute a 1.5 degree phase error at their respective unity-gain frequencies.

61 Chapter 4. Design of Programmable OTA Prototype IC Floor Plan FIGURE 4.8: Cadence layout view of the programmable amplifier in the IBM 130 nm technology The amplifier layout is implemented in IBM 130 nm CMOS technology. The design occupies a total active area of 1 mm2, which includes the 23 bond pads with electrostatic discharge (ESD) protection. The active area occupied by the programmable OTA alone is 0.6 mm2. A layout view of the IC is shown in Figure 4.8 with various cells identified. Here the two main banks of 100 and 20 Gm cells are labeled. Also seen are labels for the cells corresponding to the state-space coefficients. All cells were laid out with common-centroid geometries in mind so as to minimize the potential offset problem caused by device mismatches and process variations.

62 Chapter 4. Design of Programmable OTA Prototype Open-Loop Frequency Operation In Section 4.6 the phase error in Miller-C integrator was discussed. It is important to note that the phase error contributed by the large Gm cell is not as bad as it looks. As the OTA transfer function is modified by the remainder function R(s), the parasitic pole of each integrator has only a marginal effect on the open-loop response of OTA. To see this, the magnitude and phase response of the OTA with layout parasitics included for orders 2 to 5 is plotted in Figure 4.9 and compare to the schematic level response. As is clearly evident, only small differences appear between the two realizations. FIGURE 4.9: Frequency response of the open-loop programmable amplifier extracted from layout and compared to the ideal simulated result One can see from Figure 4.9 that the second-order system has a voltage gain of 58 db and a phase margin of 70 degrees; the third-order system has a voltage gain of 95 db and a phase margin of 45 degrees; the forth-order system has a voltage gain of 133 db and a phase margin of 25 degrees; whereas the fifth-order system has a voltage gain of 155 db and a phase margin of 20 degrees. While one may concluded that the design is less robust for higher-orders, as the phase margin is smaller.

63 Chapter 4. Design of Programmable OTA Prototype Closed-Loop Unity-Gain Operation In order to measure the impact of the layout parasitics on the proposed approach, as well as any co-efficient quantization effect, in this section a fully extracted SPICE simulation of a fully differential version of the OTA in a unity-gain configuration is performed. These simulations will include all the parasitics in the design including those that arrive from the digital scan chain control lines, pads and ESD structures. Owing to the fully differential nature of the OTA, the OTA will be embedded into the unity-gain resistive feedback circuit shown in Figure The DUT in the figure refers to the device under test, namely, the OTA. As the output impedance of the OTA is rather high, output buffers are included to help drive the resistive feedback loads. The buffers are designed to have a bandwidth 100 times greater than the unity-gain frequency of the OTA. FIGURE 4.10: Fully differential unity-gain amplifier with resistive feedback It is important to note that the feedback factor β is no longer equal to one, as was assumed before, and is now equal to 0.5. This, in turn, requires the OTA to have twice the gain it had before. This is easily accommodated by doubling all the b coefficients in the state-space formulation shown listed in Table 3.3. Moreover, to implement any one of the state-space realizations described in Table 3.3, one must consider that the OTA is programmable in terms of unit-sized Gm cells. Hence, the coefficients in Table 3.3 must be mapped and quantized in terms of integer values. These are summarizes in Table 4.2, together with the value of each integrator capacitors seen listed in Table 4.3.

64 Chapter 4. Design of Programmable OTA Prototype 52 TABLE 4.2: Programmable OTA Coefficients for Application in a Resistive Feedback Unity- Gain Amplifier Coefficients Order P1 a P2 a P3 b P4 a P5 b P6 a P7 b P8 a45 1 P9 b5 9 TABLE 4.3: Integrator Capacitor Values C1 C2 C3 C4 C5 2 pf 6 pf 4 pf 4 pf 2 pf A transient analysis is performed to verify that the amplifier with layout parasitic included indeed resembles its intended step responses, i.e., such as those displayed in Figure 3.8(a) for the schematic realization using ideal components. The simulation results are provided in Figure 4.11 for a 20 mv step input. While the 2 nd and 3 rd -order responses are quite similar to their ideal response, the 4 th and 5 th -order response appear to have a little more ringing present. In addition, the 5 th -order response appears to have very large peaks and valleys. Further investigation reveals these errors are the result of quantization effects introduced by rounding the coefficient values to multiples of a unit Gm value. All in all the OTA with orders from 2 to 4 are quite practical and useable. The 5 th -order response, however, in its present form my need some form of postmanufacturing calibration.

65 Voltage Gain (db) Chapter 4. Design of Programmable OTA Prototype 53 FIGURE 4.11: Post-layout simulated normalized step response of the programmable amplifier For step inputs as large as 400 mvpp, the behavior of the amplifier remains much the same as that shown in Figure 4.11 and is not shown here. The amplifier does not reveal any slew-rate limiting effects at its output. When the input level exceeds 400 mvpp, the output begins to ring excessively but does not slew. This is the result of the source-degeneration transistors used in the front-end stage of the OTA (see Figure 4.2). Such an approach is rarely, if ever, used in OTA design, as it comes at the expense of lost DC gain. With the proposed approach, there is plenty of gain available to trade-off with other OTA concerns. We will re-visit this issue further in the next chapter on the measurement results th 5 4 th 0 3 rd -5 2 nd E+05 1.E+06 1.E+07 1.E+08 Frequency (Hz) FIGURE 4.12: Simulated closed-loop AC response of the amplifier in a unity-gain configuration for various OTA orders

66 Chapter 4. Design of Programmable OTA Prototype 54 The AC response of the closed-loop amplifier in a unity gain configuration is shown in Figure As is clearly evident, as the OTA order increases, the resonance peak and the 3-dB bandwidth increases. This plot will also serve as the reference when the measured closed-loop AC response is presented in the next chapter Summary The circuit-level implementation of the programmable OTA was given in this chapter with details. At circuit component level, this includes design choices made for unit-sized Gm cells, DFFs, analog multiplexers and programmable transconductance cells. At system level, this includes two-input Miller-C integrator design and OTA system implementation. The amplifier layout was implemented in IBM 130 nm CMOS technology. In the last, open-loop and closed-loop operation of the completed OTA prototype was evaluated.

67 Chapter 5 OTA Testing Setup A proper testing environment needs to be established before measurements can take place. In addition, the ultra-high gain property associated with our OTA prototype requires special testing circuitry for DC gain measurement. This chapter will discuss the necessary procedures taken to prepare the OTA test bench. 5.1 Fabricated OTA Prototype The completed OTA design, named as ICGMGGAM, was taped out and sent to foundry for production. The fabrication service was provided by MOSIS and the process was managed through a subsidized academic peer-review program offered by Canadian Microelectronics Corporation (CMC). Forty programmable OTA dies were returned from fabrication and five of them were packaged in CFP24A, a 24-pins ceramic flat package (CFP). With a surface-mount structure connected to the printed circuit board, this package offers much less package parasitics than its through-hole counterpart. A die micrograph of the fabricated programmable OTA is given in Figure 5.1. Compared to the layout view of the programmable amplifier shown in Figure 4.8, all capacitors and bond pads in the die photo are clearly visible. However, to fulfill a specified fabrication requirement, most chip areas are occupied by some square patterns. As these square patterns are assigned to top metal layers, it is not possible to observe any 20 or 100 Gm cells placed beneath. 55

68 Chapter 5. OTA Testing Setup 56 FIGURE 5.1: Die photo of the programmable OTA fabricated in IBM 130nm CMOS technology The programmable OTA bonding diagram is depicted in Appendix II with all 23 bond pads connected to CFP24A package leads. A pinout diagram of the programmable OTA is shown in Figure 5.2 to establish the correspondence between bond pads and package leads. Table A.2 in Appendix III summarizes the pin assignments of OTA with the functionality of each pin specified. Pin 19 is labeled as N/C (not connected) because there is no physical connection made from the fabricated OTA die to this pin. Pin 1,2,3,4, 23 and 24 are assigned to some non-relevant circuitry on chip for other research purposes, so they are labeled as N/C as well. This table may serve as a handful reference for the PCB design in later sections.

69 Chapter 5. OTA Testing Setup 57 FIGURE 5.2: Pinout diagram of the programmable OTA packaged in CFP24A 5.2 Testing Circuitry Testing Circuitry for Unity-Gain Closed-Loop Measurement To measure the closed-loop response of the fabricated programmable OTA, a customized testing circuitry is required to interface the OTA with external test equipments. The circuit schematic for measuring OTA closed-loop behaviors is the same as illustrated in Figure The fully differential programmable OTA is placed in a resistive feedback loop with a unity gain configuration. By providing a square wave and a sinusoidal wave to the differential input terminal Vin, the step response and closed-loop frequency response of the fabricated OTA can be obtained respectively by measuring Vout through an oscilloscope.

70 Chapter 5. OTA Testing Setup Testing Circuitry for Open-Loop DC Gain Measurement FIGURE 5.3: Fully-differential servo-loop testing circuitry for DC gain measurement From the simulated open-loop frequency response of the programmable OTA depicted in Figure 4.9, it can be observed that the programmed OTA DC gain can be as high as 150dB. With a 1.2V single-rail power supply, this much gain will make the open-loop DC gain measurement extremely difficult. The main problem is to create an input testing signal with an amplitude less than 1μV. This can be hardly achieved with the instruments available at hand. Besides, the DC offset and thermal noise level can be few orders of magnitude higher than the input testing signal, which would result in a saturated OTA operation in open loop. To avoid these problems, Figure 5.3 shows a so-called servo-loop testing circuitry to measure DC gain in a closed-loop configuration. There are in total three negative feedback loops included in the servo-loop circuit. The device under test (DUT), referred to our programmable OTA without losing any generality, forms the primary feedback loop with two TL082 operational amplifiers. Two buffers are placed at DUT

71 Chapter 5. OTA Testing Setup 59 outputs to prevent backdriving. The two 10kΩ resistors at the input terminals of DUT and the two variable resistors next to them are identified as the feedforward and feedback resistors in the feedback loop, respectively. This loop is responsible for amplifying the differential signal applied at DUT inputs by 1+1MΩ/10kΩ=101 times in magnitude, assuming the variable resistors are tuned to 1MΩ as shown in Figure 5.3. Therefore, by taking the readings from the DC voltage meters VM1 and VM2, the magnitude of the differential DC signal appeared at DUT input terminals, here denoted as VIN, can be found by V IN = VM2 VM1 101 (5.1) The other two identical secondary feedback loops are composed by TL082 operational amplifiers, and each loop consists of a 1μF feedback capacitor. At DC, the voltage at the negative input terminal of TL082 equals to Vanalog, whereas the voltage at the positive input terminal is forced to be at the same potential in a negative feedback loop. In this specific case, Vanalog is set to 600mV to properly bias the programmable OTA. In these two secondary feedback loops, a differential DC voltage can be assigned at DUT outputs through Vset1 and Vset2. As the current flowing into OTA input terminals are negligible, the magnitude of the differential DC signal at DUT outputs, here denoted as VOUT, is determined by V OUT = V SET2 V SET1 (5.2) With the differential input and output signals ready, the open-loop DC gain of DUT is given by A OL = V OUT V IN = 101 V SET2 V SET1 VM2 VM1 (5.3) In actual measurements, the resistance of two variable resistors should vary depending on the estimated DC gain of a given DUT. With the same DUT output voltage level assigned by Vset1 and Vset2, a large DC gain usually corresponds to a large resistance, as the input-amplified signals VM1 and VM2 become less visible under larger DC gains. However, from a practical point of view, the resistance value cannot exceed manufacturing limit, and having large resistance values for low DC gains can saturate VM1 and VM2 to the power rails.

72 Chapter 5. OTA Testing Setup Merged Circuitry for DC and Closed-Loop Measurement FIGURE 5.4: Customized testing circuitry for DC gain and closed-loop measurement One may notice that the outer feedback loop in Figure 5.3 is almost identical to the circuit depicted in Figure Therefore, instead of creating two separate circuitries performing various tasks, a little alternation to the DC testing circuit can efficiently merge the two circuitries together. As illustrated in Figure 5.4, the two switches placed in the circuit schematic can select a desired measurement loop with circuit outputs monitored by VM1 and VM2. The switch branching displayed in the figure corresponds to the unity-gain closed-loop configuration. Branching the switches to another node results in the DC gain measurement loop given in Figure 5.3. Merging the two circuitries saves a significant amount of time and budget, as the supporting circuitry related to a DUT, which is the 24-pins programmable OTA in this work, only needs to be implemented once. This fact will become more visible when circuit board design is discussed in the next section.

73 Chapter 5. OTA Testing Setup Printed Circuit Board Design FIGURE 5.5: Printed circuit board design for DC gain and closed-loop measurement

74 Chapter 5. OTA Testing Setup 62 A printed circuit board design (PCB) is implemented based on the testing circuitry proposed in Section As demonstrated in Figure 5.5, the completed circuit board prototype occupies a 5 inches by 3 inches rectangular area. The board consists of 4 copper layers isolated by FR-4 materials. Among these 4 copper layers, ground plane and power plane are positioned in between the top layer and bottom layer to achieve high-quality signal shielding. Signal traces, together with other surface-mount or through-hole components, are routed on the top and bottom plane. Furthermore, the existence of power and ground plane in a 4-layer board may also simplify PCB design process, as small plated-through holes can be used to replace many traces required for power and ground connections in a 2-layer design. In addition, a silkscreen labeling layer is printed on the finished PCB to properly identify every circuit component. On-board components are placed as close as possible to minimize parasitic effects. Next to each power supply, there are four capacitors placed for noise filtering. Here physical connectors, including subminiature version A (SMA) female connectors and terminal blocks are placed on the PCB to setup the connections with power supplies and oscilloscopes. SMA connectors are preferred among all signal interfaces due to its minimal size and a high degree of mechanical strength. Moreover, all surface mount capacitors and resistors are in 0805 size (2mm x 1.25mm), which would offer a much higher component density over through-hole components. The PCB layout illustrated in Figure 5.5 includes top-layer traces labeled in green and bottomlayer traces labeled in red. A plated-through hole is required at the site where two traces need to cross over each other. There are three different types of through-hole components mounted on PCB: single-pole double-throw switches, SMA female connectors and terminal blocks. In general, all through-hole connectors should be placed at the edge of board to accommodate external cable connections. The two buffers were constructed using BUF602 devices from Texas Instruments. Both the TL082 opamps and BUF602 buffers are in 8-pins small outline integrated circuit (SOIC-8) package with ±5V dual power supplies.

75 Chapter 5. OTA Testing Setup Testing Preparation PCB Assembly FIGURE 5.6: Assembled printed circuit board for DC gain and closed-loop measurement All surface-mount components are fairly small in size so they are supposed to be assembled first. Therefore, the PCB assembly starts with soldering all 0805 resistors and capacitors on board. As some capacitors are polarized tantalum capacitor with high voltage rating, the orientation for their placement should be carefully considered. Then, all ICs including the programmable amplifier, buffers and opamps are placed. The assembly process ends with putting all through-hole components on board. A photograph of the completed PCB is given in Figure 5.6. As illustrated in the figure, the circuit operation can be selected by branching switch1 and switch2 to a desired position. Depending on the circuit operation mode, the resistance of feedback resistors R1 and R2 needs to be adjusted as well.

76 Chapter 5. OTA Testing Setup Test Bench Setup FIGURE 5.7: Photograph of the test bench setup A set of five packaged CMOS chips containing the programmable OTA were returned from fabrication and one was configured on a PCB for unity-gain operation as depicted in Figure An HP 81130A digital pattern generator was used to program the chip according to Table 4.2, an Agilent 33220A function generator provided the input step and sinusoidal stimulus and an Agilent Infiniium 54830D oscilloscope captured the output signals. A photograph of the test bench setup is shown in Figure 5.7. Several miscellaneous procedures are taken during the measurement process. Sample averaging is turned on in the oscilloscope to maximize noise reduction. The operation of all DC power supplies should follow first on, last off principle to guarantee a valid path for electrostatic discharge. The matching impedance of the signal generator and oscilloscopes, which is 50ohms by default, needs to be reconfigured to high impedance. Lastly, all test equipments should be properly grounded so that they share the same signal ground as the reference for every sector in the test bench.