Two Step Timing Synchronization Scheme for OFDM Signal in General Purpose Processor Based Software Defined Radio Receiver

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1 Wireless Pers Commun (2014) 79: DOI /s Two Step Timing Synchronization Scheme for OFDM Signal in General Purpose Processor Based Software Defined Radio Receiver Yuki Tanaka Mamiko Inamori Yukitoshi Sanada Published online: 6 June 2014 Springer Science+Business Media New York 2014 Abstract Software defined radio (SDR) is a technology that allows a single terminal to support various kinds of wireless systems by changing its software to reconfigure itself. A general purpose processor (GPP) based SDR receiver platform named Sora has been recently developed by Microsoft. In the GPP based SDR receiver, timing synchronization of an OFDM signal consumes a significant amount of computational resources in the GPP. In this paper, a timing synchronization scheme which uses delayed correlation and matched filtering for the GPP based SDR platform is evaluated. The two stage timing synchronization scheme reduces the computational complexity by limiting the timing range of matched filtering. The proposed scheme reduces the amount of data transmission between the memory and the GPP of the SDR platform. It is shown through an experiment that the proposed scheme reduces the number of cycles for timing synchronization by up to 30 %. Keywords Software defined radio IEEE802.11g General purpose processors OFDM Timing synchronization 1 Introduction Many wireless communication technologies such as cellular systems or wireless local area networks have been standardized and developed in recent years. In need of seamless communications across those radio standards, the software defined radio (SDR) concept has received much attention among researchers working in mobile and personal wireless communications. Y. Tanaka M. Inamori Y. Sanada (B) Department of Electronics and Electrical Engineering, Keio University, Hiyoshi, Kohoku, Yokohama, Kanagawa , Japan sanada@elec.keio.ac.jp Y. Tanaka ytanaka@snd.elec.keio.ac.jp M. Inamori inamori@tokai-u.jp

2 364 Y. Tanaka et al. SDR is a technology that allows a single terminal to support various kinds of wireless systems by changing its software to reconfigure the wireless terminal [1,2]. In the SDR terminal, radio frequency (RF) circuits support multi-band signals and flexible baseband signal processing realizes a multi-standard and multi-mode system. As SDR platforms, FPGAs, DSPs, and general-purpose processors (GPPs) have been investigated [3 5]. The SDR receivers with FPGAs and DSPs are difficult to develop because they need specific programming skills [3]. Meanwhile, a SDR receiver on a GPP suffers from the limitation in the speed of signal processing [4 6]. A new platform for SDR, named Sora, has been developed recently. It has enough processing speed to demodulate IEEE802.11g WLAN signals[7]. For acceleration of signal processing speed, single-instruction-multiple-data (SIMD) is a promising scheme. In conventional SDR platforms using GPPs parallel processing has not been investigated explicitly [5,6]. Tan et al. [7] has investigated the efficiencies of SIMD and look up tables (LUTs) in a discrete Fourier transform (DFT) and a Viterbi algorithm. However, there are remaining fundamental demodulation processes that have not been improved with these schemes. Especially, timing synchronization of an OFDM signal consumes a significant amount of computational resources in the GPP [8]. In this paper, a demodulation experiment of the IEEE802.11g signal with the Sora platform is performed. Our focus is mainly on timing synchronization as it requires many multiplication and summation processes as well as a large amount of data transmission between the memory and the GPP. A two stage timing synchronization scheme applicable to the IEEE802.11g preamble format is also proposed and its computational complexity is evaluated. This scheme reduces the computational complexity by limiting the timing range of matched filtering. This paper is organized as follows. Our experiment system is explained in Sect. 2.Numerical results obtained through the experiment are shown in Sect. 3. Finally, conclusions are presented in Sect Experiment System 2.1 Measurement Setup Figure 1 illustrates the block diagram of the experiment system. The transmitter and the receiver are connected by a cable in this experiment system. An OFDM signal following the IEEE802.11g format is generated by the signal generator. Table 1 shows the specifications of the measurement equipment. The received signal is downconverted and digitized in the Sora radio control board (RCB). The digital samples are passed to the memories on the personal computer (PC). The PC picks up the stored samples and carries out carrier detection continuously. Channel (wired) Signal generator Fig. 1 Experiment system

3 Two Step Timing Synchronization Scheme 365 Table 1 Measurement Equipment ESG vector signal generator Agilent E4438C RF transceiver MAXIM MAX2829 A/D converter Analog devices AD9248 Processor Intel Core i7 930 Frequency: from 250 khz to 6 GHz Maximum output power: +17 dbm Frequency: GHz GHz Gain control range : 93 db Dynamic range: 60 db Speed: 20, 40, 65MS/s Resolution: 14 bit Clock: 2.8 GHz Core: quad core Table 2 Specifications of signal Bandwidth of the channel 20 MHz Center frequency of the channel GHz Modulation scheme OFDM Number of subcarriers 64 Number of data subcarriers 52 Long preamble duration 3.2 µs Short preamble duration 0.8 µs Guard interval 1.6 µs Symbol duration 3.2 µs Transmit power 20 dbm (with 20 db attenetor) 2.2 Transmit Signal In this experiment, the OFDM signal that follows the IEEE802.11g format is generated by the vector signal generator. The specifications of the OFDM signal used for the experiment are shown in Table 2 [9]. Figure 2 shows that the frame format of the transmit signal used in this experiment. This format corresponds to the short preamble frame mode of the IEEE802.11g standard. Although there exist 10 short preambles as specified in the standard, it is assumed that 7 short preamble symbols are used for detection of a carrier signal as well as adjustment of a RF front end and following analog circuits. Here, for simplicity, it is assumed that the adjustment process Fig. 2 Transmit signal format

4 366 Y. Tanaka et al. Fig. 3 Frequency response of transmit filter Fig. 4 Indoor Residential-A model 0-5 Energy of Path [db] Delay [ns] of the RF circuit is carried out during 7 short preamble symbols and analog digital (A/D) conversion starts from the 8th short preamble symbol [10]. One OFDM data symbol is sent followed by 3 short preamble symbols, 1 guard interval, and 2 long preamble symbols. The OFDM signal is generated with the clock speed of 20 MHz and is upsampled to 40 MHz. After upsampling, the signal passes through a transmit filter that satisfies the IEEE802.11g spectrum mask. The frequency response of the filter is shown in Fig. 3. The AWGN channel and indoor multipath fading channels are assumed [11]. The delay profiles of the Indoor Residential-A model and the Indoor Office-B model employed in the experiment are shown in Figs. 4 and 5, respectively. Finally, the filtered signal is transmitted in 2.4 GHz band from the signal generator. 2.3 Signal Processing in Receiver The block diagram of the receiver programmed on the PC is shown in Fig. 6. DCoffset of the received signal is first removed and timing synchronization is carried out. Frequency offset of the received signal is estimated and removed with the short preamble symbols and the long preamble symbols as coarse and fine frequency synchronization processes. After

5 Two Step Timing Synchronization Scheme 367 Fig. 5 Indoor Office-B model 0-5 Energy of Path [db] Delay [ns] Fig. 6 Block diagram of signal processing in receiver downsampling, the OFDM signal passes through a DFT block. The data symbol is then demodulated after channel estimation and equalization on each subcarrier DC Offset Cancellation The DC offset of the received signal is estimated with the following equation. Nn=1 y[n] ô = (1) N where y[n] is the nth sample of the received signal and N is the number of the samples available for averaging. The averaging is carried out every 512 samples, i.e. N = 512. DC offset cancellation can be carried out by subtracting ô from the received samples as follows. ŷ[n] =y[n] ô, n = 1, 2,...,N, (2) where ŷ[n] is the nth sample after DC offset cancellation Frequency Offset Cancellation Frequency offset is cancelled in two stages. First, coarse frequency offset estimation with the short preamble symbols is carried out. After coarse estimation, frequency offset is calculated with the long preamble symbols more accurately. The ith output of the correlator with the short preamble symbols can be expressed as

6 368 Y. Tanaka et al. in s 1 q[i] = ŷ[n]ss [n], i = 1, 2, 3 (3) n=(i 1)N s where s s [n] is the nth sample in the short preamble period, and N s is the length of one short preamble symbol. The coarse estimation of frequency offset, α s, is given as α s = 1 ( q [1]q[2]+q ) [2]q[3] arg. (4) 2π N s 2 In this way, the coarse estimation of frequency offset is obtained and tentative cancellation is carried out to the long preamble symbols and data symbols as follows. ỹ[n] =ŷ[n] exp ( j2πα s n), n = 3N s + N GI,... (5) where ỹ[n] is the nth received sample after the tentative cancellation of frequency offset. Next, the ith output of the correlator with the long preamble symbols can be expressed as in l +3N s +N GI 1 Q[i] = ŷ[n]sl [n], i = 1, 2 (6) n=(i 1)N l +3N s +N GI where s l [n] is the nth sample in the long preamble, and N l is the length of one long preamble symbol. Fine estimation of frequency offset with the long preamble symbols, α l, is calculated as α l = 1 arg ( Q [1]Q[2] ). (7) 2π N l Finally, the residual frequency offset is removed. ỹ[n] =ỹ[n] exp ( j2πα l n), n = 3N s + N GI,... (8) Channel Equalization and Demodulation After timing synchronization and frequency offset compensation, the received signal is downsampled with the ratio of 2. Following the downsampling, those samples are put into the DFT block. The long preamble symbols are used for channel estimation. The received signal on the kth subcarrier is given as the following equation. Z[k] =H[k]S L [k]+w [k]. (9) where Z[k] is the received signal, H[k] is the channel response, S L [k] is the symbol in the long preamble period, and W [k] is the noise on the kth subcarrier, respectively. The channel estimation is carried out as Ĥ[k] =Z[k]S L 1 [k] =H[k]+W [k]s L 1 [k]. (10) Two long preambles are used for channel estimation through averaging the estimation results. The channel is equalized with a Zero-Forcing algorithm and the bit error rate is measured. The demodulated symbol on the kth subcarrier after channel equalization is given as Ŝ L [k] =Ĥ 1 [k]z[k]. (11)

7 Two Step Timing Synchronization Scheme 369 Fig. 7 Conventional timing synchronization 2.4 Timing Synchronization Conventional Timing Synchronization Scheme The conventional timing synchronization scheme employs matched filtering to the short preamble symbols as shown in Fig. 7 [12]. The filter length is 3 short preamble symbol duration and the timing range of matched filtering is the whole preamble sequences. The peak output of the matched filter is detected as the synchronization timing. The matched filtering consumes a large amount of computational resources [8]. It also requires a large amount of data transmission between the memory and the GPP for the multiplication and summation processes in the matched filter Proposed Timing Synchronization Scheme Figure 8 shows the proposed timing synchronization scheme. The proposed timing synchronization scheme has two stages, (a) coarse synchronization stage with delayed correlation and (b) fine synchronization with matched filtering. In the coarse synchronization stage, the guard interval of the long preamble is used for delayed correlation as shown in Fig. 9 [13]. The delay is set to 2 long preamble symbol duration so that only one peak appears at the output of the correlator. The output of the correlator is put into the peak detector. The correlator output is calculated as follows. The nth output of the correlator, p[n], is given as N GI p[n] = ŷ[n + i 1]ŷ [n + i 1 + 2T ] (12) i=1 where N GI is the duration of the guard interval and T is the long preamble length. The calculation of Eq. (3) requires a large amount of data transmission between the memory and the GPP in the summation process. Therefore, the correlator output is updated with the previous output, p[n], as follows. p[n + 1] =p[n]+ŷ[n + i + N GI 1] ŷ [n + i + N GI 1 + 2T ] ŷ[n + i 1]ŷ [n + i 1 + 2T ]. (13) In this way, only 2 multiplication results [the second and third terms in the right side of Eq. (4)] are transferred over the bus for each correlator output. The coarse frame timing is then determined by peak detection. Since the correlator outputs a triangular waveform with the width of 2N GI asshowninfig.8a, coarse timing synchronization is realized. In the

8 370 Y. Tanaka et al. (a) (b) Fig. 8 Proposed synchronization scheme. a Coarse timing synchronization. b Fine timing synchronization Fig. 9 Block diagram of delayed correlator fine timing estimation stage, based on the coarse frame timing, matched filtering to the short preamble symbols are carried out. The matched filtering period is limited to 3 short preamble sequences plus 20 samples and the computational complexity of the proposed scheme is reduced. 3 Measurement Results Table 3 shows the number of cycles for individual demodulation processes. The number of data symbols is 1 in Table 3. The number of cycles for timing synchronization with the proposed scheme is reduced by 30 % compared to the conventional scheme. The relationship between the synchronization probability and E b /N 0 on AWGN, Indoor Residential-A, and Indoor Office-B channel models are shown in Figs. 10, 11 and 12. For the measurement of synchronization probability a pseudo noise sequence of length 127 is appended prior to

9 Two Step Timing Synchronization Scheme 371 Table 3 Comparison of performance (1 data symbol) Part of process Conventional (kcycles) Proposed (kcycles) DC offset cancellation Timing synchronization Frequency offset Channel estimation Demodulation Others (including DFT) Total cycles Fig. 10 Synchronization probability versus E b /N 0, (AWGN channel) Synchronization Probability Delayed Correlation Matched Filtering Proposed Scheme Eb/N0(dB) Fig. 11 Synchronization probability versus E b /N 0, (Indoor Residential-A channel) Synchronization Probability Delayed Correlation 0.75 Matched Filtering Proposed Scheme Eb/N0(dB) the OFDM frame to give the reference synchronization timing point. In the measurements with the multipath fading channel models, the synchronization range is set to ±300ns to the reference[10]. In the figures, Delayed Correlation refers to the synchronization scheme

10 372 Y. Tanaka et al. Fig. 12 Synchronization probability versus E b /N 0, (Indoor Office-B channel) Synchronization Probability Delayed Correlation 0.75 Matched Filtering Proposed Scheme Eb/N0(dB) BER Delayed Correlation Matched Filtering Proposed Scheme Theory Eb/N0(dB) Fig. 13 BER versus E b /N 0, (AWGN channel) with the delayed correlation to the long preamble symbols. Matched filtering implies the conventional scheme that uses a matched filter to the received signal. From these figures, the conventional scheme achieves the synchronization probability of close to 1 while the correlation based scheme shows the probability of less than 0.9 in the low E b /N 0 region. On the other hand, the proposed scheme shows almost the same performance as the conventional scheme in the practical E b /N 0 ranges. The relationship between the BER performance curves with three timing synchronization schemes on the AWGN channel are shown in Fig. 13. The demodulated symbols after timing synchronization is achieved is counted in the BER performance. In this figure, the conventional and proposed synchronization schemes realize the equivalent BER performance that has 0.5 db degradation from the theoretical one. On the other hand, the correlator based scheme shows 1.0 db degradation compared with the theoretical performance.

11 Two Step Timing Synchronization Scheme Conclusions In this paper, the timing synchronization scheme for the GPP based SDR platform has been proposed. In the proposed synchronization scheme, the delayed correlation of the long preamble symbol is calculated for coarse timing synchronization. Following the coarse timing estimation, matched filtering is carried to the limited received samples compared with the conventional scheme. The proposed scheme reduces the amount of data transmission between the memory and the GPP. It has been shown through the experiment that the proposed scheme keeps the synchronization probability and reduces the total number of cycles for timing synchronization by approximately 30 %. It has also been clarified that on the Indoor Residential-A channel model and the Indoor Office-B channel model the proposed scheme shows almost the same performance as the conventional scheme despite the reduced complexity of the proposed scheme. Acknowledgments This work is supported in part by a Grant-in-Aid for Scientific Research (C) under Grant No from the Ministry of Education, Culture, Sports, Science, and Technology of Japan. References 1. Mitola, J. (1995). The software radio architecture. IEEE Communicational Magazine, 33(5), Tsurumi, H., & Suzuki, Y. (1999). Broadband RF stage architecture for software-defined radio in handheld terminal applications. IEEE, Communications Magazine, 37(2), Cummings, M., & Haruyama, S. (Feb. 1999). FPGA in the software radio. IEEE, Communications Magazine, 37(2), Schmid, T., Sekkat, O., & Srivastava, M. B. (2007). An experimental study of network performance impact of increased latency in software defined radio. In WiNETCH 07 (pp ), January Khurram, M. (2006). A general purpose processor based IEEE802.11a compatible OFDM receiver design. In IEEE, GCC conference (pp. 1 5), March Bose, V., Ismert, M., Welborn, M., & Guttag, J. (1999). Virtual radios. IEEE Journal on Selected Areas in Communications, 17(4), Tan, K., Zhang, J., Fang, J., Liu, H., Ye, Y., Wang, S., et al. (2011). Sora: High performance software radio using general purpose multi-core processors. Communications of the Association for Computing Machinery, 54(1), Tan, K.,Liu, H., Fang, J., Wang, W., Zhang, J., Chen, M.,& Voelker, G.M. (2009). Sora: High performance software radio using general purpose multi-core processors. In The 6th USENIX symposium on networked systems design and implementation, April IEEE g-Part 11: Wireless LAN medium access control (MAC) and physical layer (PHY) specifications; high-speed physical layer in the 2.4GHZ band. 10. Yip, K.-W., Wu, Y.-C., & Ng, T.-S. (Feb. 2003). Design of multiplierless correlators for timing synchronization in IEEE a wireless LANs. IEEE, Transaction on Consumer Electronics, 49(1), Joint Technical Committee of Committee T1 R1P1.4 and TIA TR46.3.3/TR on Wireless Access. (1994). Draft final report on RF channel characterization. Paper no. JTC(AIR)/ R4, January Tan, K., & Sora Core Team. (2011). The Sora manual version 1.5. No. MSR-TR , September Heiskala, J., & Terry, J. (2001). OFDM wireless LANs: A theoretical and practical guide. Indianapolis: Sams Publishing.

374 Y. Tanaka et al. Yuki Tanaka was born in Hyogo, Japan in 1986. He received his B.E. degree in electronics engineering from Keio University, Japan in 2012.

His research interests are mainly concentrated on software defined radio. Mamiko Inamori was born in Kagoshima, Japan in 1982. She received her B.E., M.E., and Ph.

She received the Young Scientist Award from Ericsson Japan in 2010. Her research interests are mainly concentrated on software defined radio. Yukitoshi Sanada was born in Tokyo in 1969.

12 374 Y. Tanaka et al. Yuki Tanaka was born in Hyogo, Japan in He received his B.E. degree in electronics engineering from Keio University, Japan in Since April 2012, he has been a graduate student in School of Integrated Design Engineering, Graduate School of Science and Technology, Keio University. His research interests are mainly concentrated on software defined radio. Mamiko Inamori was born in Kagoshima, Japan in She received her B.E., M.E., and Ph.D degrees in electronics engineering from Keio University, Japan in 2005, 2007, and 2009, respectively. Since October 2009, she has been an assistant professor in Keio University. She received the Young Scientist Award from Ericsson Japan in Her research interests are mainly concentrated on software defined radio. Yukitoshi Sanada was born in Tokyo in He received his B.E. degree in electrical engineering from Keio University, Yokohama Japan, his M.A.Sc. degree in electrical engineering from the University of Victoria, B.C., Canada, and his Ph.D. degree in electrical engineering from Keio University, Yokohama Japan, in 1992, 1995, and 1997, respectively. In 1997 he joined the Faculty of Engineering, Tokyo Institute of Technology as a Research Associate. In 2000 he joined Advanced Telecommunication Laboratory, Sony Computer Science Laboratories, Inc, as an associate researcher. In 2001 he joined Faculty of Science and Engineering, Keio University, where he is now a professor. He received the Young Engineer Award from IEICE Japan in His current research interest are in software defined radio, cognitive radio, and OFDM systems.

Experimental Investigation of IEEE802.11n Reception with Fractional Sampling

21st Annual IEEE International Symposium on Personal, Indoor and Mobile Radio Communications Experimental Investigation of IEEE802.11n Reception with Fractional Sampling Ryosuke Nakamura, Yukitoshi Sanada